* Re: [PATCH v1] ibmvnic: remove excessive irqsave
From: Lijun Pan @ 2021-03-05 17:24 UTC (permalink / raw)
To: angkery
Cc: Junlin Yang, linux-kernel, Jakub Kicinski, netdev, Lijun Pan,
Dany Madden, paulus, Sukadev Bhattiprolu, linuxppc-dev,
David Miller
In-Reply-To: <20210305084839.2405-1-angkery@163.com>
[-- Attachment #1: Type: text/html, Size: 4281 bytes --]
^ permalink raw reply
* [PATCH] KVM: PPC: Book3S HV: Do not expose HFSCR sanitisation to nested hypervisor
From: Fabiano Rosas @ 2021-03-05 23:10 UTC (permalink / raw)
To: kvm-ppc; +Cc: linuxppc-dev, npiggin
As one of the arguments of the H_ENTER_NESTED hypercall, the nested
hypervisor (L1) prepares a structure containing the values of various
hypervisor-privileged registers with which it wants the nested guest
(L2) to run. Since the nested HV runs in supervisor mode it needs the
host to write to these registers.
To stop a nested HV manipulating this mechanism and using a nested
guest as a proxy to access a facility that has been made unavailable
to it, we have a routine that sanitises the values of the HV registers
before copying them into the nested guest's vcpu struct.
However, when coming out of the guest the values are copied as they
were back into L1 memory, which means that any sanitisation we did
during guest entry will be exposed to L1 after H_ENTER_NESTED returns.
This is not a problem by itself, but in the case of the Hypervisor
Facility Status and Control Register (HFSCR), we use the intersection
between L2 hfscr bits and L1 hfscr bits. That means that L1 could use
this to indirectly read the (hv-privileged) value from its vcpu
struct.
This patch fixes this by making sure that L1 only gets back the bits
that are necessary for regular functioning.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
arch/powerpc/kvm/book3s_hv_nested.c | 22 +++++++++++++++++-----
1 file changed, 17 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/kvm/book3s_hv_nested.c b/arch/powerpc/kvm/book3s_hv_nested.c
index 0cd0e7aad588..860004f46e08 100644
--- a/arch/powerpc/kvm/book3s_hv_nested.c
+++ b/arch/powerpc/kvm/book3s_hv_nested.c
@@ -98,12 +98,20 @@ static void byteswap_hv_regs(struct hv_guest_state *hr)
}
static void save_hv_return_state(struct kvm_vcpu *vcpu, int trap,
- struct hv_guest_state *hr)
+ struct hv_guest_state *hr, u64 saved_hfscr)
{
struct kvmppc_vcore *vc = vcpu->arch.vcore;
+ /*
+ * During sanitise_hv_regs() we used HFSCR bits from L1 state
+ * to restrict what the L2 state is allowed to be. Since L1 is
+ * not allowed to read this SPR, do not include these
+ * modifications in the return state.
+ */
+ hr->hfscr = ((~HFSCR_INTR_CAUSE & saved_hfscr) |
+ (HFSCR_INTR_CAUSE & vcpu->arch.hfscr));
+
hr->dpdes = vc->dpdes;
- hr->hfscr = vcpu->arch.hfscr;
hr->purr = vcpu->arch.purr;
hr->spurr = vcpu->arch.spurr;
hr->ic = vcpu->arch.ic;
@@ -132,12 +140,14 @@ static void save_hv_return_state(struct kvm_vcpu *vcpu, int trap,
}
}
-static void sanitise_hv_regs(struct kvm_vcpu *vcpu, struct hv_guest_state *hr)
+static void sanitise_hv_regs(struct kvm_vcpu *vcpu, struct hv_guest_state *hr,
+ u64 *saved_hfscr)
{
/*
* Don't let L1 enable features for L2 which we've disabled for L1,
* but preserve the interrupt cause field.
*/
+ *saved_hfscr = hr->hfscr;
hr->hfscr &= (HFSCR_INTR_CAUSE | vcpu->arch.hfscr);
/* Don't let data address watchpoint match in hypervisor state */
@@ -272,6 +282,7 @@ long kvmhv_enter_nested_guest(struct kvm_vcpu *vcpu)
u64 hdec_exp;
s64 delta_purr, delta_spurr, delta_ic, delta_vtb;
u64 mask;
+ u64 hfscr;
unsigned long lpcr;
if (vcpu->kvm->arch.l1_ptcr == 0)
@@ -324,7 +335,8 @@ long kvmhv_enter_nested_guest(struct kvm_vcpu *vcpu)
mask = LPCR_DPFD | LPCR_ILE | LPCR_TC | LPCR_AIL | LPCR_LD |
LPCR_LPES | LPCR_MER;
lpcr = (vc->lpcr & ~mask) | (l2_hv.lpcr & mask);
- sanitise_hv_regs(vcpu, &l2_hv);
+
+ sanitise_hv_regs(vcpu, &l2_hv, &hfscr);
restore_hv_regs(vcpu, &l2_hv);
vcpu->arch.ret = RESUME_GUEST;
@@ -345,7 +357,7 @@ long kvmhv_enter_nested_guest(struct kvm_vcpu *vcpu)
delta_spurr = vcpu->arch.spurr - l2_hv.spurr;
delta_ic = vcpu->arch.ic - l2_hv.ic;
delta_vtb = vc->vtb - l2_hv.vtb;
- save_hv_return_state(vcpu, vcpu->arch.trap, &l2_hv);
+ save_hv_return_state(vcpu, vcpu->arch.trap, &l2_hv, hfscr);
/* restore L1 state */
vcpu->arch.nested = NULL;
--
2.29.2
^ permalink raw reply related
* Re: cleanup unused or almost unused IOMMU APIs and the FSL PAMU driver
From: Li Yang @ 2021-03-06 0:03 UTC (permalink / raw)
To: Christoph Hellwig
Cc: kvm, Will Deacon, Joerg Roedel, linuxppc-dev, dri-devel,
virtualization, Linux IOMMU,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, Netdev,
freedreno, David Woodhouse, linux-arm-msm, Lu Baolu
In-Reply-To: <20210301084257.945454-1-hch@lst.de>
On Mon, Mar 1, 2021 at 2:44 AM Christoph Hellwig <hch@lst.de> wrote:
>
> Hi all,
>
> there are a bunch of IOMMU APIs that are entirely unused, or only used as
> a private communication channel between the FSL PAMU driver and it's only
> consumer, the qbman portal driver.
>
> So this series drops a huge chunk of entirely unused FSL PAMU
> functionality, then drops all kinds of unused IOMMU APIs, and then
> replaces what is left of the iommu_attrs with properly typed, smaller
> and easier to use specific APIs.
It looks like the unused APIs were added for functionality that were
never completed later on. So
Acked-by: Li Yang <leoyang.li@nxp.com>
>
> Diffstat:
> arch/powerpc/include/asm/fsl_pamu_stash.h | 12
> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2
> drivers/iommu/amd/iommu.c | 23
> drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 85 ---
> drivers/iommu/arm/arm-smmu/arm-smmu.c | 122 +---
> drivers/iommu/dma-iommu.c | 8
> drivers/iommu/fsl_pamu.c | 264 ----------
> drivers/iommu/fsl_pamu.h | 10
> drivers/iommu/fsl_pamu_domain.c | 694 ++--------------------------
> drivers/iommu/fsl_pamu_domain.h | 46 -
> drivers/iommu/intel/iommu.c | 55 --
> drivers/iommu/iommu.c | 75 ---
> drivers/soc/fsl/qbman/qman_portal.c | 56 --
> drivers/vfio/vfio_iommu_type1.c | 31 -
> drivers/vhost/vdpa.c | 10
> include/linux/iommu.h | 81 ---
> 16 files changed, 214 insertions(+), 1360 deletions(-)
^ permalink raw reply
* [PATCH v1 0/3] Remove qe_io{read,write}* IO accessors
From: Christophe Leroy @ 2021-03-06 18:09 UTC (permalink / raw)
To: Qiang Zhao, Li Yang, Rasmus Villemoes, Timur Tabi,
Greg Kroah-Hartman, Jiri Slaby
Cc: linuxppc-dev, linux-kernel, linux-arm-kernel, linux-serial
Commit 6ac9b61786cc ("soc: fsl: qe: introduce qe_io{read,write}*
wrappers") added specific I/O accessors for qe because at that
time ioread/iowrite functions were sub-optimal on powerpc/32
compared to the architecture specific in_/out_ IO accessors.
But as ioread/iowrite accessors are now equivalent since
commit 894fa235eb4c ("powerpc: inline iomap accessors"),
use them in order to allow removal of the qe specific ones.
Christophe Leroy (3):
soc: fsl: qe: replace qe_io{read,write}* wrappers by generic
io{read,write}*
tty: serial: ucc_uart: replace qe_io{read,write}* wrappers by generic
io{read,write}*
Revert "soc: fsl: qe: introduce qe_io{read,write}* wrappers"
drivers/soc/fsl/qe/gpio.c | 20 +++---
drivers/soc/fsl/qe/qe.c | 24 +++----
drivers/soc/fsl/qe/qe_ic.c | 4 +-
drivers/soc/fsl/qe/qe_io.c | 36 +++++-----
drivers/soc/fsl/qe/ucc_fast.c | 68 +++++++++----------
drivers/soc/fsl/qe/ucc_slow.c | 42 ++++++------
drivers/tty/serial/ucc_uart.c | 124 +++++++++++++++++-----------------
include/soc/fsl/qe/qe.h | 34 +++-------
8 files changed, 168 insertions(+), 184 deletions(-)
--
2.25.0
^ permalink raw reply
* [PATCH v1 3/3] Revert "soc: fsl: qe: introduce qe_io{read,write}* wrappers"
From: Christophe Leroy @ 2021-03-06 18:09 UTC (permalink / raw)
To: Qiang Zhao, Li Yang, Rasmus Villemoes, Timur Tabi,
Greg Kroah-Hartman, Jiri Slaby
Cc: linuxppc-dev, linux-kernel, linux-arm-kernel, linux-serial
In-Reply-To: <cover.1615053848.git.christophe.leroy@csgroup.eu>
This reverts commit 6ac9b61786cc64ae5cbfb69413137656f72e8204.
This commit was required because at that time, ioread/iowrite
functions were sub-optimal on powerpc/32 compared to the
architecture specific in_/out_ IO accessors.
But there are now equivalent since
commit 894fa235eb4c ("powerpc: inline iomap accessors").
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
---
include/soc/fsl/qe/qe.h | 34 +++++++++-------------------------
1 file changed, 9 insertions(+), 25 deletions(-)
diff --git a/include/soc/fsl/qe/qe.h b/include/soc/fsl/qe/qe.h
index 4925a1b59dc9..b02e9fe69146 100644
--- a/include/soc/fsl/qe/qe.h
+++ b/include/soc/fsl/qe/qe.h
@@ -239,37 +239,21 @@ static inline int qe_alive_during_sleep(void)
#define qe_muram_dma cpm_muram_dma
#define qe_muram_free_addr cpm_muram_free_addr
-#ifdef CONFIG_PPC32
-#define qe_iowrite8(val, addr) out_8(addr, val)
-#define qe_iowrite16be(val, addr) out_be16(addr, val)
-#define qe_iowrite32be(val, addr) out_be32(addr, val)
-#define qe_ioread8(addr) in_8(addr)
-#define qe_ioread16be(addr) in_be16(addr)
-#define qe_ioread32be(addr) in_be32(addr)
-#else
-#define qe_iowrite8(val, addr) iowrite8(val, addr)
-#define qe_iowrite16be(val, addr) iowrite16be(val, addr)
-#define qe_iowrite32be(val, addr) iowrite32be(val, addr)
-#define qe_ioread8(addr) ioread8(addr)
-#define qe_ioread16be(addr) ioread16be(addr)
-#define qe_ioread32be(addr) ioread32be(addr)
-#endif
-
-#define qe_setbits_be32(_addr, _v) qe_iowrite32be(qe_ioread32be(_addr) | (_v), (_addr))
-#define qe_clrbits_be32(_addr, _v) qe_iowrite32be(qe_ioread32be(_addr) & ~(_v), (_addr))
+#define qe_setbits_be32(_addr, _v) iowrite32be(ioread32be(_addr) | (_v), (_addr))
+#define qe_clrbits_be32(_addr, _v) iowrite32be(ioread32be(_addr) & ~(_v), (_addr))
-#define qe_setbits_be16(_addr, _v) qe_iowrite16be(qe_ioread16be(_addr) | (_v), (_addr))
-#define qe_clrbits_be16(_addr, _v) qe_iowrite16be(qe_ioread16be(_addr) & ~(_v), (_addr))
+#define qe_setbits_be16(_addr, _v) iowrite16be(ioread16be(_addr) | (_v), (_addr))
+#define qe_clrbits_be16(_addr, _v) iowrite16be(ioread16be(_addr) & ~(_v), (_addr))
-#define qe_setbits_8(_addr, _v) qe_iowrite8(qe_ioread8(_addr) | (_v), (_addr))
-#define qe_clrbits_8(_addr, _v) qe_iowrite8(qe_ioread8(_addr) & ~(_v), (_addr))
+#define qe_setbits_8(_addr, _v) iowrite8(ioread8(_addr) | (_v), (_addr))
+#define qe_clrbits_8(_addr, _v) iowrite8(ioread8(_addr) & ~(_v), (_addr))
#define qe_clrsetbits_be32(addr, clear, set) \
- qe_iowrite32be((qe_ioread32be(addr) & ~(clear)) | (set), (addr))
+ iowrite32be((ioread32be(addr) & ~(clear)) | (set), (addr))
#define qe_clrsetbits_be16(addr, clear, set) \
- qe_iowrite16be((qe_ioread16be(addr) & ~(clear)) | (set), (addr))
+ iowrite16be((ioread16be(addr) & ~(clear)) | (set), (addr))
#define qe_clrsetbits_8(addr, clear, set) \
- qe_iowrite8((qe_ioread8(addr) & ~(clear)) | (set), (addr))
+ iowrite8((ioread8(addr) & ~(clear)) | (set), (addr))
/* Structure that defines QE firmware binary files.
*
--
2.25.0
^ permalink raw reply related
* [PATCH v1 2/3] tty: serial: ucc_uart: replace qe_io{read,write}* wrappers by generic io{read,write}*
From: Christophe Leroy @ 2021-03-06 18:09 UTC (permalink / raw)
To: Qiang Zhao, Li Yang, Rasmus Villemoes, Timur Tabi,
Greg Kroah-Hartman, Jiri Slaby
Cc: linuxppc-dev, linux-kernel, linux-arm-kernel, linux-serial
In-Reply-To: <cover.1615053848.git.christophe.leroy@csgroup.eu>
Commit 6ac9b61786cc ("soc: fsl: qe: introduce qe_io{read,write}*
wrappers") added specific I/O accessors for qe because at that
time ioread/iowrite functions were sub-optimal on powerpc/32
compared to the architecture specific in_/out_ IO accessors.
But as ioread/iowrite accessors are now equivalent since
commit 894fa235eb4c ("powerpc: inline iomap accessors"),
use them in order to allow removal of the qe specific ones.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
---
drivers/tty/serial/ucc_uart.c | 124 +++++++++++++++++-----------------
1 file changed, 62 insertions(+), 62 deletions(-)
diff --git a/drivers/tty/serial/ucc_uart.c b/drivers/tty/serial/ucc_uart.c
index d6a8604157ab..f81261cb52b8 100644
--- a/drivers/tty/serial/ucc_uart.c
+++ b/drivers/tty/serial/ucc_uart.c
@@ -261,11 +261,11 @@ static unsigned int qe_uart_tx_empty(struct uart_port *port)
struct qe_bd *bdp = qe_port->tx_bd_base;
while (1) {
- if (qe_ioread16be(&bdp->status) & BD_SC_READY)
+ if (ioread16be(&bdp->status) & BD_SC_READY)
/* This BD is not done, so return "not done" */
return 0;
- if (qe_ioread16be(&bdp->status) & BD_SC_WRAP)
+ if (ioread16be(&bdp->status) & BD_SC_WRAP)
/*
* This BD is done and it's the last one, so return
* "done"
@@ -344,10 +344,10 @@ static int qe_uart_tx_pump(struct uart_qe_port *qe_port)
p = qe2cpu_addr(be32_to_cpu(bdp->buf), qe_port);
*p++ = port->x_char;
- qe_iowrite16be(1, &bdp->length);
+ iowrite16be(1, &bdp->length);
qe_setbits_be16(&bdp->status, BD_SC_READY);
/* Get next BD. */
- if (qe_ioread16be(&bdp->status) & BD_SC_WRAP)
+ if (ioread16be(&bdp->status) & BD_SC_WRAP)
bdp = qe_port->tx_bd_base;
else
bdp++;
@@ -366,7 +366,7 @@ static int qe_uart_tx_pump(struct uart_qe_port *qe_port)
/* Pick next descriptor and fill from buffer */
bdp = qe_port->tx_cur;
- while (!(qe_ioread16be(&bdp->status) & BD_SC_READY) &&
+ while (!(ioread16be(&bdp->status) & BD_SC_READY) &&
(xmit->tail != xmit->head)) {
count = 0;
p = qe2cpu_addr(be32_to_cpu(bdp->buf), qe_port);
@@ -379,11 +379,11 @@ static int qe_uart_tx_pump(struct uart_qe_port *qe_port)
break;
}
- qe_iowrite16be(count, &bdp->length);
+ iowrite16be(count, &bdp->length);
qe_setbits_be16(&bdp->status, BD_SC_READY);
/* Get next BD. */
- if (qe_ioread16be(&bdp->status) & BD_SC_WRAP)
+ if (ioread16be(&bdp->status) & BD_SC_WRAP)
bdp = qe_port->tx_bd_base;
else
bdp++;
@@ -416,7 +416,7 @@ static void qe_uart_start_tx(struct uart_port *port)
container_of(port, struct uart_qe_port, port);
/* If we currently are transmitting, then just return */
- if (qe_ioread16be(&qe_port->uccp->uccm) & UCC_UART_UCCE_TX)
+ if (ioread16be(&qe_port->uccp->uccm) & UCC_UART_UCCE_TX)
return;
/* Otherwise, pump the port and start transmission */
@@ -471,14 +471,14 @@ static void qe_uart_int_rx(struct uart_qe_port *qe_port)
*/
bdp = qe_port->rx_cur;
while (1) {
- status = qe_ioread16be(&bdp->status);
+ status = ioread16be(&bdp->status);
/* If this one is empty, then we assume we've read them all */
if (status & BD_SC_EMPTY)
break;
/* get number of characters, and check space in RX buffer */
- i = qe_ioread16be(&bdp->length);
+ i = ioread16be(&bdp->length);
/* If we don't have enough room in RX buffer for the entire BD,
* then we try later, which will be the next RX interrupt.
@@ -512,7 +512,7 @@ static void qe_uart_int_rx(struct uart_qe_port *qe_port)
qe_clrsetbits_be16(&bdp->status,
BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV | BD_SC_ID,
BD_SC_EMPTY);
- if (qe_ioread16be(&bdp->status) & BD_SC_WRAP)
+ if (ioread16be(&bdp->status) & BD_SC_WRAP)
bdp = qe_port->rx_bd_base;
else
bdp++;
@@ -569,8 +569,8 @@ static irqreturn_t qe_uart_int(int irq, void *data)
u16 events;
/* Clear the interrupts */
- events = qe_ioread16be(&uccp->ucce);
- qe_iowrite16be(events, &uccp->ucce);
+ events = ioread16be(&uccp->ucce);
+ iowrite16be(events, &uccp->ucce);
if (events & UCC_UART_UCCE_BRKE)
uart_handle_break(&qe_port->port);
@@ -601,17 +601,17 @@ static void qe_uart_initbd(struct uart_qe_port *qe_port)
bdp = qe_port->rx_bd_base;
qe_port->rx_cur = qe_port->rx_bd_base;
for (i = 0; i < (qe_port->rx_nrfifos - 1); i++) {
- qe_iowrite16be(BD_SC_EMPTY | BD_SC_INTRPT, &bdp->status);
- qe_iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
- qe_iowrite16be(0, &bdp->length);
+ iowrite16be(BD_SC_EMPTY | BD_SC_INTRPT, &bdp->status);
+ iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
+ iowrite16be(0, &bdp->length);
bd_virt += qe_port->rx_fifosize;
bdp++;
}
/* */
- qe_iowrite16be(BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT, &bdp->status);
- qe_iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
- qe_iowrite16be(0, &bdp->length);
+ iowrite16be(BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT, &bdp->status);
+ iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
+ iowrite16be(0, &bdp->length);
/* Set the physical address of the host memory
* buffers in the buffer descriptors, and the
@@ -622,9 +622,9 @@ static void qe_uart_initbd(struct uart_qe_port *qe_port)
qe_port->tx_cur = qe_port->tx_bd_base;
bdp = qe_port->tx_bd_base;
for (i = 0; i < (qe_port->tx_nrfifos - 1); i++) {
- qe_iowrite16be(BD_SC_INTRPT, &bdp->status);
- qe_iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
- qe_iowrite16be(0, &bdp->length);
+ iowrite16be(BD_SC_INTRPT, &bdp->status);
+ iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
+ iowrite16be(0, &bdp->length);
bd_virt += qe_port->tx_fifosize;
bdp++;
}
@@ -634,9 +634,9 @@ static void qe_uart_initbd(struct uart_qe_port *qe_port)
qe_setbits_be16(&qe_port->tx_cur->status, BD_SC_P);
#endif
- qe_iowrite16be(BD_SC_WRAP | BD_SC_INTRPT, &bdp->status);
- qe_iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
- qe_iowrite16be(0, &bdp->length);
+ iowrite16be(BD_SC_WRAP | BD_SC_INTRPT, &bdp->status);
+ iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
+ iowrite16be(0, &bdp->length);
}
/*
@@ -658,21 +658,21 @@ static void qe_uart_init_ucc(struct uart_qe_port *qe_port)
ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX);
/* Program the UCC UART parameter RAM */
- qe_iowrite8(UCC_BMR_GBL | UCC_BMR_BO_BE, &uccup->common.rbmr);
- qe_iowrite8(UCC_BMR_GBL | UCC_BMR_BO_BE, &uccup->common.tbmr);
- qe_iowrite16be(qe_port->rx_fifosize, &uccup->common.mrblr);
- qe_iowrite16be(0x10, &uccup->maxidl);
- qe_iowrite16be(1, &uccup->brkcr);
- qe_iowrite16be(0, &uccup->parec);
- qe_iowrite16be(0, &uccup->frmec);
- qe_iowrite16be(0, &uccup->nosec);
- qe_iowrite16be(0, &uccup->brkec);
- qe_iowrite16be(0, &uccup->uaddr[0]);
- qe_iowrite16be(0, &uccup->uaddr[1]);
- qe_iowrite16be(0, &uccup->toseq);
+ iowrite8(UCC_BMR_GBL | UCC_BMR_BO_BE, &uccup->common.rbmr);
+ iowrite8(UCC_BMR_GBL | UCC_BMR_BO_BE, &uccup->common.tbmr);
+ iowrite16be(qe_port->rx_fifosize, &uccup->common.mrblr);
+ iowrite16be(0x10, &uccup->maxidl);
+ iowrite16be(1, &uccup->brkcr);
+ iowrite16be(0, &uccup->parec);
+ iowrite16be(0, &uccup->frmec);
+ iowrite16be(0, &uccup->nosec);
+ iowrite16be(0, &uccup->brkec);
+ iowrite16be(0, &uccup->uaddr[0]);
+ iowrite16be(0, &uccup->uaddr[1]);
+ iowrite16be(0, &uccup->toseq);
for (i = 0; i < 8; i++)
- qe_iowrite16be(0xC000, &uccup->cchars[i]);
- qe_iowrite16be(0xc0ff, &uccup->rccm);
+ iowrite16be(0xC000, &uccup->cchars[i]);
+ iowrite16be(0xc0ff, &uccup->rccm);
/* Configure the GUMR registers for UART */
if (soft_uart) {
@@ -702,30 +702,30 @@ static void qe_uart_init_ucc(struct uart_qe_port *qe_port)
#endif
/* Disable rx interrupts and clear all pending events. */
- qe_iowrite16be(0, &uccp->uccm);
- qe_iowrite16be(0xffff, &uccp->ucce);
- qe_iowrite16be(0x7e7e, &uccp->udsr);
+ iowrite16be(0, &uccp->uccm);
+ iowrite16be(0xffff, &uccp->ucce);
+ iowrite16be(0x7e7e, &uccp->udsr);
/* Initialize UPSMR */
- qe_iowrite16be(0, &uccp->upsmr);
+ iowrite16be(0, &uccp->upsmr);
if (soft_uart) {
- qe_iowrite16be(0x30, &uccup->supsmr);
- qe_iowrite16be(0, &uccup->res92);
- qe_iowrite32be(0, &uccup->rx_state);
- qe_iowrite32be(0, &uccup->rx_cnt);
- qe_iowrite8(0, &uccup->rx_bitmark);
- qe_iowrite8(10, &uccup->rx_length);
- qe_iowrite32be(0x4000, &uccup->dump_ptr);
- qe_iowrite8(0, &uccup->rx_temp_dlst_qe);
- qe_iowrite32be(0, &uccup->rx_frame_rem);
- qe_iowrite8(0, &uccup->rx_frame_rem_size);
+ iowrite16be(0x30, &uccup->supsmr);
+ iowrite16be(0, &uccup->res92);
+ iowrite32be(0, &uccup->rx_state);
+ iowrite32be(0, &uccup->rx_cnt);
+ iowrite8(0, &uccup->rx_bitmark);
+ iowrite8(10, &uccup->rx_length);
+ iowrite32be(0x4000, &uccup->dump_ptr);
+ iowrite8(0, &uccup->rx_temp_dlst_qe);
+ iowrite32be(0, &uccup->rx_frame_rem);
+ iowrite8(0, &uccup->rx_frame_rem_size);
/* Soft-UART requires TX to be 1X */
- qe_iowrite8(UCC_UART_TX_STATE_UART | UCC_UART_TX_STATE_X1,
+ iowrite8(UCC_UART_TX_STATE_UART | UCC_UART_TX_STATE_X1,
&uccup->tx_mode);
- qe_iowrite16be(0, &uccup->tx_state);
- qe_iowrite8(0, &uccup->resD4);
- qe_iowrite16be(0, &uccup->resD5);
+ iowrite16be(0, &uccup->tx_state);
+ iowrite8(0, &uccup->resD4);
+ iowrite16be(0, &uccup->resD5);
/* Set UART mode.
* Enable receive and transmit.
@@ -850,9 +850,9 @@ static void qe_uart_set_termios(struct uart_port *port,
struct ucc_slow __iomem *uccp = qe_port->uccp;
unsigned int baud;
unsigned long flags;
- u16 upsmr = qe_ioread16be(&uccp->upsmr);
+ u16 upsmr = ioread16be(&uccp->upsmr);
struct ucc_uart_pram __iomem *uccup = qe_port->uccup;
- u16 supsmr = qe_ioread16be(&uccup->supsmr);
+ u16 supsmr = ioread16be(&uccup->supsmr);
u8 char_length = 2; /* 1 + CL + PEN + 1 + SL */
/* Character length programmed into the mode register is the
@@ -950,10 +950,10 @@ static void qe_uart_set_termios(struct uart_port *port,
/* Update the per-port timeout. */
uart_update_timeout(port, termios->c_cflag, baud);
- qe_iowrite16be(upsmr, &uccp->upsmr);
+ iowrite16be(upsmr, &uccp->upsmr);
if (soft_uart) {
- qe_iowrite16be(supsmr, &uccup->supsmr);
- qe_iowrite8(char_length, &uccup->rx_length);
+ iowrite16be(supsmr, &uccup->supsmr);
+ iowrite8(char_length, &uccup->rx_length);
/* Soft-UART requires a 1X multiplier for TX */
qe_setbrg(qe_port->us_info.rx_clock, baud, 16);
--
2.25.0
^ permalink raw reply related
* [PATCH v1 1/3] soc: fsl: qe: replace qe_io{read,write}* wrappers by generic io{read,write}*
From: Christophe Leroy @ 2021-03-06 18:09 UTC (permalink / raw)
To: Qiang Zhao, Li Yang, Rasmus Villemoes, Timur Tabi,
Greg Kroah-Hartman, Jiri Slaby
Cc: linuxppc-dev, linux-kernel, linux-arm-kernel, linux-serial
In-Reply-To: <cover.1615053848.git.christophe.leroy@csgroup.eu>
Commit 6ac9b61786cc ("soc: fsl: qe: introduce qe_io{read,write}*
wrappers") added specific I/O accessors for qe because at that
time ioread/iowrite functions were sub-optimal on powerpc/32
compared to the architecture specific in_/out_ IO accessors.
But as ioread/iowrite accessors are now equivalent since
commit 894fa235eb4c ("powerpc: inline iomap accessors"),
use them in order to allow removal of the qe specific ones.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
---
drivers/soc/fsl/qe/gpio.c | 20 +++++------
drivers/soc/fsl/qe/qe.c | 24 ++++++-------
drivers/soc/fsl/qe/qe_ic.c | 4 +--
drivers/soc/fsl/qe/qe_io.c | 36 +++++++++----------
drivers/soc/fsl/qe/ucc_fast.c | 68 +++++++++++++++++------------------
drivers/soc/fsl/qe/ucc_slow.c | 42 +++++++++++-----------
6 files changed, 97 insertions(+), 97 deletions(-)
diff --git a/drivers/soc/fsl/qe/gpio.c b/drivers/soc/fsl/qe/gpio.c
index ed75198ed254..99f7de43c3c6 100644
--- a/drivers/soc/fsl/qe/gpio.c
+++ b/drivers/soc/fsl/qe/gpio.c
@@ -41,13 +41,13 @@ static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)
container_of(mm_gc, struct qe_gpio_chip, mm_gc);
struct qe_pio_regs __iomem *regs = mm_gc->regs;
- qe_gc->cpdata = qe_ioread32be(®s->cpdata);
+ qe_gc->cpdata = ioread32be(®s->cpdata);
qe_gc->saved_regs.cpdata = qe_gc->cpdata;
- qe_gc->saved_regs.cpdir1 = qe_ioread32be(®s->cpdir1);
- qe_gc->saved_regs.cpdir2 = qe_ioread32be(®s->cpdir2);
- qe_gc->saved_regs.cppar1 = qe_ioread32be(®s->cppar1);
- qe_gc->saved_regs.cppar2 = qe_ioread32be(®s->cppar2);
- qe_gc->saved_regs.cpodr = qe_ioread32be(®s->cpodr);
+ qe_gc->saved_regs.cpdir1 = ioread32be(®s->cpdir1);
+ qe_gc->saved_regs.cpdir2 = ioread32be(®s->cpdir2);
+ qe_gc->saved_regs.cppar1 = ioread32be(®s->cppar1);
+ qe_gc->saved_regs.cppar2 = ioread32be(®s->cppar2);
+ qe_gc->saved_regs.cpodr = ioread32be(®s->cpodr);
}
static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio)
@@ -56,7 +56,7 @@ static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio)
struct qe_pio_regs __iomem *regs = mm_gc->regs;
u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);
- return !!(qe_ioread32be(®s->cpdata) & pin_mask);
+ return !!(ioread32be(®s->cpdata) & pin_mask);
}
static void qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
@@ -74,7 +74,7 @@ static void qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
else
qe_gc->cpdata &= ~pin_mask;
- qe_iowrite32be(qe_gc->cpdata, ®s->cpdata);
+ iowrite32be(qe_gc->cpdata, ®s->cpdata);
spin_unlock_irqrestore(&qe_gc->lock, flags);
}
@@ -101,7 +101,7 @@ static void qe_gpio_set_multiple(struct gpio_chip *gc,
}
}
- qe_iowrite32be(qe_gc->cpdata, ®s->cpdata);
+ iowrite32be(qe_gc->cpdata, ®s->cpdata);
spin_unlock_irqrestore(&qe_gc->lock, flags);
}
@@ -269,7 +269,7 @@ void qe_pin_set_dedicated(struct qe_pin *qe_pin)
else
qe_gc->cpdata &= ~mask1;
- qe_iowrite32be(qe_gc->cpdata, ®s->cpdata);
+ iowrite32be(qe_gc->cpdata, ®s->cpdata);
qe_clrsetbits_be32(®s->cpodr, mask1, sregs->cpodr & mask1);
spin_unlock_irqrestore(&qe_gc->lock, flags);
diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c
index 2df20d6f85fa..4d38c80f8be8 100644
--- a/drivers/soc/fsl/qe/qe.c
+++ b/drivers/soc/fsl/qe/qe.c
@@ -109,7 +109,7 @@ int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input)
spin_lock_irqsave(&qe_lock, flags);
if (cmd == QE_RESET) {
- qe_iowrite32be((u32)(cmd | QE_CR_FLG), &qe_immr->cp.cecr);
+ iowrite32be((u32)(cmd | QE_CR_FLG), &qe_immr->cp.cecr);
} else {
if (cmd == QE_ASSIGN_PAGE) {
/* Here device is the SNUM, not sub-block */
@@ -126,13 +126,13 @@ int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input)
mcn_shift = QE_CR_MCN_NORMAL_SHIFT;
}
- qe_iowrite32be(cmd_input, &qe_immr->cp.cecdr);
- qe_iowrite32be((cmd | QE_CR_FLG | ((u32)device << dev_shift) | (u32)mcn_protocol << mcn_shift),
+ iowrite32be(cmd_input, &qe_immr->cp.cecdr);
+ iowrite32be((cmd | QE_CR_FLG | ((u32)device << dev_shift) | (u32)mcn_protocol << mcn_shift),
&qe_immr->cp.cecr);
}
/* wait for the QE_CR_FLG to clear */
- ret = readx_poll_timeout_atomic(qe_ioread32be, &qe_immr->cp.cecr, val,
+ ret = readx_poll_timeout_atomic(ioread32be, &qe_immr->cp.cecr, val,
(val & QE_CR_FLG) == 0, 0, 100);
/* On timeout, ret is -ETIMEDOUT, otherwise it will be 0. */
spin_unlock_irqrestore(&qe_lock, flags);
@@ -231,7 +231,7 @@ int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier)
tempval = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) |
QE_BRGC_ENABLE | div16;
- qe_iowrite32be(tempval, &qe_immr->brg.brgc[brg - QE_BRG1]);
+ iowrite32be(tempval, &qe_immr->brg.brgc[brg - QE_BRG1]);
return 0;
}
@@ -375,9 +375,9 @@ static int qe_sdma_init(void)
return -ENOMEM;
}
- qe_iowrite32be((u32)sdma_buf_offset & QE_SDEBCR_BA_MASK,
+ iowrite32be((u32)sdma_buf_offset & QE_SDEBCR_BA_MASK,
&sdma->sdebcr);
- qe_iowrite32be((QE_SDMR_GLB_1_MSK | (0x1 << QE_SDMR_CEN_SHIFT)),
+ iowrite32be((QE_SDMR_GLB_1_MSK | (0x1 << QE_SDMR_CEN_SHIFT)),
&sdma->sdmr);
return 0;
@@ -416,14 +416,14 @@ static void qe_upload_microcode(const void *base,
"uploading microcode '%s'\n", ucode->id);
/* Use auto-increment */
- qe_iowrite32be(be32_to_cpu(ucode->iram_offset) | QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR,
+ iowrite32be(be32_to_cpu(ucode->iram_offset) | QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR,
&qe_immr->iram.iadd);
for (i = 0; i < be32_to_cpu(ucode->count); i++)
- qe_iowrite32be(be32_to_cpu(code[i]), &qe_immr->iram.idata);
+ iowrite32be(be32_to_cpu(code[i]), &qe_immr->iram.idata);
/* Set I-RAM Ready Register */
- qe_iowrite32be(QE_IRAM_READY, &qe_immr->iram.iready);
+ iowrite32be(QE_IRAM_READY, &qe_immr->iram.iready);
}
/*
@@ -542,12 +542,12 @@ int qe_upload_firmware(const struct qe_firmware *firmware)
u32 trap = be32_to_cpu(ucode->traps[j]);
if (trap)
- qe_iowrite32be(trap,
+ iowrite32be(trap,
&qe_immr->rsp[i].tibcr[j]);
}
/* Enable traps */
- qe_iowrite32be(be32_to_cpu(ucode->eccr),
+ iowrite32be(be32_to_cpu(ucode->eccr),
&qe_immr->rsp[i].eccr);
}
diff --git a/drivers/soc/fsl/qe/qe_ic.c b/drivers/soc/fsl/qe/qe_ic.c
index 0390af999900..3f711c1a0996 100644
--- a/drivers/soc/fsl/qe/qe_ic.c
+++ b/drivers/soc/fsl/qe/qe_ic.c
@@ -222,13 +222,13 @@ static struct qe_ic_info qe_ic_info[] = {
static inline u32 qe_ic_read(__be32 __iomem *base, unsigned int reg)
{
- return qe_ioread32be(base + (reg >> 2));
+ return ioread32be(base + (reg >> 2));
}
static inline void qe_ic_write(__be32 __iomem *base, unsigned int reg,
u32 value)
{
- qe_iowrite32be(value, base + (reg >> 2));
+ iowrite32be(value, base + (reg >> 2));
}
static inline struct qe_ic *qe_ic_from_irq(unsigned int virq)
diff --git a/drivers/soc/fsl/qe/qe_io.c b/drivers/soc/fsl/qe/qe_io.c
index 11ea08e97db7..e277c827bdf3 100644
--- a/drivers/soc/fsl/qe/qe_io.c
+++ b/drivers/soc/fsl/qe/qe_io.c
@@ -54,16 +54,16 @@ void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin, int dir,
pin_mask1bit = (u32) (1 << (QE_PIO_PINS - (pin + 1)));
/* Set open drain, if required */
- tmp_val = qe_ioread32be(&par_io->cpodr);
+ tmp_val = ioread32be(&par_io->cpodr);
if (open_drain)
- qe_iowrite32be(pin_mask1bit | tmp_val, &par_io->cpodr);
+ iowrite32be(pin_mask1bit | tmp_val, &par_io->cpodr);
else
- qe_iowrite32be(~pin_mask1bit & tmp_val, &par_io->cpodr);
+ iowrite32be(~pin_mask1bit & tmp_val, &par_io->cpodr);
/* define direction */
tmp_val = (pin > (QE_PIO_PINS / 2) - 1) ?
- qe_ioread32be(&par_io->cpdir2) :
- qe_ioread32be(&par_io->cpdir1);
+ ioread32be(&par_io->cpdir2) :
+ ioread32be(&par_io->cpdir1);
/* get all bits mask for 2 bit per port */
pin_mask2bits = (u32) (0x3 << (QE_PIO_PINS -
@@ -75,30 +75,30 @@ void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin, int dir,
/* clear and set 2 bits mask */
if (pin > (QE_PIO_PINS / 2) - 1) {
- qe_iowrite32be(~pin_mask2bits & tmp_val, &par_io->cpdir2);
+ iowrite32be(~pin_mask2bits & tmp_val, &par_io->cpdir2);
tmp_val &= ~pin_mask2bits;
- qe_iowrite32be(new_mask2bits | tmp_val, &par_io->cpdir2);
+ iowrite32be(new_mask2bits | tmp_val, &par_io->cpdir2);
} else {
- qe_iowrite32be(~pin_mask2bits & tmp_val, &par_io->cpdir1);
+ iowrite32be(~pin_mask2bits & tmp_val, &par_io->cpdir1);
tmp_val &= ~pin_mask2bits;
- qe_iowrite32be(new_mask2bits | tmp_val, &par_io->cpdir1);
+ iowrite32be(new_mask2bits | tmp_val, &par_io->cpdir1);
}
/* define pin assignment */
tmp_val = (pin > (QE_PIO_PINS / 2) - 1) ?
- qe_ioread32be(&par_io->cppar2) :
- qe_ioread32be(&par_io->cppar1);
+ ioread32be(&par_io->cppar2) :
+ ioread32be(&par_io->cppar1);
new_mask2bits = (u32) (assignment << (QE_PIO_PINS -
(pin % (QE_PIO_PINS / 2) + 1) * 2));
/* clear and set 2 bits mask */
if (pin > (QE_PIO_PINS / 2) - 1) {
- qe_iowrite32be(~pin_mask2bits & tmp_val, &par_io->cppar2);
+ iowrite32be(~pin_mask2bits & tmp_val, &par_io->cppar2);
tmp_val &= ~pin_mask2bits;
- qe_iowrite32be(new_mask2bits | tmp_val, &par_io->cppar2);
+ iowrite32be(new_mask2bits | tmp_val, &par_io->cppar2);
} else {
- qe_iowrite32be(~pin_mask2bits & tmp_val, &par_io->cppar1);
+ iowrite32be(~pin_mask2bits & tmp_val, &par_io->cppar1);
tmp_val &= ~pin_mask2bits;
- qe_iowrite32be(new_mask2bits | tmp_val, &par_io->cppar1);
+ iowrite32be(new_mask2bits | tmp_val, &par_io->cppar1);
}
}
EXPORT_SYMBOL(__par_io_config_pin);
@@ -126,12 +126,12 @@ int par_io_data_set(u8 port, u8 pin, u8 val)
/* calculate pin location */
pin_mask = (u32) (1 << (QE_PIO_PINS - 1 - pin));
- tmp_val = qe_ioread32be(&par_io[port].cpdata);
+ tmp_val = ioread32be(&par_io[port].cpdata);
if (val == 0) /* clear */
- qe_iowrite32be(~pin_mask & tmp_val, &par_io[port].cpdata);
+ iowrite32be(~pin_mask & tmp_val, &par_io[port].cpdata);
else /* set */
- qe_iowrite32be(pin_mask | tmp_val, &par_io[port].cpdata);
+ iowrite32be(pin_mask | tmp_val, &par_io[port].cpdata);
return 0;
}
diff --git a/drivers/soc/fsl/qe/ucc_fast.c b/drivers/soc/fsl/qe/ucc_fast.c
index ad6193ea4597..53d8aafc9317 100644
--- a/drivers/soc/fsl/qe/ucc_fast.c
+++ b/drivers/soc/fsl/qe/ucc_fast.c
@@ -29,42 +29,42 @@ void ucc_fast_dump_regs(struct ucc_fast_private * uccf)
printk(KERN_INFO "Base address: 0x%p\n", uccf->uf_regs);
printk(KERN_INFO "gumr : addr=0x%p, val=0x%08x\n",
- &uccf->uf_regs->gumr, qe_ioread32be(&uccf->uf_regs->gumr));
+ &uccf->uf_regs->gumr, ioread32be(&uccf->uf_regs->gumr));
printk(KERN_INFO "upsmr : addr=0x%p, val=0x%08x\n",
- &uccf->uf_regs->upsmr, qe_ioread32be(&uccf->uf_regs->upsmr));
+ &uccf->uf_regs->upsmr, ioread32be(&uccf->uf_regs->upsmr));
printk(KERN_INFO "utodr : addr=0x%p, val=0x%04x\n",
- &uccf->uf_regs->utodr, qe_ioread16be(&uccf->uf_regs->utodr));
+ &uccf->uf_regs->utodr, ioread16be(&uccf->uf_regs->utodr));
printk(KERN_INFO "udsr : addr=0x%p, val=0x%04x\n",
- &uccf->uf_regs->udsr, qe_ioread16be(&uccf->uf_regs->udsr));
+ &uccf->uf_regs->udsr, ioread16be(&uccf->uf_regs->udsr));
printk(KERN_INFO "ucce : addr=0x%p, val=0x%08x\n",
- &uccf->uf_regs->ucce, qe_ioread32be(&uccf->uf_regs->ucce));
+ &uccf->uf_regs->ucce, ioread32be(&uccf->uf_regs->ucce));
printk(KERN_INFO "uccm : addr=0x%p, val=0x%08x\n",
- &uccf->uf_regs->uccm, qe_ioread32be(&uccf->uf_regs->uccm));
+ &uccf->uf_regs->uccm, ioread32be(&uccf->uf_regs->uccm));
printk(KERN_INFO "uccs : addr=0x%p, val=0x%02x\n",
- &uccf->uf_regs->uccs, qe_ioread8(&uccf->uf_regs->uccs));
+ &uccf->uf_regs->uccs, ioread8(&uccf->uf_regs->uccs));
printk(KERN_INFO "urfb : addr=0x%p, val=0x%08x\n",
- &uccf->uf_regs->urfb, qe_ioread32be(&uccf->uf_regs->urfb));
+ &uccf->uf_regs->urfb, ioread32be(&uccf->uf_regs->urfb));
printk(KERN_INFO "urfs : addr=0x%p, val=0x%04x\n",
- &uccf->uf_regs->urfs, qe_ioread16be(&uccf->uf_regs->urfs));
+ &uccf->uf_regs->urfs, ioread16be(&uccf->uf_regs->urfs));
printk(KERN_INFO "urfet : addr=0x%p, val=0x%04x\n",
- &uccf->uf_regs->urfet, qe_ioread16be(&uccf->uf_regs->urfet));
+ &uccf->uf_regs->urfet, ioread16be(&uccf->uf_regs->urfet));
printk(KERN_INFO "urfset: addr=0x%p, val=0x%04x\n",
&uccf->uf_regs->urfset,
- qe_ioread16be(&uccf->uf_regs->urfset));
+ ioread16be(&uccf->uf_regs->urfset));
printk(KERN_INFO "utfb : addr=0x%p, val=0x%08x\n",
- &uccf->uf_regs->utfb, qe_ioread32be(&uccf->uf_regs->utfb));
+ &uccf->uf_regs->utfb, ioread32be(&uccf->uf_regs->utfb));
printk(KERN_INFO "utfs : addr=0x%p, val=0x%04x\n",
- &uccf->uf_regs->utfs, qe_ioread16be(&uccf->uf_regs->utfs));
+ &uccf->uf_regs->utfs, ioread16be(&uccf->uf_regs->utfs));
printk(KERN_INFO "utfet : addr=0x%p, val=0x%04x\n",
- &uccf->uf_regs->utfet, qe_ioread16be(&uccf->uf_regs->utfet));
+ &uccf->uf_regs->utfet, ioread16be(&uccf->uf_regs->utfet));
printk(KERN_INFO "utftt : addr=0x%p, val=0x%04x\n",
- &uccf->uf_regs->utftt, qe_ioread16be(&uccf->uf_regs->utftt));
+ &uccf->uf_regs->utftt, ioread16be(&uccf->uf_regs->utftt));
printk(KERN_INFO "utpt : addr=0x%p, val=0x%04x\n",
- &uccf->uf_regs->utpt, qe_ioread16be(&uccf->uf_regs->utpt));
+ &uccf->uf_regs->utpt, ioread16be(&uccf->uf_regs->utpt));
printk(KERN_INFO "urtry : addr=0x%p, val=0x%08x\n",
- &uccf->uf_regs->urtry, qe_ioread32be(&uccf->uf_regs->urtry));
+ &uccf->uf_regs->urtry, ioread32be(&uccf->uf_regs->urtry));
printk(KERN_INFO "guemr : addr=0x%p, val=0x%02x\n",
- &uccf->uf_regs->guemr, qe_ioread8(&uccf->uf_regs->guemr));
+ &uccf->uf_regs->guemr, ioread8(&uccf->uf_regs->guemr));
}
EXPORT_SYMBOL(ucc_fast_dump_regs);
@@ -86,7 +86,7 @@ EXPORT_SYMBOL(ucc_fast_get_qe_cr_subblock);
void ucc_fast_transmit_on_demand(struct ucc_fast_private * uccf)
{
- qe_iowrite16be(UCC_FAST_TOD, &uccf->uf_regs->utodr);
+ iowrite16be(UCC_FAST_TOD, &uccf->uf_regs->utodr);
}
EXPORT_SYMBOL(ucc_fast_transmit_on_demand);
@@ -98,7 +98,7 @@ void ucc_fast_enable(struct ucc_fast_private * uccf, enum comm_dir mode)
uf_regs = uccf->uf_regs;
/* Enable reception and/or transmission on this UCC. */
- gumr = qe_ioread32be(&uf_regs->gumr);
+ gumr = ioread32be(&uf_regs->gumr);
if (mode & COMM_DIR_TX) {
gumr |= UCC_FAST_GUMR_ENT;
uccf->enabled_tx = 1;
@@ -107,7 +107,7 @@ void ucc_fast_enable(struct ucc_fast_private * uccf, enum comm_dir mode)
gumr |= UCC_FAST_GUMR_ENR;
uccf->enabled_rx = 1;
}
- qe_iowrite32be(gumr, &uf_regs->gumr);
+ iowrite32be(gumr, &uf_regs->gumr);
}
EXPORT_SYMBOL(ucc_fast_enable);
@@ -119,7 +119,7 @@ void ucc_fast_disable(struct ucc_fast_private * uccf, enum comm_dir mode)
uf_regs = uccf->uf_regs;
/* Disable reception and/or transmission on this UCC. */
- gumr = qe_ioread32be(&uf_regs->gumr);
+ gumr = ioread32be(&uf_regs->gumr);
if (mode & COMM_DIR_TX) {
gumr &= ~UCC_FAST_GUMR_ENT;
uccf->enabled_tx = 0;
@@ -128,7 +128,7 @@ void ucc_fast_disable(struct ucc_fast_private * uccf, enum comm_dir mode)
gumr &= ~UCC_FAST_GUMR_ENR;
uccf->enabled_rx = 0;
}
- qe_iowrite32be(gumr, &uf_regs->gumr);
+ iowrite32be(gumr, &uf_regs->gumr);
}
EXPORT_SYMBOL(ucc_fast_disable);
@@ -262,7 +262,7 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
gumr |= uf_info->tenc;
gumr |= uf_info->tcrc;
gumr |= uf_info->mode;
- qe_iowrite32be(gumr, &uf_regs->gumr);
+ iowrite32be(gumr, &uf_regs->gumr);
/* Allocate memory for Tx Virtual Fifo */
uccf->ucc_fast_tx_virtual_fifo_base_offset =
@@ -287,16 +287,16 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
}
/* Set Virtual Fifo registers */
- qe_iowrite16be(uf_info->urfs, &uf_regs->urfs);
- qe_iowrite16be(uf_info->urfet, &uf_regs->urfet);
- qe_iowrite16be(uf_info->urfset, &uf_regs->urfset);
- qe_iowrite16be(uf_info->utfs, &uf_regs->utfs);
- qe_iowrite16be(uf_info->utfet, &uf_regs->utfet);
- qe_iowrite16be(uf_info->utftt, &uf_regs->utftt);
+ iowrite16be(uf_info->urfs, &uf_regs->urfs);
+ iowrite16be(uf_info->urfet, &uf_regs->urfet);
+ iowrite16be(uf_info->urfset, &uf_regs->urfset);
+ iowrite16be(uf_info->utfs, &uf_regs->utfs);
+ iowrite16be(uf_info->utfet, &uf_regs->utfet);
+ iowrite16be(uf_info->utftt, &uf_regs->utftt);
/* utfb, urfb are offsets from MURAM base */
- qe_iowrite32be(uccf->ucc_fast_tx_virtual_fifo_base_offset,
+ iowrite32be(uccf->ucc_fast_tx_virtual_fifo_base_offset,
&uf_regs->utfb);
- qe_iowrite32be(uccf->ucc_fast_rx_virtual_fifo_base_offset,
+ iowrite32be(uccf->ucc_fast_rx_virtual_fifo_base_offset,
&uf_regs->urfb);
/* Mux clocking */
@@ -365,14 +365,14 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
}
/* Set interrupt mask register at UCC level. */
- qe_iowrite32be(uf_info->uccm_mask, &uf_regs->uccm);
+ iowrite32be(uf_info->uccm_mask, &uf_regs->uccm);
/* First, clear anything pending at UCC level,
* otherwise, old garbage may come through
* as soon as the dam is opened. */
/* Writing '1' clears */
- qe_iowrite32be(0xffffffff, &uf_regs->ucce);
+ iowrite32be(0xffffffff, &uf_regs->ucce);
*uccf_ret = uccf;
return 0;
diff --git a/drivers/soc/fsl/qe/ucc_slow.c b/drivers/soc/fsl/qe/ucc_slow.c
index 7e11be41ab62..d5ac1ac0ed3c 100644
--- a/drivers/soc/fsl/qe/ucc_slow.c
+++ b/drivers/soc/fsl/qe/ucc_slow.c
@@ -78,7 +78,7 @@ void ucc_slow_enable(struct ucc_slow_private * uccs, enum comm_dir mode)
us_regs = uccs->us_regs;
/* Enable reception and/or transmission on this UCC. */
- gumr_l = qe_ioread32be(&us_regs->gumr_l);
+ gumr_l = ioread32be(&us_regs->gumr_l);
if (mode & COMM_DIR_TX) {
gumr_l |= UCC_SLOW_GUMR_L_ENT;
uccs->enabled_tx = 1;
@@ -87,7 +87,7 @@ void ucc_slow_enable(struct ucc_slow_private * uccs, enum comm_dir mode)
gumr_l |= UCC_SLOW_GUMR_L_ENR;
uccs->enabled_rx = 1;
}
- qe_iowrite32be(gumr_l, &us_regs->gumr_l);
+ iowrite32be(gumr_l, &us_regs->gumr_l);
}
EXPORT_SYMBOL(ucc_slow_enable);
@@ -99,7 +99,7 @@ void ucc_slow_disable(struct ucc_slow_private * uccs, enum comm_dir mode)
us_regs = uccs->us_regs;
/* Disable reception and/or transmission on this UCC. */
- gumr_l = qe_ioread32be(&us_regs->gumr_l);
+ gumr_l = ioread32be(&us_regs->gumr_l);
if (mode & COMM_DIR_TX) {
gumr_l &= ~UCC_SLOW_GUMR_L_ENT;
uccs->enabled_tx = 0;
@@ -108,7 +108,7 @@ void ucc_slow_disable(struct ucc_slow_private * uccs, enum comm_dir mode)
gumr_l &= ~UCC_SLOW_GUMR_L_ENR;
uccs->enabled_rx = 0;
}
- qe_iowrite32be(gumr_l, &us_regs->gumr_l);
+ iowrite32be(gumr_l, &us_regs->gumr_l);
}
EXPORT_SYMBOL(ucc_slow_disable);
@@ -194,7 +194,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
return ret;
}
- qe_iowrite16be(us_info->max_rx_buf_length, &uccs->us_pram->mrblr);
+ iowrite16be(us_info->max_rx_buf_length, &uccs->us_pram->mrblr);
INIT_LIST_HEAD(&uccs->confQ);
@@ -222,27 +222,27 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
bd = uccs->confBd = uccs->tx_bd = qe_muram_addr(uccs->tx_base_offset);
for (i = 0; i < us_info->tx_bd_ring_len - 1; i++) {
/* clear bd buffer */
- qe_iowrite32be(0, &bd->buf);
+ iowrite32be(0, &bd->buf);
/* set bd status and length */
- qe_iowrite32be(0, (u32 __iomem *)bd);
+ iowrite32be(0, (u32 __iomem *)bd);
bd++;
}
/* for last BD set Wrap bit */
- qe_iowrite32be(0, &bd->buf);
- qe_iowrite32be(T_W, (u32 __iomem *)bd);
+ iowrite32be(0, &bd->buf);
+ iowrite32be(T_W, (u32 __iomem *)bd);
/* Init Rx bds */
bd = uccs->rx_bd = qe_muram_addr(uccs->rx_base_offset);
for (i = 0; i < us_info->rx_bd_ring_len - 1; i++) {
/* set bd status and length */
- qe_iowrite32be(0, (u32 __iomem *)bd);
+ iowrite32be(0, (u32 __iomem *)bd);
/* clear bd buffer */
- qe_iowrite32be(0, &bd->buf);
+ iowrite32be(0, &bd->buf);
bd++;
}
/* for last BD set Wrap bit */
- qe_iowrite32be(R_W, (u32 __iomem *)bd);
- qe_iowrite32be(0, &bd->buf);
+ iowrite32be(R_W, (u32 __iomem *)bd);
+ iowrite32be(0, &bd->buf);
/* Set GUMR (For more details see the hardware spec.). */
/* gumr_h */
@@ -263,7 +263,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
gumr |= UCC_SLOW_GUMR_H_TXSY;
if (us_info->rtsm)
gumr |= UCC_SLOW_GUMR_H_RTSM;
- qe_iowrite32be(gumr, &us_regs->gumr_h);
+ iowrite32be(gumr, &us_regs->gumr_h);
/* gumr_l */
gumr = (u32)us_info->tdcr | (u32)us_info->rdcr | (u32)us_info->tenc |
@@ -276,18 +276,18 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
gumr |= UCC_SLOW_GUMR_L_TINV;
if (us_info->tend)
gumr |= UCC_SLOW_GUMR_L_TEND;
- qe_iowrite32be(gumr, &us_regs->gumr_l);
+ iowrite32be(gumr, &us_regs->gumr_l);
/* Function code registers */
/* if the data is in cachable memory, the 'global' */
/* in the function code should be set. */
- qe_iowrite8(UCC_BMR_BO_BE, &uccs->us_pram->tbmr);
- qe_iowrite8(UCC_BMR_BO_BE, &uccs->us_pram->rbmr);
+ iowrite8(UCC_BMR_BO_BE, &uccs->us_pram->tbmr);
+ iowrite8(UCC_BMR_BO_BE, &uccs->us_pram->rbmr);
/* rbase, tbase are offsets from MURAM base */
- qe_iowrite16be(uccs->rx_base_offset, &uccs->us_pram->rbase);
- qe_iowrite16be(uccs->tx_base_offset, &uccs->us_pram->tbase);
+ iowrite16be(uccs->rx_base_offset, &uccs->us_pram->rbase);
+ iowrite16be(uccs->tx_base_offset, &uccs->us_pram->tbase);
/* Mux clocking */
/* Grant Support */
@@ -317,14 +317,14 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
}
/* Set interrupt mask register at UCC level. */
- qe_iowrite16be(us_info->uccm_mask, &us_regs->uccm);
+ iowrite16be(us_info->uccm_mask, &us_regs->uccm);
/* First, clear anything pending at UCC level,
* otherwise, old garbage may come through
* as soon as the dam is opened. */
/* Writing '1' clears */
- qe_iowrite16be(0xffff, &us_regs->ucce);
+ iowrite16be(0xffff, &us_regs->ucce);
/* Issue QE Init command */
if (us_info->init_tx && us_info->init_rx)
--
2.25.0
^ permalink raw reply related
* Re: [PATCH v1 2/3] tty: serial: ucc_uart: replace qe_io{read, write}* wrappers by generic io{read,write}*
From: Greg Kroah-Hartman @ 2021-03-06 19:23 UTC (permalink / raw)
To: Christophe Leroy
Cc: Timur Tabi, Rasmus Villemoes, linuxppc-dev, linux-kernel, Li Yang,
linux-serial, Jiri Slaby, linux-arm-kernel, Qiang Zhao
In-Reply-To: <479e57158ed85c041e4c32ef17b55024f8a784ce.1615053848.git.christophe.leroy@csgroup.eu>
On Sat, Mar 06, 2021 at 06:09:30PM +0000, Christophe Leroy wrote:
> Commit 6ac9b61786cc ("soc: fsl: qe: introduce qe_io{read,write}*
> wrappers") added specific I/O accessors for qe because at that
> time ioread/iowrite functions were sub-optimal on powerpc/32
> compared to the architecture specific in_/out_ IO accessors.
>
> But as ioread/iowrite accessors are now equivalent since
> commit 894fa235eb4c ("powerpc: inline iomap accessors"),
> use them in order to allow removal of the qe specific ones.
>
> Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
> ---
> drivers/tty/serial/ucc_uart.c | 124 +++++++++++++++++-----------------
> 1 file changed, 62 insertions(+), 62 deletions(-)
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
^ permalink raw reply
* Re: [PATCH] powerpc: iommu: fix build when neither PCI or IBMVIO is set
From: Randy Dunlap @ 2021-03-06 19:44 UTC (permalink / raw)
To: Michael Ellerman, linux-kernel
Cc: linuxppc-dev, kernel test robot, Anton Blanchard
In-Reply-To: <87lfb5sthg.fsf@mpe.ellerman.id.au>
On March 2, 2021 3:08:43 AM PST, Michael Ellerman <mpe@ellerman.id.au> wrote:
>Randy Dunlap <rdunlap@infradead.org> writes:
>> When neither CONFIG_PCI nor CONFIG_IBMVIO is enabled:
>>
>> ../arch/powerpc/kernel/iommu.c:178:30: error:
>'fail_iommu_bus_notifier' defined but not used
>[-Werror=unused-variable]
>> 178 | static struct notifier_block fail_iommu_bus_notifier = {
>>
>> If only that struct is bounded by 2 #if defined() phrases (PCI &&
>IBMVIO):
>>
>> ../arch/powerpc/kernel/iommu.c:162:12: error: 'fail_iommu_bus_notify'
>defined but not used [-Werror=unused-function]
>> 162 | static int fail_iommu_bus_notify(struct notifier_block *nb,
>>
>> If that function is also guarded by 2 #if defined() phrases:
>>
>> In file included from ../include/linux/dma-mapping.h:7,
>> from ../arch/powerpc/kernel/iommu.c:19:
>> ../include/linux/device.h:131:26: error: 'dev_attr_fail_iommu'
>defined but not used [-Werror=unused-variable]
>> 131 | struct device_attribute dev_attr_##_name = __ATTR_RW(_name)
>> ../arch/powerpc/kernel/iommu.c:160:8: note: in expansion of macro
>'DEVICE_ATTR_RW'
>> 160 | static DEVICE_ATTR_RW(fail_iommu);
>>
>> and the snowball continues to grow.
>> Next I got this one:
>>
>> ../arch/powerpc/kernel/iommu.c: In function 'iommu_range_alloc':
>> ../arch/powerpc/kernel/iommu.c:234:6: error: implicit declaration of
>function 'should_fail_iommu'; did you mean 'should_failslab'?
>[-Werror=implicit-function-declaration]
>> 234 | if (should_fail_iommu(dev))
>>
>> and
>>
>> ../arch/powerpc/kernel/iommu.c: In function 'should_fail_iommu':
>> ../arch/powerpc/kernel/iommu.c:122:50: error: 'fail_iommu' undeclared
>(first use in this function)
>> 122 | return dev->archdata.fail_iommu && should_fail(&fail_iommu,
>1);
>>
>> So combine CONFIG_FAIL_IOMMU && (CONFIG_PCI || CONFIG_IBMVIO)
>> to decide on building some of this code/data.
>
>Couldn't we just make FAIL_IOMMU depend on PCI || IBMVIO?
>
>cheers
Yes, I thought of that about 5 seconds after hitting Send. But I can't do it just now -- am away from computer.
--
Sent from my Android device with K-9 Mail. Please excuse my brevity.
^ permalink raw reply
* Re: [PATCH v3 7/7] ASoC: dt-bindings: imx-rpmsg: Add binding doc for rpmsg machine driver
From: Rob Herring @ 2021-03-06 20:36 UTC (permalink / raw)
To: Shengjiu Wang
Cc: devicetree, alsa-devel, timur, lgirdwood, linuxppc-dev, Xiubo.Lee,
linux-kernel, tiwai, nicoleotsuka, broonie, perex, festevam
In-Reply-To: <1614221563-26822-8-git-send-email-shengjiu.wang@nxp.com>
On Thu, Feb 25, 2021 at 10:52:43AM +0800, Shengjiu Wang wrote:
> Imx-rpmsg is a new added machine driver for supporting audio on Cortex-M
> core. The Cortex-M core will control the audio interface, DMA and audio
> codec, setup the pipeline, the audio driver on Cortex-A core side is just
> to communitcate with M core, it is a virtual sound card and don't touch
> the hardware.
This sounds like 1 h/w block (the interface to the cortex-M), your DT
should be 1 node. If you need 2 drivers to satisfy the needs of the OS,
then instantiate one device from the other device's driver.
Rob
^ permalink raw reply
* [PATCH] Replace __toc_start + 0x8000 with .TOC.
From: Fangrui Song @ 2021-03-07 5:14 UTC (permalink / raw)
To: Michael Ellerman, linuxppc-dev, linux-kernel, clang-built-linux
Cc: Alexey Kardashevskiy, Fangrui Song
TOC relocations are like GOT relocations on other architectures.
However, unlike other architectures, GNU ld's ppc64 port defines .TOC.
relative to the .got output section instead of the linker synthesized
.got input section. LLD defines .TOC. as the .got input section plus
0x8000. When CONFIG_PPC_OF_BOOT_TRAMPOLINE=y,
arch/powerpc/kernel/prom_init.o is built, and LLD computed .TOC. can be
different from __toc_start defined by the linker script.
Simplify kernel_toc_addr with asm label .TOC. so that we can get rid of
__toc_start.
With this change, powernv_defconfig with CONFIG_PPC_OF_BOOT_TRAMPOLINE=y
is bootable with LLD. There is still an untriaged issue with Alexey's
configuration.
Link: https://github.com/ClangBuiltLinux/linux/issues/1318
Reported-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: Fangrui Song <maskray@google.com>
---
arch/powerpc/boot/crt0.S | 2 +-
arch/powerpc/boot/zImage.lds.S | 1 -
arch/powerpc/include/asm/sections.h | 10 ++--------
arch/powerpc/kernel/head_64.S | 2 +-
arch/powerpc/kernel/vmlinux.lds.S | 1 -
5 files changed, 4 insertions(+), 12 deletions(-)
diff --git a/arch/powerpc/boot/crt0.S b/arch/powerpc/boot/crt0.S
index 1d83966f5ef6..e45907fe468f 100644
--- a/arch/powerpc/boot/crt0.S
+++ b/arch/powerpc/boot/crt0.S
@@ -28,7 +28,7 @@ p_etext: .8byte _etext
p_bss_start: .8byte __bss_start
p_end: .8byte _end
-p_toc: .8byte __toc_start + 0x8000 - p_base
+p_toc: .8byte .TOC. - p_base
p_dyn: .8byte __dynamic_start - p_base
p_rela: .8byte __rela_dyn_start - p_base
p_prom: .8byte 0
diff --git a/arch/powerpc/boot/zImage.lds.S b/arch/powerpc/boot/zImage.lds.S
index d6f072865627..32cf7816292f 100644
--- a/arch/powerpc/boot/zImage.lds.S
+++ b/arch/powerpc/boot/zImage.lds.S
@@ -39,7 +39,6 @@ SECTIONS
. = ALIGN(256);
.got :
{
- __toc_start = .;
*(.got)
*(.toc)
}
diff --git a/arch/powerpc/include/asm/sections.h b/arch/powerpc/include/asm/sections.h
index 324d7b298ec3..bd22ca0b5eca 100644
--- a/arch/powerpc/include/asm/sections.h
+++ b/arch/powerpc/include/asm/sections.h
@@ -48,14 +48,8 @@ static inline int in_kernel_text(unsigned long addr)
static inline unsigned long kernel_toc_addr(void)
{
- /* Defined by the linker, see vmlinux.lds.S */
- extern unsigned long __toc_start;
-
- /*
- * The TOC register (r2) points 32kB into the TOC, so that 64kB of
- * the TOC can be addressed using a single machine instruction.
- */
- return (unsigned long)(&__toc_start) + 0x8000UL;
+ extern unsigned long toc asm(".TOC.");
+ return (unsigned long)(&toc);
}
static inline int overlaps_interrupt_vector_text(unsigned long start,
diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S
index ece7f97bafff..9542d03b2efe 100644
--- a/arch/powerpc/kernel/head_64.S
+++ b/arch/powerpc/kernel/head_64.S
@@ -899,7 +899,7 @@ _GLOBAL(relative_toc)
blr
.balign 8
-p_toc: .8byte __toc_start + 0x8000 - 0b
+p_toc: .8byte .TOC. - 0b
/*
* This is where the main kernel code starts.
diff --git a/arch/powerpc/kernel/vmlinux.lds.S b/arch/powerpc/kernel/vmlinux.lds.S
index 72fa3c00229a..c28f4e5bae3f 100644
--- a/arch/powerpc/kernel/vmlinux.lds.S
+++ b/arch/powerpc/kernel/vmlinux.lds.S
@@ -328,7 +328,6 @@ SECTIONS
. = ALIGN(256);
.got : AT(ADDR(.got) - LOAD_OFFSET) {
- __toc_start = .;
#ifndef CONFIG_RELOCATABLE
__prom_init_toc_start = .;
arch/powerpc/kernel/prom_init.o*(.toc .got)
--
2.30.1.766.gb4fecdf3b7-goog
^ permalink raw reply related
* Re: [PATCH] Replace __toc_start + 0x8000 with .TOC.
From: Segher Boessenkool @ 2021-03-07 6:23 UTC (permalink / raw)
To: Fangrui Song
Cc: Alexey Kardashevskiy, linuxppc-dev, linux-kernel,
clang-built-linux
In-Reply-To: <20210307051433.2756645-1-maskray@google.com>
Hi!
On Sat, Mar 06, 2021 at 09:14:33PM -0800, Fangrui Song wrote:
> TOC relocations are like GOT relocations on other architectures.
> However, unlike other architectures, GNU ld's ppc64 port defines .TOC.
> relative to the .got output section instead of the linker synthesized
> .got input section. LLD defines .TOC. as the .got input section plus
> 0x8000. When CONFIG_PPC_OF_BOOT_TRAMPOLINE=y,
> arch/powerpc/kernel/prom_init.o is built, and LLD computed .TOC. can be
> different from __toc_start defined by the linker script.
>
> Simplify kernel_toc_addr with asm label .TOC. so that we can get rid of
> __toc_start.
>
> With this change, powernv_defconfig with CONFIG_PPC_OF_BOOT_TRAMPOLINE=y
> is bootable with LLD. There is still an untriaged issue with Alexey's
> configuration.
Do you have any explanation why this *does* work, while the original
doesn't? Some explanation that says *what* is wrong. To me it doesn't
look like the kernel script is.
Segher
^ permalink raw reply
* Re: [PATCH] Replace __toc_start + 0x8000 with .TOC.
From: Fāng-ruì Sòng @ 2021-03-07 6:31 UTC (permalink / raw)
To: Segher Boessenkool
Cc: Alexey Kardashevskiy, linuxppc-dev, LKML, clang-built-linux
In-Reply-To: <20210307062336.GD29191@gate.crashing.org>
On Sat, Mar 6, 2021 at 10:25 PM Segher Boessenkool
<segher@kernel.crashing.org> wrote:
>
> Hi!
>
> On Sat, Mar 06, 2021 at 09:14:33PM -0800, Fangrui Song wrote:
> > TOC relocations are like GOT relocations on other architectures.
> > However, unlike other architectures, GNU ld's ppc64 port defines .TOC.
> > relative to the .got output section instead of the linker synthesized
> > .got input section. LLD defines .TOC. as the .got input section plus
> > 0x8000. When CONFIG_PPC_OF_BOOT_TRAMPOLINE=y,
> > arch/powerpc/kernel/prom_init.o is built, and LLD computed .TOC. can be
> > different from __toc_start defined by the linker script.
> >
> > Simplify kernel_toc_addr with asm label .TOC. so that we can get rid of
> > __toc_start.
> >
> > With this change, powernv_defconfig with CONFIG_PPC_OF_BOOT_TRAMPOLINE=y
> > is bootable with LLD. There is still an untriaged issue with Alexey's
> > configuration.
>
> Do you have any explanation why this *does* work, while the original
> doesn't? Some explanation that says *what* is wrong. To me it doesn't
> look like the kernel script is.
>
>
> Segher
The kernel code probably wants to access .TOC. (the TOC base symbol)
via __toc_start+0x8000.
If the kernel understood TOC base is different from the linker
understood TOC base (.TOC.), there should be a problem.
By using .TOC. in the kernel code, the two concepts are guaranteed to match.
^ permalink raw reply
* [PATCH] net: wan: fix error return code of uhdlc_init()
From: Jia-Ju Bai @ 2021-03-07 9:12 UTC (permalink / raw)
To: qiang.zhao, davem, kuba; +Cc: netdev, Jia-Ju Bai, linuxppc-dev, linux-kernel
When priv->rx_skbuff or priv->tx_skbuff is NULL, no error return code of
uhdlc_init() is assigned.
To fix this bug, ret is assigned with -ENOMEM in these cases.
Reported-by: TOTE Robot <oslab@tsinghua.edu.cn>
Signed-off-by: Jia-Ju Bai <baijiaju1990@gmail.com>
---
drivers/net/wan/fsl_ucc_hdlc.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/net/wan/fsl_ucc_hdlc.c b/drivers/net/wan/fsl_ucc_hdlc.c
index dca97cd7c4e7..7eac6a3e1cde 100644
--- a/drivers/net/wan/fsl_ucc_hdlc.c
+++ b/drivers/net/wan/fsl_ucc_hdlc.c
@@ -204,14 +204,18 @@ static int uhdlc_init(struct ucc_hdlc_private *priv)
priv->rx_skbuff = kcalloc(priv->rx_ring_size,
sizeof(*priv->rx_skbuff),
GFP_KERNEL);
- if (!priv->rx_skbuff)
+ if (!priv->rx_skbuff) {
+ ret = -ENOMEM;
goto free_ucc_pram;
+ }
priv->tx_skbuff = kcalloc(priv->tx_ring_size,
sizeof(*priv->tx_skbuff),
GFP_KERNEL);
- if (!priv->tx_skbuff)
+ if (!priv->tx_skbuff) {
+ ret = -ENOMEM;
goto free_rx_skbuff;
+ }
priv->skb_curtx = 0;
priv->skb_dirtytx = 0;
--
2.17.1
^ permalink raw reply related
* Re: [PATCH v1 12/15] powerpc/uaccess: Refactor get/put_user() and __get/put_user()
From: kernel test robot @ 2021-03-07 10:23 UTC (permalink / raw)
To: Christophe Leroy, Benjamin Herrenschmidt, Paul Mackerras,
Michael Ellerman
Cc: linuxppc-dev, kbuild-all, linux-kernel
In-Reply-To: <3c174edb80d2d37af6b08c637b09268f675e5371.1614275314.git.christophe.leroy@csgroup.eu>
[-- Attachment #1: Type: text/plain, Size: 5429 bytes --]
Hi Christophe,
I love your patch! Perhaps something to improve:
[auto build test WARNING on powerpc/next]
[also build test WARNING on v5.12-rc2 next-20210305]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Christophe-Leroy/powerpc-Cleanup-of-uaccess-h/20210226-015715
base: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next
config: powerpc-randconfig-s031-20210307 (attached as .config)
compiler: powerpc-linux-gcc (GCC) 9.3.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# apt-get install sparse
# sparse version: v0.6.3-245-gacc5c298-dirty
# https://github.com/0day-ci/linux/commit/449bdbf978936e67e4919be8be0eec3e490a65e2
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Christophe-Leroy/powerpc-Cleanup-of-uaccess-h/20210226-015715
git checkout 449bdbf978936e67e4919be8be0eec3e490a65e2
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' ARCH=powerpc
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
"sparse warnings: (new ones prefixed by >>)"
>> drivers/w1/slaves/w1_ds28e04.c:342:13: sparse: sparse: incorrect type in initializer (different address spaces) @@ expected char [noderef] __user *_pu_addr @@ got char *buf @@
drivers/w1/slaves/w1_ds28e04.c:342:13: sparse: expected char [noderef] __user *_pu_addr
drivers/w1/slaves/w1_ds28e04.c:342:13: sparse: got char *buf
>> drivers/w1/slaves/w1_ds28e04.c:356:13: sparse: sparse: incorrect type in initializer (different address spaces) @@ expected char const [noderef] __user *_gu_addr @@ got char const *buf @@
drivers/w1/slaves/w1_ds28e04.c:356:13: sparse: expected char const [noderef] __user *_gu_addr
drivers/w1/slaves/w1_ds28e04.c:356:13: sparse: got char const *buf
--
drivers/gpu/drm/radeon/radeon_ttm.c:933:21: sparse: sparse: cast removes address space '__user' of expression
drivers/gpu/drm/radeon/radeon_ttm.c:933:21: sparse: sparse: cast removes address space '__user' of expression
>> drivers/gpu/drm/radeon/radeon_ttm.c:933:21: sparse: sparse: incorrect type in initializer (different address spaces) @@ expected unsigned int [noderef] __user *_pu_addr @@ got unsigned int [usertype] * @@
drivers/gpu/drm/radeon/radeon_ttm.c:933:21: sparse: expected unsigned int [noderef] __user *_pu_addr
drivers/gpu/drm/radeon/radeon_ttm.c:933:21: sparse: got unsigned int [usertype] *
drivers/gpu/drm/radeon/radeon_ttm.c:933:21: sparse: sparse: cast removes address space '__user' of expression
vim +342 drivers/w1/slaves/w1_ds28e04.c
fa33a65a9cf7e2 Greg Kroah-Hartman 2013-08-21 338
fa33a65a9cf7e2 Greg Kroah-Hartman 2013-08-21 339 static ssize_t crccheck_show(struct device *dev, struct device_attribute *attr,
fa33a65a9cf7e2 Greg Kroah-Hartman 2013-08-21 340 char *buf)
fbf7f7b4e2ae40 Markus Franke 2012-05-26 341 {
fbf7f7b4e2ae40 Markus Franke 2012-05-26 @342 if (put_user(w1_enable_crccheck + 0x30, buf))
fbf7f7b4e2ae40 Markus Franke 2012-05-26 343 return -EFAULT;
fbf7f7b4e2ae40 Markus Franke 2012-05-26 344
fbf7f7b4e2ae40 Markus Franke 2012-05-26 345 return sizeof(w1_enable_crccheck);
fbf7f7b4e2ae40 Markus Franke 2012-05-26 346 }
fbf7f7b4e2ae40 Markus Franke 2012-05-26 347
fa33a65a9cf7e2 Greg Kroah-Hartman 2013-08-21 348 static ssize_t crccheck_store(struct device *dev, struct device_attribute *attr,
fbf7f7b4e2ae40 Markus Franke 2012-05-26 349 const char *buf, size_t count)
fbf7f7b4e2ae40 Markus Franke 2012-05-26 350 {
fbf7f7b4e2ae40 Markus Franke 2012-05-26 351 char val;
fbf7f7b4e2ae40 Markus Franke 2012-05-26 352
fbf7f7b4e2ae40 Markus Franke 2012-05-26 353 if (count != 1 || !buf)
fbf7f7b4e2ae40 Markus Franke 2012-05-26 354 return -EINVAL;
fbf7f7b4e2ae40 Markus Franke 2012-05-26 355
fbf7f7b4e2ae40 Markus Franke 2012-05-26 @356 if (get_user(val, buf))
fbf7f7b4e2ae40 Markus Franke 2012-05-26 357 return -EFAULT;
fbf7f7b4e2ae40 Markus Franke 2012-05-26 358
fbf7f7b4e2ae40 Markus Franke 2012-05-26 359 /* convert to decimal */
fbf7f7b4e2ae40 Markus Franke 2012-05-26 360 val = val - 0x30;
fbf7f7b4e2ae40 Markus Franke 2012-05-26 361 if (val != 0 && val != 1)
fbf7f7b4e2ae40 Markus Franke 2012-05-26 362 return -EINVAL;
fbf7f7b4e2ae40 Markus Franke 2012-05-26 363
fbf7f7b4e2ae40 Markus Franke 2012-05-26 364 /* set the new value */
fbf7f7b4e2ae40 Markus Franke 2012-05-26 365 w1_enable_crccheck = val;
fbf7f7b4e2ae40 Markus Franke 2012-05-26 366
fbf7f7b4e2ae40 Markus Franke 2012-05-26 367 return sizeof(w1_enable_crccheck);
fbf7f7b4e2ae40 Markus Franke 2012-05-26 368 }
fbf7f7b4e2ae40 Markus Franke 2012-05-26 369
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 27591 bytes --]
^ permalink raw reply
* [GIT PULL] Please pull powerpc/linux.git powerpc-5.12-2 tag
From: Michael Ellerman @ 2021-03-07 10:25 UTC (permalink / raw)
To: Linus Torvalds
Cc: feng.tang, atrajeev, uwe, peterz, gregkh, groug, linux-kernel,
ljp, npiggin, jniethe5, linuxppc-dev
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA256
Hi Linus,
Please pull powerpc fixes for 5.12:
The following changes since commit fe07bfda2fb9cdef8a4d4008a409bb02f35f1bd8:
Linux 5.12-rc1 (2021-02-28 16:05:19 -0800)
are available in the git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git tags/powerpc-5.12-2
for you to fetch changes up to 5c88a17e15795226b56d83f579cbb9b7a4864f79:
powerpc/sstep: Fix VSX instruction emulation (2021-03-02 22:41:51 +1100)
- ------------------------------------------------------------------
powerpc fixes for 5.12 #2
One non-fix, the conversion of vio_driver->remove() to return void, which
touches various powerpc specific drivers.
Fix the privilege checks we do in our perf handling, which could cause soft/hard
lockups in some configurations.
Fix a bug with IRQ affinity seen on kdump kernels when CPU 0 is offline in the
second kernel.
Fix missed page faults after mprotect(..., PROT_NONE) on 603 (32-bit).
Fix a bug in our VSX (vector) instruction emulation, which should only be seen
when doing VSX ops to cache inhibited mappings.
Three commits fixing various build issues with obscure configurations.
Thanks to:
Athira Rajeev, Cédric Le Goater, Christophe Leroy, Christoph Plattner, Greg
Kurz, Jordan Niethe, Laurent Vivier, Ravi Bangoria, Tyrel Datwyler, Uwe
Kleine-König.
- ------------------------------------------------------------------
Athira Rajeev (1):
powerpc/perf: Fix handling of privilege level checks in perf interrupt context
Christophe Leroy (3):
powerpc/603: Fix protection of user pages mapped with PROT_NONE
powerpc/syscall: Force inlining of __prep_irq_for_enabled_exit()
powerpc: Force inlining of mmu_has_feature to fix build failure
Greg Kurz (1):
powerpc/pseries: Don't enforce MSI affinity with kdump
Jordan Niethe (1):
powerpc/sstep: Fix VSX instruction emulation
Michael Ellerman (1):
powerpc/4xx: Fix build errors from mfdcr()
Uwe Kleine-König (1):
vio: make remove callback return void
arch/powerpc/include/asm/dcr-native.h | 8 +++----
arch/powerpc/include/asm/mmu.h | 4 ++--
arch/powerpc/include/asm/vio.h | 2 +-
arch/powerpc/kernel/head_book3s_32.S | 9 ++++---
arch/powerpc/kernel/interrupt.c | 2 +-
arch/powerpc/lib/sstep.c | 4 ++--
arch/powerpc/perf/core-book3s.c | 4 ++--
arch/powerpc/platforms/pseries/msi.c | 25 ++++++++++++++++++--
arch/powerpc/platforms/pseries/vio.c | 7 +++---
drivers/char/hw_random/pseries-rng.c | 3 +--
drivers/char/tpm/tpm_ibmvtpm.c | 4 +---
drivers/crypto/nx/nx-842-pseries.c | 4 +---
drivers/crypto/nx/nx.c | 4 +---
drivers/misc/ibmvmc.c | 4 +---
drivers/net/ethernet/ibm/ibmveth.c | 4 +---
drivers/net/ethernet/ibm/ibmvnic.c | 5 +---
drivers/scsi/ibmvscsi/ibmvfc.c | 3 +--
drivers/scsi/ibmvscsi/ibmvscsi.c | 4 +---
drivers/scsi/ibmvscsi_tgt/ibmvscsi_tgt.c | 4 +---
drivers/tty/hvc/hvcs.c | 4 +---
20 files changed, 55 insertions(+), 53 deletions(-)
-----BEGIN PGP SIGNATURE-----
iQIzBAEBCAAdFiEEJFGtCPCthwEv2Y/bUevqPMjhpYAFAmBEqeAACgkQUevqPMjh
pYALkRAAhMzfrU//Dw1pykwjlJhF6TccHSjmLh5y5V3qq95yXdhogx/XamGsuxZx
s0hAET3La+2HC75ZVtLbfDct1ZuFNUAqR7n/pyPINTqhAYPeB9VoVRSl7nLL8U19
dhxPKmtb1dBvEQFxtBO7Q5dka3S33sc1dX/ATqhXNeHpEgsN6FT99qOXzOHo3VdR
X/i+yXIoTh72f565sxxW/Ca2apy0cfdwwAwsK+S63s9Sxmsx+sF3mtY/rZs04rzg
JzsI14empb8nvz8EUJfk+In4uk9+BZxRF92OTGHvCkp6ptv+JtYT2A4h/JWnr0Vq
kS40Xwqwa62tvevUgKYcjSvaCsoC5sTaETqV/5WPIIKvXjVe5DMoZWv/JqOGRGHF
i4IbnIBEXYodcKaRto7/yNFgCvaInKjVHC1qX46ft809mfRIJlz0akUNwvIl8nRa
o479MJpBVtSf+3e491InY26RCpwaBmEB2KM3pR30TZV4jFSWZN55cnJuVW1wj0Gg
b1ObTrjJ/WjnIDUxLN2Hq4f60RWWhfxJtq9IplnWNM9kPx9AJRaUvlzS0Z2A7yFa
eSNCJlV2aXhJUGOYhVM7FMgHd0HcmF00LC22X+mfxlKbAEm1ys9VmoFPhtnkUMLX
menb5yEDGlVq+bDa0ChBUYmFx8jHbyF88YRo16TmtutW4trAr4I=
=lgtl
-----END PGP SIGNATURE-----
^ permalink raw reply
* [powerpc:next-test 15/17] arch/powerpc/mm/book3s64/hash_utils.c:1986:6: warning: no previous prototype for 'kfence_protect_page'
From: kernel test robot @ 2021-03-07 13:18 UTC (permalink / raw)
To: Christophe Leroy; +Cc: linuxppc-dev, kbuild-all
[-- Attachment #1: Type: text/plain, Size: 1897 bytes --]
tree: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next-test
head: 7c6d5b4b9e8a472043a26ccc22092aebbe65ca68
commit: 0f19bac474e0f9ce9b38a7ce00c57abb321338d1 [15/17] powerpc: Enable KFENCE on BOOK3S/64
config: powerpc-allyesconfig (attached as .config)
compiler: powerpc64-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id=0f19bac474e0f9ce9b38a7ce00c57abb321338d1
git remote add powerpc https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git
git fetch --no-tags powerpc next-test
git checkout 0f19bac474e0f9ce9b38a7ce00c57abb321338d1
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=powerpc
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
>> arch/powerpc/mm/book3s64/hash_utils.c:1986:6: warning: no previous prototype for 'kfence_protect_page' [-Wmissing-prototypes]
1986 | bool kfence_protect_page(unsigned long addr, bool protect)
| ^~~~~~~~~~~~~~~~~~~
vim +/kfence_protect_page +1986 arch/powerpc/mm/book3s64/hash_utils.c
1984
1985 #ifdef CONFIG_KFENCE
> 1986 bool kfence_protect_page(unsigned long addr, bool protect)
1987 {
1988 unsigned long lmi = __pa(addr) >> PAGE_SHIFT;
1989
1990 if (protect)
1991 kernel_unmap_linear_page(addr, lmi);
1992 else
1993 kernel_map_linear_page(addr, lmi);
1994
1995 return true;
1996 }
1997 #endif
1998
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 72777 bytes --]
^ permalink raw reply
* Re: [PATCH -next] pci/controller/dwc: convert comma to semicolon
From: Krzysztof Wilczyński @ 2021-03-07 18:36 UTC (permalink / raw)
To: Lorenzo Pieralisi
Cc: robh, roy.zang, minghuan.Lian, linux-pci, linux-kernel,
Zheng Yongjun, Bjorn Helgaas, linux-arm-kernel, linuxppc-dev,
mingkai.hu
In-Reply-To: <20210115113654.GA22508@e121166-lin.cambridge.arm.com>
Hi,
[...]
> I would request NXP maintainers to take this patch, rewrite it as
> Bjorn requested and resend it as fast as possible, this is a very
> relevant fix.
[...]
Looking at the state of the pci-layerscape-ep.c file in Linus' tree,
this still hasn't been fixed, and it has been a while.
NXP folks, are you intend to pick this up? Do let us know.
Krzysztof
^ permalink raw reply
* Re: [GIT PULL] Please pull powerpc/linux.git powerpc-5.12-2 tag
From: pr-tracker-bot @ 2021-03-07 21:30 UTC (permalink / raw)
To: Michael Ellerman
Cc: feng.tang, atrajeev, uwe, peterz, gregkh, linuxppc-dev, groug,
npiggin, linux-kernel, ljp, jniethe5, Linus Torvalds
In-Reply-To: <87mtvfqn03.fsf@mpe.ellerman.id.au>
The pull request you sent on Sun, 07 Mar 2021 21:25:16 +1100:
> https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git tags/powerpc-5.12-2
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/fbda7904302499dd7ffc073a3c84eb7c9275db0a
Thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/prtracker.html
^ permalink raw reply
* Errant readings on LM81 with T2080 SoC
From: Chris Packham @ 2021-03-07 22:52 UTC (permalink / raw)
To: jdelvare@suse.com, Guenter Roeck
Cc: linux-hwmon@vger.kernel.org, linuxppc-dev@lists.ozlabs.org,
linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org
Hi,
I've got a system using a PowerPC T2080 SoC and among other things has
an LM81 hwmon chip.
Under a high CPU load we see errant readings from the LM81 as well as
actual failures. It's the errant readings that cause the most concern
since we can easily ignore the read errors in our monitoring application
(although it would be better if they weren't there at all).
I'm able to reproduce this with a test application[0] that artificially
creates a high CPU load then by repeatedly checking for the all-1s
values from the LM81 datasheet[1](page 17). The all-1s readings stick
out as they are obviously higher than the voltage rails that are
connected and disagree with measurements taken with a multimeter.
Here's the output from my device
[root@linuxbox ~]# cpuload 90&
[root@linuxbox ~]# (while true; do cat /sys/class/hwmon/hwmon0/in*_input
| grep '3320\|4383\|6641\|15930\|3586'; sleep 1; done)&
3586
3586
cat: read error: No such device or address
cat: read error: No such device or address
3320
3320
3586
3586
6641
6641
4383
4383
Fundamentally I think this is a problem with the fact that the LM81 is
an SMBus device but the T2080 (and other Freescale SoCs) uses i2c and we
emulate SMBus. I suspect the errant readings are when we don't get round
to completing the read within the timeout specified by the SMBus
specification. Depending on when that happens we either fail the
transfer or interpret the result as all-1s.
[0] - https://gist.github.com/cpackham/6356a3a943accebb228135dc10daf721
[1] - https://www.ti.com/lit/ds/symlink/lm81.pdf
^ permalink raw reply
* [powerpc:next-test] BUILD SUCCESS WITH WARNING 7c6d5b4b9e8a472043a26ccc22092aebbe65ca68
From: kernel test robot @ 2021-03-07 23:09 UTC (permalink / raw)
To: Michael Ellerman; +Cc: linuxppc-dev
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next-test
branch HEAD: 7c6d5b4b9e8a472043a26ccc22092aebbe65ca68 powerpc/pseries: export LPAR security flavor in lparcfg
Warning reports:
https://lore.kernel.org/linuxppc-dev/202103072122.wpIjBOYV-lkp@intel.com
possible Warning in current branch:
arch/powerpc/mm/book3s64/hash_utils.c:1986:6: warning: no previous prototype for 'kfence_protect_page' [-Wmissing-prototypes]
Warning ids grouped by kconfigs:
gcc_recent_errors
|-- powerpc-allmodconfig
| `-- arch-powerpc-mm-book3s64-hash_utils.c:warning:no-previous-prototype-for-kfence_protect_page
|-- powerpc-allyesconfig
| `-- arch-powerpc-mm-book3s64-hash_utils.c:warning:no-previous-prototype-for-kfence_protect_page
`-- powerpc64-allyesconfig
`-- arch-powerpc-mm-book3s64-hash_utils.c:warning:no-previous-prototype-for-kfence_protect_page
elapsed time: 723m
configs tested: 172
configs skipped: 2
gcc tested configs:
arm defconfig
arm64 allyesconfig
arm64 defconfig
arm allyesconfig
arm allmodconfig
mips ip28_defconfig
mips capcella_defconfig
arm mini2440_defconfig
arm spitz_defconfig
arm pxa168_defconfig
mips gcw0_defconfig
sh se7724_defconfig
arc nsim_700_defconfig
powerpc mpc83xx_defconfig
mips decstation_64_defconfig
arm clps711x_defconfig
arc allyesconfig
parisc defconfig
powerpc klondike_defconfig
sh titan_defconfig
xtensa smp_lx200_defconfig
powerpc ge_imp3a_defconfig
arm mainstone_defconfig
mips allmodconfig
arm dove_defconfig
sh shx3_defconfig
s390 zfcpdump_defconfig
powerpc akebono_defconfig
arc hsdk_defconfig
powerpc warp_defconfig
mips loongson3_defconfig
m68k defconfig
riscv nommu_k210_defconfig
sparc allyesconfig
mips maltaup_defconfig
sh sh7785lcr_defconfig
powerpc chrp32_defconfig
mips qi_lb60_defconfig
arm mv78xx0_defconfig
arm spear3xx_defconfig
arc axs103_defconfig
arc axs101_defconfig
powerpc mpc866_ads_defconfig
mips workpad_defconfig
powerpc mpc8313_rdb_defconfig
arm at91_dt_defconfig
powerpc powernv_defconfig
csky alldefconfig
mips nlm_xlr_defconfig
xtensa common_defconfig
sh defconfig
sh se7722_defconfig
arm s5pv210_defconfig
arm hisi_defconfig
ia64 bigsur_defconfig
sh espt_defconfig
m68k sun3x_defconfig
sparc sparc64_defconfig
sh r7780mp_defconfig
arc nsimosci_hs_smp_defconfig
parisc generic-64bit_defconfig
powerpc bamboo_defconfig
arc tb10x_defconfig
powerpc mpc885_ads_defconfig
sh sdk7786_defconfig
arm am200epdkit_defconfig
mips gpr_defconfig
arm cm_x300_defconfig
arc vdk_hs38_defconfig
sh polaris_defconfig
arc vdk_hs38_smp_defconfig
powerpc tqm8555_defconfig
mips rbtx49xx_defconfig
arm pxa3xx_defconfig
powerpc pasemi_defconfig
arc axs103_smp_defconfig
powerpc tqm8560_defconfig
microblaze defconfig
sh sdk7780_defconfig
arm jornada720_defconfig
powerpc bluestone_defconfig
mips ip27_defconfig
xtensa iss_defconfig
mips tb0226_defconfig
ia64 allmodconfig
ia64 defconfig
ia64 allyesconfig
m68k allmodconfig
m68k allyesconfig
nds32 defconfig
nios2 allyesconfig
csky defconfig
alpha defconfig
alpha allyesconfig
xtensa allyesconfig
h8300 allyesconfig
arc defconfig
sh allmodconfig
s390 allyesconfig
s390 allmodconfig
parisc allyesconfig
s390 defconfig
nios2 defconfig
nds32 allnoconfig
i386 allyesconfig
sparc defconfig
i386 tinyconfig
i386 defconfig
mips allyesconfig
powerpc allyesconfig
powerpc allmodconfig
powerpc allnoconfig
x86_64 randconfig-a006-20210308
x86_64 randconfig-a001-20210308
x86_64 randconfig-a004-20210308
x86_64 randconfig-a002-20210308
x86_64 randconfig-a005-20210308
x86_64 randconfig-a003-20210308
i386 randconfig-a005-20210307
i386 randconfig-a003-20210307
i386 randconfig-a002-20210307
i386 randconfig-a004-20210307
i386 randconfig-a006-20210307
i386 randconfig-a001-20210307
i386 randconfig-a005-20210308
i386 randconfig-a003-20210308
i386 randconfig-a002-20210308
i386 randconfig-a006-20210308
i386 randconfig-a004-20210308
i386 randconfig-a001-20210308
x86_64 randconfig-a013-20210307
x86_64 randconfig-a016-20210307
x86_64 randconfig-a015-20210307
x86_64 randconfig-a014-20210307
x86_64 randconfig-a012-20210307
x86_64 randconfig-a011-20210307
i386 randconfig-a016-20210307
i386 randconfig-a012-20210307
i386 randconfig-a013-20210307
i386 randconfig-a014-20210307
i386 randconfig-a011-20210307
i386 randconfig-a015-20210307
i386 randconfig-a016-20210308
i386 randconfig-a012-20210308
i386 randconfig-a014-20210308
i386 randconfig-a013-20210308
i386 randconfig-a011-20210308
i386 randconfig-a015-20210308
riscv allyesconfig
riscv nommu_virt_defconfig
riscv allnoconfig
riscv defconfig
riscv rv32_defconfig
riscv allmodconfig
x86_64 allyesconfig
x86_64 rhel-7.6-kselftests
x86_64 defconfig
x86_64 rhel-8.3
x86_64 rhel-8.3-kbuiltin
x86_64 kexec
clang tested configs:
x86_64 randconfig-a006-20210307
x86_64 randconfig-a001-20210307
x86_64 randconfig-a004-20210307
x86_64 randconfig-a005-20210307
x86_64 randconfig-a002-20210307
x86_64 randconfig-a003-20210307
x86_64 randconfig-a013-20210308
x86_64 randconfig-a016-20210308
x86_64 randconfig-a015-20210308
x86_64 randconfig-a014-20210308
x86_64 randconfig-a011-20210308
x86_64 randconfig-a012-20210308
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
^ permalink raw reply
* [powerpc:merge] BUILD SUCCESS 103ebc760cccd96ab1ebc3558881106d48efdcea
From: kernel test robot @ 2021-03-07 23:09 UTC (permalink / raw)
To: Michael Ellerman; +Cc: linuxppc-dev
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git merge
branch HEAD: 103ebc760cccd96ab1ebc3558881106d48efdcea Automatic merge of 'master' into merge (2021-03-07 21:07)
elapsed time: 723m
configs tested: 150
configs skipped: 2
The following configs have been built successfully.
More configs may be tested in the coming days.
gcc tested configs:
arm defconfig
arm64 allyesconfig
arm64 defconfig
arm allyesconfig
arm allmodconfig
mips ip28_defconfig
mips capcella_defconfig
arm mini2440_defconfig
arm spitz_defconfig
arm pxa168_defconfig
mips gcw0_defconfig
sh se7724_defconfig
arc nsim_700_defconfig
powerpc mpc83xx_defconfig
mips decstation_64_defconfig
arm clps711x_defconfig
arc allyesconfig
parisc defconfig
powerpc klondike_defconfig
sh titan_defconfig
xtensa smp_lx200_defconfig
powerpc ge_imp3a_defconfig
arm mainstone_defconfig
mips allmodconfig
arm dove_defconfig
sh shx3_defconfig
arc axs101_defconfig
powerpc mpc866_ads_defconfig
mips workpad_defconfig
powerpc mpc8313_rdb_defconfig
mips maltaup_defconfig
mips loongson3_defconfig
powerpc mpc834x_itx_defconfig
alpha alldefconfig
sh sh7763rdp_defconfig
openrisc simple_smp_defconfig
arm at91_dt_defconfig
powerpc powernv_defconfig
csky alldefconfig
mips nlm_xlr_defconfig
xtensa common_defconfig
sh defconfig
sh se7722_defconfig
arm s5pv210_defconfig
arm hisi_defconfig
ia64 bigsur_defconfig
powerpc mpc885_ads_defconfig
sh sdk7786_defconfig
arm am200epdkit_defconfig
mips gpr_defconfig
arm cm_x300_defconfig
arc vdk_hs38_defconfig
sh polaris_defconfig
arc vdk_hs38_smp_defconfig
powerpc tqm8555_defconfig
mips rbtx49xx_defconfig
arm pxa3xx_defconfig
powerpc pasemi_defconfig
arc axs103_smp_defconfig
powerpc tqm8560_defconfig
microblaze defconfig
powerpc bluestone_defconfig
mips ip27_defconfig
xtensa iss_defconfig
mips tb0226_defconfig
ia64 allmodconfig
ia64 defconfig
ia64 allyesconfig
m68k allmodconfig
m68k defconfig
m68k allyesconfig
nds32 defconfig
nios2 allyesconfig
csky defconfig
alpha defconfig
alpha allyesconfig
xtensa allyesconfig
h8300 allyesconfig
arc defconfig
sh allmodconfig
s390 allyesconfig
s390 allmodconfig
parisc allyesconfig
s390 defconfig
nios2 defconfig
nds32 allnoconfig
i386 allyesconfig
sparc allyesconfig
sparc defconfig
i386 tinyconfig
i386 defconfig
mips allyesconfig
powerpc allyesconfig
powerpc allmodconfig
powerpc allnoconfig
i386 randconfig-a005-20210307
i386 randconfig-a003-20210307
i386 randconfig-a002-20210307
i386 randconfig-a004-20210307
i386 randconfig-a006-20210307
i386 randconfig-a001-20210307
x86_64 randconfig-a013-20210307
x86_64 randconfig-a016-20210307
x86_64 randconfig-a015-20210307
x86_64 randconfig-a014-20210307
x86_64 randconfig-a012-20210307
x86_64 randconfig-a011-20210307
i386 randconfig-a016-20210308
i386 randconfig-a012-20210308
i386 randconfig-a014-20210308
i386 randconfig-a013-20210308
i386 randconfig-a011-20210308
i386 randconfig-a015-20210308
i386 randconfig-a016-20210307
i386 randconfig-a012-20210307
i386 randconfig-a013-20210307
i386 randconfig-a014-20210307
i386 randconfig-a011-20210307
i386 randconfig-a015-20210307
x86_64 randconfig-a006-20210308
x86_64 randconfig-a001-20210308
x86_64 randconfig-a004-20210308
x86_64 randconfig-a002-20210308
x86_64 randconfig-a005-20210308
x86_64 randconfig-a003-20210308
riscv nommu_k210_defconfig
riscv allyesconfig
riscv nommu_virt_defconfig
riscv allnoconfig
riscv defconfig
riscv rv32_defconfig
riscv allmodconfig
x86_64 allyesconfig
x86_64 rhel-7.6-kselftests
x86_64 defconfig
x86_64 rhel-8.3
x86_64 rhel-8.3-kbuiltin
x86_64 kexec
clang tested configs:
x86_64 randconfig-a006-20210307
x86_64 randconfig-a001-20210307
x86_64 randconfig-a004-20210307
x86_64 randconfig-a005-20210307
x86_64 randconfig-a002-20210307
x86_64 randconfig-a003-20210307
x86_64 randconfig-a013-20210308
x86_64 randconfig-a016-20210308
x86_64 randconfig-a015-20210308
x86_64 randconfig-a014-20210308
x86_64 randconfig-a011-20210308
x86_64 randconfig-a012-20210308
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
^ permalink raw reply
* Re: Errant readings on LM81 with T2080 SoC
From: Guenter Roeck @ 2021-03-08 0:31 UTC (permalink / raw)
To: Chris Packham, jdelvare@suse.com
Cc: linux-hwmon@vger.kernel.org, linuxppc-dev@lists.ozlabs.org,
linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org
In-Reply-To: <8e0a88ba-01e9-9bc1-c78b-20f26ce27d12@alliedtelesis.co.nz>
On 3/7/21 2:52 PM, Chris Packham wrote:
> Hi,
>
> I've got a system using a PowerPC T2080 SoC and among other things has
> an LM81 hwmon chip.
>
> Under a high CPU load we see errant readings from the LM81 as well as
> actual failures. It's the errant readings that cause the most concern
> since we can easily ignore the read errors in our monitoring application
> (although it would be better if they weren't there at all).
>
> I'm able to reproduce this with a test application[0] that artificially
> creates a high CPU load then by repeatedly checking for the all-1s
> values from the LM81 datasheet[1](page 17). The all-1s readings stick
> out as they are obviously higher than the voltage rails that are
> connected and disagree with measurements taken with a multimeter.
>
> Here's the output from my device
>
> [root@linuxbox ~]# cpuload 90&
> [root@linuxbox ~]# (while true; do cat /sys/class/hwmon/hwmon0/in*_input
> | grep '3320\|4383\|6641\|15930\|3586'; sleep 1; done)&
> 3586
> 3586
> cat: read error: No such device or address
> cat: read error: No such device or address
> 3320
> 3320
> 3586
> 3586
> 6641
> 6641
> 4383
> 4383
>
> Fundamentally I think this is a problem with the fact that the LM81 is
> an SMBus device but the T2080 (and other Freescale SoCs) uses i2c and we
> emulate SMBus. I suspect the errant readings are when we don't get round
> to completing the read within the timeout specified by the SMBus
> specification. Depending on when that happens we either fail the
> transfer or interpret the result as all-1s.
>
That is quite unlikely. Many sensor chips are SMBus chips connected to
i2c busses. It is much more likely that there is a bug in the T2080 i2c driver,
that the chip doesn't like the bulk read command issued through regmap, that
the chip has problems with the i2c bus speed, or that the i2c bus is noisy.
In this context, the "No such device or address" responses are very suspicious.
Those are reported by the i2c driver, not by the hwmon driver, and suggest
that the chip did not respond to a read request. Maybe it helps to enable
debugging to the i2c driver to see if it reports anything useful. Even
better might be to connect an i2c bus analyzer to the i2c bus and check
what is going on.
Guenter
^ permalink raw reply
* Re: Errant readings on LM81 with T2080 SoC
From: Chris Packham @ 2021-03-08 2:27 UTC (permalink / raw)
To: Guenter Roeck, jdelvare@suse.com
Cc: linux-hwmon@vger.kernel.org, linuxppc-dev@lists.ozlabs.org,
linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org
In-Reply-To: <96d660bc-17ab-4e0e-9a94-bce1737a8da1@roeck-us.net>
On 8/03/21 1:31 pm, Guenter Roeck wrote:
> On 3/7/21 2:52 PM, Chris Packham wrote:
>> Hi,
>>
>> I've got a system using a PowerPC T2080 SoC and among other things has
>> an LM81 hwmon chip.
>>
>> Under a high CPU load we see errant readings from the LM81 as well as
>> actual failures. It's the errant readings that cause the most concern
>> since we can easily ignore the read errors in our monitoring application
>> (although it would be better if they weren't there at all).
>>
>> I'm able to reproduce this with a test application[0] that artificially
>> creates a high CPU load then by repeatedly checking for the all-1s
>> values from the LM81 datasheet[1](page 17). The all-1s readings stick
>> out as they are obviously higher than the voltage rails that are
>> connected and disagree with measurements taken with a multimeter.
>>
>> Here's the output from my device
>>
>> [root@linuxbox ~]# cpuload 90&
>> [root@linuxbox ~]# (while true; do cat /sys/class/hwmon/hwmon0/in*_input
>> | grep '3320\|4383\|6641\|15930\|3586'; sleep 1; done)&
>> 3586
>> 3586
>> cat: read error: No such device or address
>> cat: read error: No such device or address
>> 3320
>> 3320
>> 3586
>> 3586
>> 6641
>> 6641
>> 4383
>> 4383
>>
>> Fundamentally I think this is a problem with the fact that the LM81 is
>> an SMBus device but the T2080 (and other Freescale SoCs) uses i2c and we
>> emulate SMBus. I suspect the errant readings are when we don't get round
>> to completing the read within the timeout specified by the SMBus
>> specification. Depending on when that happens we either fail the
>> transfer or interpret the result as all-1s.
>>
> That is quite unlikely. Many sensor chips are SMBus chips connected to
> i2c busses. It is much more likely that there is a bug in the T2080 i2c driver,
> that the chip doesn't like the bulk read command issued through regmap, that
> the chip has problems with the i2c bus speed, or that the i2c bus is noisy.
Perhaps something gets upset when interrupt processing is delayed
because of CPU load. I don't see the problem when there isn't a CPU load
so I think that eliminates board issues.
> In this context, the "No such device or address" responses are very suspicious.
> Those are reported by the i2c driver, not by the hwmon driver, and suggest
> that the chip did not respond to a read request. Maybe it helps to enable
> debugging to the i2c driver to see if it reports anything useful. Even
> better might be to connect an i2c bus analyzer to the i2c bus and check
> what is going on.
That's from -ENXIO which is used in only one place in i2c-mpc.c. I'll
enable some debug and see what we get.
>
> Guenter
^ permalink raw reply
* Re: [PATCH v4] powerpc/uprobes: Validation for prefixed instruction
From: Sandipan Das @ 2021-03-08 4:33 UTC (permalink / raw)
To: Ravi Bangoria
Cc: oleg, rostedt, linux-kernel, paulus, jniethe5, naveen.n.rao,
linuxppc-dev
In-Reply-To: <20210305115433.140769-1-ravi.bangoria@linux.ibm.com>
On 05/03/21 5:24 pm, Ravi Bangoria wrote:
> As per ISA 3.1, prefixed instruction should not cross 64-byte
> boundary. So don't allow Uprobe on such prefixed instruction.
>
> There are two ways probed instruction is changed in mapped pages.
> First, when Uprobe is activated, it searches for all the relevant
> pages and replace instruction in them. In this case, if that probe
> is on the 64-byte unaligned prefixed instruction, error out
> directly. Second, when Uprobe is already active and user maps a
> relevant page via mmap(), instruction is replaced via mmap() code
> path. But because Uprobe is invalid, entire mmap() operation can
> not be stopped. In this case just print an error and continue.
>
> Signed-off-by: Ravi Bangoria <ravi.bangoria@linux.ibm.com>
> Acked-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com>
> ---
> v3: https://lore.kernel.org/r/20210304050529.59391-1-ravi.bangoria@linux.ibm.com
> v3->v4:
> - CONFIG_PPC64 check was not required, remove it.
> - Use SZ_ macros instead of hardcoded numbers.
>
Acked-by: Sandipan Das <sandipan@linux.ibm.com>
^ permalink raw reply
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