* Re: [PATCH] powerpc/vdso: Separate vvar vma from vdso
From: Christophe Leroy @ 2021-03-27 17:19 UTC (permalink / raw)
To: Dmitry Safonov, linux-kernel
Cc: Dmitry Safonov, stable, Andrei Vagin, Paul Mackerras,
Andy Lutomirski, Laurent Dufour, linuxppc-dev
In-Reply-To: <20210326191720.138155-1-dima@arista.com>
Le 26/03/2021 à 20:17, Dmitry Safonov a écrit :
> Since commit 511157ab641e ("powerpc/vdso: Move vdso datapage up front")
> VVAR page is in front of the VDSO area. In result it breaks CRIU
> (Checkpoint Restore In Userspace) [1], where CRIU expects that "[vdso]"
> from /proc/../maps points at ELF/vdso image, rather than at VVAR data page.
> Laurent made a patch to keep CRIU working (by reading aux vector).
> But I think it still makes sence to separate two mappings into different
> VMAs. It will also make ppc64 less "special" for userspace and as
> a side-bonus will make VVAR page un-writable by debugger (which previously
> would COW page and can be unexpected).
>
> I opportunistically Cc stable on it: I understand that usually such
> stuff isn't a stable material, but that will allow us in CRIU have
> one workaround less that is needed just for one release (v5.11) on
> one platform (ppc64), which we otherwise have to maintain.
Why is that a workaround, and why for one release only ? I think the solution proposed by Laurentto
use the aux vector AT_SYSINFO_EHDR should work with any past and future release.
> I wouldn't go as far as to say that the commit 511157ab641e is ABI
> regression as no other userspace got broken, but I'd really appreciate
> if it gets backported to v5.11 after v5.12 is released, so as not
> to complicate already non-simple CRIU-vdso code. Thanks!
>
> Cc: Andrei Vagin <avagin@gmail.com>
> Cc: Andy Lutomirski <luto@kernel.org>
> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> Cc: Christophe Leroy <christophe.leroy@csgroup.eu>
> Cc: Laurent Dufour <ldufour@linux.ibm.com>
> Cc: Michael Ellerman <mpe@ellerman.id.au>
> Cc: Paul Mackerras <paulus@samba.org>
> Cc: linuxppc-dev@lists.ozlabs.org
> Cc: stable@vger.kernel.org # v5.11
> [1]: https://github.com/checkpoint-restore/criu/issues/1417
> Signed-off-by: Dmitry Safonov <dima@arista.com>
> Tested-by: Christophe Leroy <christophe.leroy@csgroup.eu>
I tested it with sifreturn_vdso selftest and it worked, because that selftest doesn't involve VDSO data.
But if I do a mremap() on the VDSO text vma without remapping VVAR to keep the same distance between
the two vmas, gettimeofday() crashes. The reason is that the code obtains the address of the data by
calculating a fix difference from its own address with the below macro, the delta being resolved at
link time:
.macro get_datapage ptr
bcl 20, 31, .+4
999:
mflr \ptr
#if CONFIG_PPC_PAGE_SHIFT > 14
addis \ptr, \ptr, (_vdso_datapage - 999b)@ha
#endif
addi \ptr, \ptr, (_vdso_datapage - 999b)@l
.endm
So the datapage needs to remain at the same distance from the code at all time.
Wondering how the other architectures do to have two independant VMAs and be able to move one
independantly of the other.
Christophe
^ permalink raw reply
* Re: [PATCH v3 37/41] powerpc/32s: Move KUEP locking/unlocking in C
From: Christophe Leroy @ 2021-03-27 17:24 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman, npiggin
Cc: linuxppc-dev, linux-kernel
In-Reply-To: <4eadd873927e9a73c3d1dfe2f9497353465514cf.1615552867.git.christophe.leroy@csgroup.eu>
Le 12/03/2021 à 13:50, Christophe Leroy a écrit :
> This can be done in C, do it.
>
> Unrolling the loop gains approx. 15% performance.
>
> From now on, prepare_transfer_to_handler() is only for
> interrupts from kernel.
>
> Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
> ---
> arch/powerpc/include/asm/book3s/32/kup.h | 31 -------------------
> arch/powerpc/include/asm/interrupt.h | 6 +++-
> arch/powerpc/include/asm/kup.h | 8 +++++
> arch/powerpc/kernel/entry_32.S | 16 ----------
> arch/powerpc/kernel/head_32.h | 3 ++
> arch/powerpc/kernel/head_booke.h | 3 ++
> arch/powerpc/kernel/interrupt.c | 4 +++
> arch/powerpc/mm/book3s32/Makefile | 1 +
> arch/powerpc/mm/book3s32/kuep.c | 38 ++++++++++++++++++++++++
> 9 files changed, 62 insertions(+), 48 deletions(-)
> create mode 100644 arch/powerpc/mm/book3s32/kuep.c
>
> diff --git a/arch/powerpc/mm/book3s32/kuep.c b/arch/powerpc/mm/book3s32/kuep.c
> new file mode 100644
> index 000000000000..c70532568a28
> --- /dev/null
> +++ b/arch/powerpc/mm/book3s32/kuep.c
> @@ -0,0 +1,38 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +#include <asm/reg.h>
> +#include <asm/task_size_32.h>
> +#include <asm/mmu.h>
Need to add <asm/kup.h> to make Robot happy (missing prototypes of kuep_lock() and kuep_unlock())
> +
> +#define KUEP_UPDATE_TWO_USER_SEGMENTS(n) do { \
> + if (TASK_SIZE > ((n) << 28)) \
> + mtsr(val1, (n) << 28); \
> + if (TASK_SIZE > (((n) + 1) << 28)) \
> + mtsr(val2, ((n) + 1) << 28); \
> + val1 = (val1 + 0x222) & 0xf0ffffff; \
> + val2 = (val2 + 0x222) & 0xf0ffffff; \
> +} while (0)
> +
> +static __always_inline void kuep_update(u32 val)
> +{
> + int val1 = val;
> + int val2 = (val + 0x111) & 0xf0ffffff;
> +
> + KUEP_UPDATE_TWO_USER_SEGMENTS(0);
> + KUEP_UPDATE_TWO_USER_SEGMENTS(2);
> + KUEP_UPDATE_TWO_USER_SEGMENTS(4);
> + KUEP_UPDATE_TWO_USER_SEGMENTS(6);
> + KUEP_UPDATE_TWO_USER_SEGMENTS(8);
> + KUEP_UPDATE_TWO_USER_SEGMENTS(10);
> + KUEP_UPDATE_TWO_USER_SEGMENTS(12);
> + KUEP_UPDATE_TWO_USER_SEGMENTS(14);
> +}
> +
> +void kuep_lock(void)
> +{
> + kuep_update(mfsr(0) | SR_NX);
> +}
> +
> +void kuep_unlock(void)
> +{
> + kuep_update(mfsr(0) & ~SR_NX);
> +}
>
^ permalink raw reply
* Re: [PATCH] powerpc/vdso: Separate vvar vma from vdso
From: Dmitry Safonov @ 2021-03-27 17:43 UTC (permalink / raw)
To: Christophe Leroy, linux-kernel
Cc: Dmitry Safonov, stable, Andrei Vagin, Paul Mackerras,
Andy Lutomirski, Laurent Dufour, linuxppc-dev
In-Reply-To: <52562f46-6767-ba04-7301-04c6209fe4f1@csgroup.eu>
Hi Christophe,
On 3/27/21 5:19 PM, Christophe Leroy wrote:
[..]
>> I opportunistically Cc stable on it: I understand that usually such
>> stuff isn't a stable material, but that will allow us in CRIU have
>> one workaround less that is needed just for one release (v5.11) on
>> one platform (ppc64), which we otherwise have to maintain.
>
> Why is that a workaround, and why for one release only ? I think the
> solution proposed by Laurentto use the aux vector AT_SYSINFO_EHDR should
> work with any past and future release.
Yeah, I guess.
Previously, (before v5.11/power) all kernels had ELF start at "[vdso]"
VMA start, now we'll have to carry the offset in the VMA. Probably, not
the worst thing, but as it will be only for v5.11 release it can break,
so needs separate testing.
Kinda life was a bit easier without this additional code.
>> I wouldn't go as far as to say that the commit 511157ab641e is ABI
>> regression as no other userspace got broken, but I'd really appreciate
>> if it gets backported to v5.11 after v5.12 is released, so as not
>> to complicate already non-simple CRIU-vdso code. Thanks!
>>
>> Cc: Andrei Vagin <avagin@gmail.com>
>> Cc: Andy Lutomirski <luto@kernel.org>
>> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>> Cc: Christophe Leroy <christophe.leroy@csgroup.eu>
>> Cc: Laurent Dufour <ldufour@linux.ibm.com>
>> Cc: Michael Ellerman <mpe@ellerman.id.au>
>> Cc: Paul Mackerras <paulus@samba.org>
>> Cc: linuxppc-dev@lists.ozlabs.org
>> Cc: stable@vger.kernel.org # v5.11
>> [1]: https://github.com/checkpoint-restore/criu/issues/1417
>> Signed-off-by: Dmitry Safonov <dima@arista.com>
>> Tested-by: Christophe Leroy <christophe.leroy@csgroup.eu>
>
> I tested it with sifreturn_vdso selftest and it worked, because that
> selftest doesn't involve VDSO data.
Thanks again on helping with testing it, I appreciate it!
> But if I do a mremap() on the VDSO text vma without remapping VVAR to
> keep the same distance between the two vmas, gettimeofday() crashes. The
> reason is that the code obtains the address of the data by calculating a
> fix difference from its own address with the below macro, the delta
> being resolved at link time:
>
> .macro get_datapage ptr
> bcl 20, 31, .+4
> 999:
> mflr \ptr
> #if CONFIG_PPC_PAGE_SHIFT > 14
> addis \ptr, \ptr, (_vdso_datapage - 999b)@ha
> #endif
> addi \ptr, \ptr, (_vdso_datapage - 999b)@l
> .endm
>
> So the datapage needs to remain at the same distance from the code at
> all time.
>
> Wondering how the other architectures do to have two independent VMAs
> and be able to move one independently of the other.
It's alright as far as I know. If userspace remaps vdso/vvar it should
be aware of this (CRIU keeps this in mind, also old vdso image is dumped
to compare on restore with the one that the host has).
Thanks,
Dmitry
^ permalink raw reply
* Re: [PATCH 2/4] exec: remove compat_do_execve
From: Sergei Shtylyov @ 2021-03-27 19:56 UTC (permalink / raw)
To: Christoph Hellwig, Eric W. Biederman, Al Viro
Cc: linux-arch, linux-s390, linux-parisc, Arnd Bergmann, Brian Gerst,
x86, linux-mips, linux-kernel, linux-fsdevel, Luis Chamberlain,
sparclinux, linuxppc-dev, linux-arm-kernel
In-Reply-To: <20210326143831.1550030-3-hch@lst.de>
On 3/26/21 5:38 PM, Christoph Hellwig wrote:
> Just call compat_do_execve instead.
compat_do_execveat(), maybe?
> Signed-off-by: Christoph Hellwig <hch@lst.de>
> ---
> fs/exec.c | 17 +----------------
> 1 file changed, 1 insertion(+), 16 deletions(-)
>
> diff --git a/fs/exec.c b/fs/exec.c
> index b63fb020909075..06e07278b456fa 100644
> --- a/fs/exec.c
> +++ b/fs/exec.c
[...]
> @@ -2072,7 +2057,7 @@ COMPAT_SYSCALL_DEFINE3(execve, const char __user *, filename,
> const compat_uptr_t __user *, argv,
> const compat_uptr_t __user *, envp)
> {
> - return compat_do_execve(getname(filename), argv, envp);
> + return compat_do_execveat(AT_FDCWD, getname(filename), argv, envp, 0);
> }
>
> COMPAT_SYSCALL_DEFINE5(execveat, int, fd,
MBR, Sergei
^ permalink raw reply
* [PATCH] powerpc: Fix HAVE_HARDLOCKUP_DETECTOR_ARCH build configuration
From: Chen Huang @ 2021-03-27 9:49 UTC (permalink / raw)
To: Michael Ellerman, Benjamin Herrenschmidt, Paul Mackerras
Cc: Don Zickus, Chen Huang, linux-kernel, Nicholas Piggin, Hulk Robot,
Andrew Morton, linuxppc-dev
When compiling the powerpc with the SMP disabled, it shows the issue:
arch/powerpc/kernel/watchdog.c: In function ‘watchdog_smp_panic’:
arch/powerpc/kernel/watchdog.c:177:4: error: implicit declaration of function ‘smp_send_nmi_ipi’; did you mean ‘smp_send_stop’? [-Werror=implicit-function-declaration]
177 | smp_send_nmi_ipi(c, wd_lockup_ipi, 1000000);
| ^~~~~~~~~~~~~~~~
| smp_send_stop
cc1: all warnings being treated as errors
make[2]: *** [scripts/Makefile.build:273: arch/powerpc/kernel/watchdog.o] Error 1
make[1]: *** [scripts/Makefile.build:534: arch/powerpc/kernel] Error 2
make: *** [Makefile:1980: arch/powerpc] Error 2
make: *** Waiting for unfinished jobs....
We found that powerpc used ipi to implement hardlockup watchdog, so the
HAVE_HARDLOCKUP_DETECTOR_ARCH should depend on the SMP.
Fixes: 2104180a5369 ("powerpc/64s: implement arch-specific hardlockup watchdog")
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Chen Huang <chenhuang5@huawei.com>
---
arch/powerpc/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 764df010baee..2d4f37b117ce 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -225,7 +225,7 @@ config PPC
select HAVE_LIVEPATCH if HAVE_DYNAMIC_FTRACE_WITH_REGS
select HAVE_MOD_ARCH_SPECIFIC
select HAVE_NMI if PERF_EVENTS || (PPC64 && PPC_BOOK3S)
- select HAVE_HARDLOCKUP_DETECTOR_ARCH if (PPC64 && PPC_BOOK3S)
+ select HAVE_HARDLOCKUP_DETECTOR_ARCH if PPC64 && PPC_BOOK3S && SMP
select HAVE_OPTPROBES if PPC64
select HAVE_PERF_EVENTS
select HAVE_PERF_EVENTS_NMI if PPC64
--
2.17.1
^ permalink raw reply related
* [PATCH v5 0/7] riscv: Add qspinlock/qrwlock
From: guoren @ 2021-03-28 6:30 UTC (permalink / raw)
To: guoren
Cc: linux-arch, linux-xtensa, Guo Ren, linux-kernel, linux-csky,
openrisc, sparclinux, linux-riscv, linuxppc-dev
From: Guo Ren <guoren@linux.alibaba.com>
Current riscv is still using baby spinlock implementation. It'll cause
fairness and cache line bouncing problems. Many people are involved
and pay the efforts to improve it:
- The first version of patch was made in 2019.1:
https://lore.kernel.org/linux-riscv/20190211043829.30096-1-michaeljclark@mac.com/#r
- The second version was made in 2020.11:
https://lore.kernel.org/linux-riscv/1606225437-22948-2-git-send-email-guoren@kernel.org/
- A good discussion at Platform HSC.2021-03-08:
https://drive.google.com/drive/folders/1ooqdnIsYx7XKor5O1XTtM6D1CHp4hc0p
Hope your comments and Tested-by or Co-developed-by or Reviewed-by ...
Let's kick the qspinlock into riscv right now (Also for the
architecture which hasn't xchg16 atomic instruction.)
Change V5:
- Fixup #endif comment typo by Waiman
- Remove cmpxchg coding convention patches which will get into a
separate patchset later by Arnd's advice
- Try to involve more architectures in the discussion
Change V4:
- Remove custom sub-word xchg implementation
- Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32 in locking/qspinlock
Change V3:
- Coding convention by Peter Zijlstra's advices
Change V2:
- Coding convention in cmpxchg.h
- Re-implement short xchg
- Remove char & cmpxchg implementations
Guo Ren (6):
locking/qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32
csky: Convert custom spinlock/rwlock to generic qspinlock/qrwlock
powerpc/qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32
openrisc: qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32
sparc: qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32
xtensa: qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32
Michael Clark (1):
riscv: Convert custom spinlock/rwlock to generic qspinlock/qrwlock
arch/csky/Kconfig | 2 +
arch/csky/include/asm/Kbuild | 2 +
arch/csky/include/asm/spinlock.h | 82 +--------------
arch/csky/include/asm/spinlock_types.h | 16 +--
arch/openrisc/Kconfig | 1 +
arch/powerpc/Kconfig | 1 +
arch/riscv/Kconfig | 3 +
arch/riscv/include/asm/Kbuild | 3 +
arch/riscv/include/asm/spinlock.h | 126 +-----------------------
arch/riscv/include/asm/spinlock_types.h | 15 +--
arch/sparc/Kconfig | 1 +
arch/xtensa/Kconfig | 1 +
kernel/Kconfig.locks | 3 +
kernel/locking/qspinlock.c | 46 +++++----
14 files changed, 49 insertions(+), 253 deletions(-)
--
2.17.1
^ permalink raw reply
* [PATCH v5 1/7] locking/qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32
From: guoren @ 2021-03-28 6:30 UTC (permalink / raw)
To: guoren
Cc: linux-arch, linux-xtensa, Guo Ren, Arnd Bergmann, Peter Zijlstra,
Will Deacon, linux-kernel, linux-csky, openrisc, Anup Patel,
sparclinux, Waiman Long, linux-riscv, linuxppc-dev, Ingo Molnar
In-Reply-To: <1616913028-83376-1-git-send-email-guoren@kernel.org>
From: Guo Ren <guoren@linux.alibaba.com>
Some architectures don't have sub-word swap atomic instruction,
they only have the full word's one.
The sub-word swap only improve the performance when:
NR_CPUS < 16K
* 0- 7: locked byte
* 8: pending
* 9-15: not used
* 16-17: tail index
* 18-31: tail cpu (+1)
The 9-15 bits are wasted to use xchg16 in xchg_tail.
Please let architecture select xchg16/xchg32 to implement
xchg_tail.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Will Deacon <will@kernel.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Waiman Long <longman@redhat.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Anup Patel <anup@brainfault.org>
---
kernel/Kconfig.locks | 3 +++
kernel/locking/qspinlock.c | 46 +++++++++++++++++++++-----------------
2 files changed, 28 insertions(+), 21 deletions(-)
diff --git a/kernel/Kconfig.locks b/kernel/Kconfig.locks
index 3de8fd11873b..d02f1261f73f 100644
--- a/kernel/Kconfig.locks
+++ b/kernel/Kconfig.locks
@@ -239,6 +239,9 @@ config LOCK_SPIN_ON_OWNER
config ARCH_USE_QUEUED_SPINLOCKS
bool
+config ARCH_USE_QUEUED_SPINLOCKS_XCHG32
+ bool
+
config QUEUED_SPINLOCKS
def_bool y if ARCH_USE_QUEUED_SPINLOCKS
depends on SMP
diff --git a/kernel/locking/qspinlock.c b/kernel/locking/qspinlock.c
index cbff6ba53d56..4bfaa969bd15 100644
--- a/kernel/locking/qspinlock.c
+++ b/kernel/locking/qspinlock.c
@@ -163,26 +163,6 @@ static __always_inline void clear_pending_set_locked(struct qspinlock *lock)
WRITE_ONCE(lock->locked_pending, _Q_LOCKED_VAL);
}
-/*
- * xchg_tail - Put in the new queue tail code word & retrieve previous one
- * @lock : Pointer to queued spinlock structure
- * @tail : The new queue tail code word
- * Return: The previous queue tail code word
- *
- * xchg(lock, tail), which heads an address dependency
- *
- * p,*,* -> n,*,* ; prev = xchg(lock, node)
- */
-static __always_inline u32 xchg_tail(struct qspinlock *lock, u32 tail)
-{
- /*
- * We can use relaxed semantics since the caller ensures that the
- * MCS node is properly initialized before updating the tail.
- */
- return (u32)xchg_relaxed(&lock->tail,
- tail >> _Q_TAIL_OFFSET) << _Q_TAIL_OFFSET;
-}
-
#else /* _Q_PENDING_BITS == 8 */
/**
@@ -206,6 +186,30 @@ static __always_inline void clear_pending_set_locked(struct qspinlock *lock)
{
atomic_add(-_Q_PENDING_VAL + _Q_LOCKED_VAL, &lock->val);
}
+#endif /* _Q_PENDING_BITS == 8 */
+
+#if _Q_PENDING_BITS == 8 && !defined(CONFIG_ARCH_USE_QUEUED_SPINLOCKS_XCHG32)
+/*
+ * xchg_tail - Put in the new queue tail code word & retrieve previous one
+ * @lock : Pointer to queued spinlock structure
+ * @tail : The new queue tail code word
+ * Return: The previous queue tail code word
+ *
+ * xchg(lock, tail), which heads an address dependency
+ *
+ * p,*,* -> n,*,* ; prev = xchg(lock, node)
+ */
+static __always_inline u32 xchg_tail(struct qspinlock *lock, u32 tail)
+{
+ /*
+ * We can use relaxed semantics since the caller ensures that the
+ * MCS node is properly initialized before updating the tail.
+ */
+ return (u32)xchg_relaxed(&lock->tail,
+ tail >> _Q_TAIL_OFFSET) << _Q_TAIL_OFFSET;
+}
+
+#else
/**
* xchg_tail - Put in the new queue tail code word & retrieve previous one
@@ -236,7 +240,7 @@ static __always_inline u32 xchg_tail(struct qspinlock *lock, u32 tail)
}
return old;
}
-#endif /* _Q_PENDING_BITS == 8 */
+#endif
/**
* queued_fetch_set_pending_acquire - fetch the whole lock value and set pending
--
2.17.1
^ permalink raw reply related
* [PATCH v5 2/7] riscv: Convert custom spinlock/rwlock to generic qspinlock/qrwlock
From: guoren @ 2021-03-28 6:30 UTC (permalink / raw)
To: guoren
Cc: linux-arch, linux-xtensa, Guo Ren, Arnd Bergmann, Peter Zijlstra,
Anup Patel, Palmer Dabbelt, linux-kernel, linux-csky,
Michael Clark, openrisc, sparclinux, linux-riscv, linuxppc-dev
In-Reply-To: <1616913028-83376-1-git-send-email-guoren@kernel.org>
From: Michael Clark <michaeljclark@mac.com>
Update the RISC-V port to use the generic qspinlock and qrwlock.
This patch requires support for xchg_xtail for full-word which
are added by a previous patch:
Guo added select ARCH_USE_QUEUED_SPINLOCKS_XCHG32 in Kconfig
Guo fixed up compile error which made by below include sequence:
+#include <asm/qrwlock.h>
+#include <asm/qspinlock.h>
Signed-off-by: Michael Clark <michaeljclark@mac.com>
Co-developed-by: Guo Ren <guoren@linux.alibaba.com>
Tested-by: Guo Ren <guoren@linux.alibaba.com>
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Link: https://lore.kernel.org/linux-riscv/20190211043829.30096-3-michaeljclark@mac.com/
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Anup Patel <anup@brainfault.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Palmer Dabbelt <palmerdabbelt@google.com>
---
arch/riscv/Kconfig | 3 +
arch/riscv/include/asm/Kbuild | 3 +
arch/riscv/include/asm/spinlock.h | 126 +-----------------------
arch/riscv/include/asm/spinlock_types.h | 15 +--
4 files changed, 11 insertions(+), 136 deletions(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 87d7b52f278f..67cc65ba1ea1 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -33,6 +33,9 @@ config RISCV
select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
select ARCH_WANT_FRAME_POINTERS
select ARCH_WANT_HUGE_PMD_SHARE if 64BIT
+ select ARCH_USE_QUEUED_RWLOCKS
+ select ARCH_USE_QUEUED_SPINLOCKS
+ select ARCH_USE_QUEUED_SPINLOCKS_XCHG32
select CLONE_BACKWARDS
select CLINT_TIMER if !MMU
select COMMON_CLK
diff --git a/arch/riscv/include/asm/Kbuild b/arch/riscv/include/asm/Kbuild
index 445ccc97305a..750c1056b90f 100644
--- a/arch/riscv/include/asm/Kbuild
+++ b/arch/riscv/include/asm/Kbuild
@@ -3,5 +3,8 @@ generic-y += early_ioremap.h
generic-y += extable.h
generic-y += flat.h
generic-y += kvm_para.h
+generic-y += mcs_spinlock.h
+generic-y += qrwlock.h
+generic-y += qspinlock.h
generic-y += user.h
generic-y += vmlinux.lds.h
diff --git a/arch/riscv/include/asm/spinlock.h b/arch/riscv/include/asm/spinlock.h
index f4f7fa1b7ca8..a557de67a425 100644
--- a/arch/riscv/include/asm/spinlock.h
+++ b/arch/riscv/include/asm/spinlock.h
@@ -7,129 +7,7 @@
#ifndef _ASM_RISCV_SPINLOCK_H
#define _ASM_RISCV_SPINLOCK_H
-#include <linux/kernel.h>
-#include <asm/current.h>
-#include <asm/fence.h>
-
-/*
- * Simple spin lock operations. These provide no fairness guarantees.
- */
-
-/* FIXME: Replace this with a ticket lock, like MIPS. */
-
-#define arch_spin_is_locked(x) (READ_ONCE((x)->lock) != 0)
-
-static inline void arch_spin_unlock(arch_spinlock_t *lock)
-{
- smp_store_release(&lock->lock, 0);
-}
-
-static inline int arch_spin_trylock(arch_spinlock_t *lock)
-{
- int tmp = 1, busy;
-
- __asm__ __volatile__ (
- " amoswap.w %0, %2, %1\n"
- RISCV_ACQUIRE_BARRIER
- : "=r" (busy), "+A" (lock->lock)
- : "r" (tmp)
- : "memory");
-
- return !busy;
-}
-
-static inline void arch_spin_lock(arch_spinlock_t *lock)
-{
- while (1) {
- if (arch_spin_is_locked(lock))
- continue;
-
- if (arch_spin_trylock(lock))
- break;
- }
-}
-
-/***********************************************************/
-
-static inline void arch_read_lock(arch_rwlock_t *lock)
-{
- int tmp;
-
- __asm__ __volatile__(
- "1: lr.w %1, %0\n"
- " bltz %1, 1b\n"
- " addi %1, %1, 1\n"
- " sc.w %1, %1, %0\n"
- " bnez %1, 1b\n"
- RISCV_ACQUIRE_BARRIER
- : "+A" (lock->lock), "=&r" (tmp)
- :: "memory");
-}
-
-static inline void arch_write_lock(arch_rwlock_t *lock)
-{
- int tmp;
-
- __asm__ __volatile__(
- "1: lr.w %1, %0\n"
- " bnez %1, 1b\n"
- " li %1, -1\n"
- " sc.w %1, %1, %0\n"
- " bnez %1, 1b\n"
- RISCV_ACQUIRE_BARRIER
- : "+A" (lock->lock), "=&r" (tmp)
- :: "memory");
-}
-
-static inline int arch_read_trylock(arch_rwlock_t *lock)
-{
- int busy;
-
- __asm__ __volatile__(
- "1: lr.w %1, %0\n"
- " bltz %1, 1f\n"
- " addi %1, %1, 1\n"
- " sc.w %1, %1, %0\n"
- " bnez %1, 1b\n"
- RISCV_ACQUIRE_BARRIER
- "1:\n"
- : "+A" (lock->lock), "=&r" (busy)
- :: "memory");
-
- return !busy;
-}
-
-static inline int arch_write_trylock(arch_rwlock_t *lock)
-{
- int busy;
-
- __asm__ __volatile__(
- "1: lr.w %1, %0\n"
- " bnez %1, 1f\n"
- " li %1, -1\n"
- " sc.w %1, %1, %0\n"
- " bnez %1, 1b\n"
- RISCV_ACQUIRE_BARRIER
- "1:\n"
- : "+A" (lock->lock), "=&r" (busy)
- :: "memory");
-
- return !busy;
-}
-
-static inline void arch_read_unlock(arch_rwlock_t *lock)
-{
- __asm__ __volatile__(
- RISCV_RELEASE_BARRIER
- " amoadd.w x0, %1, %0\n"
- : "+A" (lock->lock)
- : "r" (-1)
- : "memory");
-}
-
-static inline void arch_write_unlock(arch_rwlock_t *lock)
-{
- smp_store_release(&lock->lock, 0);
-}
+#include <asm/qspinlock.h>
+#include <asm/qrwlock.h>
#endif /* _ASM_RISCV_SPINLOCK_H */
diff --git a/arch/riscv/include/asm/spinlock_types.h b/arch/riscv/include/asm/spinlock_types.h
index f398e7638dd6..d033a973f287 100644
--- a/arch/riscv/include/asm/spinlock_types.h
+++ b/arch/riscv/include/asm/spinlock_types.h
@@ -6,20 +6,11 @@
#ifndef _ASM_RISCV_SPINLOCK_TYPES_H
#define _ASM_RISCV_SPINLOCK_TYPES_H
-#ifndef __LINUX_SPINLOCK_TYPES_H
+#if !defined(__LINUX_SPINLOCK_TYPES_H) && !defined(_ASM_RISCV_SPINLOCK_H)
# error "please don't include this file directly"
#endif
-typedef struct {
- volatile unsigned int lock;
-} arch_spinlock_t;
-
-#define __ARCH_SPIN_LOCK_UNLOCKED { 0 }
-
-typedef struct {
- volatile unsigned int lock;
-} arch_rwlock_t;
-
-#define __ARCH_RW_LOCK_UNLOCKED { 0 }
+#include <asm-generic/qspinlock_types.h>
+#include <asm-generic/qrwlock_types.h>
#endif /* _ASM_RISCV_SPINLOCK_TYPES_H */
--
2.17.1
^ permalink raw reply related
* [PATCH v5 3/7] csky: Convert custom spinlock/rwlock to generic qspinlock/qrwlock
From: guoren @ 2021-03-28 6:30 UTC (permalink / raw)
To: guoren
Cc: linux-arch, linux-xtensa, Guo Ren, Arnd Bergmann, Peter Zijlstra,
Will Deacon, linux-kernel, linux-csky, openrisc, sparclinux,
Waiman Long, linux-riscv, linuxppc-dev
In-Reply-To: <1616913028-83376-1-git-send-email-guoren@kernel.org>
From: Guo Ren <guoren@linux.alibaba.com>
Update the C-SKY port to use the generic qspinlock and qrwlock.
C-SKY only support ldex.w/stex.w with word(double word) size &
align access. So it must select XCHG32 to let qspinlock only use
word atomic xchg_tail.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Cc: Waiman Long <longman@redhat.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Will Deacon <will@kernel.org>
Cc: Arnd Bergmann <arnd@arndb.de>
---
arch/csky/Kconfig | 2 +
arch/csky/include/asm/Kbuild | 2 +
arch/csky/include/asm/spinlock.h | 82 +-------------------------
arch/csky/include/asm/spinlock_types.h | 16 +----
4 files changed, 6 insertions(+), 96 deletions(-)
diff --git a/arch/csky/Kconfig b/arch/csky/Kconfig
index 34e91224adc3..5910eb6ddde2 100644
--- a/arch/csky/Kconfig
+++ b/arch/csky/Kconfig
@@ -8,6 +8,8 @@ config CSKY
select ARCH_HAS_SYNC_DMA_FOR_DEVICE
select ARCH_USE_BUILTIN_BSWAP
select ARCH_USE_QUEUED_RWLOCKS
+ select ARCH_USE_QUEUED_SPINLOCKS
+ select ARCH_USE_QUEUED_SPINLOCKS_XCHG32
select ARCH_WANT_FRAME_POINTERS if !CPU_CK610
select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
select COMMON_CLK
diff --git a/arch/csky/include/asm/Kbuild b/arch/csky/include/asm/Kbuild
index cc24bb8e539f..2a2d09963bb9 100644
--- a/arch/csky/include/asm/Kbuild
+++ b/arch/csky/include/asm/Kbuild
@@ -2,6 +2,8 @@
generic-y += asm-offsets.h
generic-y += gpio.h
generic-y += kvm_para.h
+generic-y += mcs_spinlock.h
generic-y += qrwlock.h
+generic-y += qspinlock.h
generic-y += user.h
generic-y += vmlinux.lds.h
diff --git a/arch/csky/include/asm/spinlock.h b/arch/csky/include/asm/spinlock.h
index 69f5aa249c5f..fcff36753c25 100644
--- a/arch/csky/include/asm/spinlock.h
+++ b/arch/csky/include/asm/spinlock.h
@@ -3,87 +3,7 @@
#ifndef __ASM_CSKY_SPINLOCK_H
#define __ASM_CSKY_SPINLOCK_H
-#include <linux/spinlock_types.h>
-#include <asm/barrier.h>
-
-/*
- * Ticket-based spin-locking.
- */
-static inline void arch_spin_lock(arch_spinlock_t *lock)
-{
- arch_spinlock_t lockval;
- u32 ticket_next = 1 << TICKET_NEXT;
- u32 *p = &lock->lock;
- u32 tmp;
-
- asm volatile (
- "1: ldex.w %0, (%2) \n"
- " mov %1, %0 \n"
- " add %0, %3 \n"
- " stex.w %0, (%2) \n"
- " bez %0, 1b \n"
- : "=&r" (tmp), "=&r" (lockval)
- : "r"(p), "r"(ticket_next)
- : "cc");
-
- while (lockval.tickets.next != lockval.tickets.owner)
- lockval.tickets.owner = READ_ONCE(lock->tickets.owner);
-
- smp_mb();
-}
-
-static inline int arch_spin_trylock(arch_spinlock_t *lock)
-{
- u32 tmp, contended, res;
- u32 ticket_next = 1 << TICKET_NEXT;
- u32 *p = &lock->lock;
-
- do {
- asm volatile (
- " ldex.w %0, (%3) \n"
- " movi %2, 1 \n"
- " rotli %1, %0, 16 \n"
- " cmpne %1, %0 \n"
- " bt 1f \n"
- " movi %2, 0 \n"
- " add %0, %0, %4 \n"
- " stex.w %0, (%3) \n"
- "1: \n"
- : "=&r" (res), "=&r" (tmp), "=&r" (contended)
- : "r"(p), "r"(ticket_next)
- : "cc");
- } while (!res);
-
- if (!contended)
- smp_mb();
-
- return !contended;
-}
-
-static inline void arch_spin_unlock(arch_spinlock_t *lock)
-{
- smp_mb();
- WRITE_ONCE(lock->tickets.owner, lock->tickets.owner + 1);
-}
-
-static inline int arch_spin_value_unlocked(arch_spinlock_t lock)
-{
- return lock.tickets.owner == lock.tickets.next;
-}
-
-static inline int arch_spin_is_locked(arch_spinlock_t *lock)
-{
- return !arch_spin_value_unlocked(READ_ONCE(*lock));
-}
-
-static inline int arch_spin_is_contended(arch_spinlock_t *lock)
-{
- struct __raw_tickets tickets = READ_ONCE(lock->tickets);
-
- return (tickets.next - tickets.owner) > 1;
-}
-#define arch_spin_is_contended arch_spin_is_contended
-
+#include <asm/qspinlock.h>
#include <asm/qrwlock.h>
#endif /* __ASM_CSKY_SPINLOCK_H */
diff --git a/arch/csky/include/asm/spinlock_types.h b/arch/csky/include/asm/spinlock_types.h
index 8ff0f6ff3a00..757594760e65 100644
--- a/arch/csky/include/asm/spinlock_types.h
+++ b/arch/csky/include/asm/spinlock_types.h
@@ -7,21 +7,7 @@
# error "please don't include this file directly"
#endif
-#define TICKET_NEXT 16
-
-typedef struct {
- union {
- u32 lock;
- struct __raw_tickets {
- /* little endian */
- u16 owner;
- u16 next;
- } tickets;
- };
-} arch_spinlock_t;
-
-#define __ARCH_SPIN_LOCK_UNLOCKED { { 0 } }
-
+#include <asm-generic/qspinlock_types.h>
#include <asm-generic/qrwlock_types.h>
#endif /* __ASM_CSKY_SPINLOCK_TYPES_H */
--
2.17.1
^ permalink raw reply related
* [PATCH v5 4/7] powerpc/qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32
From: guoren @ 2021-03-28 6:30 UTC (permalink / raw)
To: guoren
Cc: linux-arch, linux-xtensa, Guo Ren, linux-kernel, linux-csky,
openrisc, Paul Mackerras, sparclinux, linux-riscv, linuxppc-dev
In-Reply-To: <1616913028-83376-1-git-send-email-guoren@kernel.org>
From: Guo Ren <guoren@linux.alibaba.com>
We don't have native hw xchg16 instruction, so let qspinlock
generic code to deal with it.
Using the full-word atomic xchg instructions implement xchg16 has
the semantic risk for atomic operations.
This patch cancels the dependency of on qspinlock generic code on
architecture's xchg16.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
---
arch/powerpc/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 386ae12d8523..69ec4ade6521 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -151,6 +151,7 @@ config PPC
select ARCH_USE_CMPXCHG_LOCKREF if PPC64
select ARCH_USE_QUEUED_RWLOCKS if PPC_QUEUED_SPINLOCKS
select ARCH_USE_QUEUED_SPINLOCKS if PPC_QUEUED_SPINLOCKS
+ select ARCH_USE_QUEUED_SPINLOCKS_XCHG32 if PPC_QUEUED_SPINLOCKS
select ARCH_WANT_IPC_PARSE_VERSION
select ARCH_WANT_IRQS_OFF_ACTIVATE_MM
select ARCH_WANT_LD_ORPHAN_WARN
--
2.17.1
^ permalink raw reply related
* [PATCH v5 5/7] openrisc: qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32
From: guoren @ 2021-03-28 6:30 UTC (permalink / raw)
To: guoren
Cc: linux-arch, linux-xtensa, Guo Ren, Arnd Bergmann, linux-kernel,
linux-csky, Stefan Kristiansson, openrisc, Stafford Horne,
sparclinux, linux-riscv, linuxppc-dev, Jonas Bonn
In-Reply-To: <1616913028-83376-1-git-send-email-guoren@kernel.org>
From: Guo Ren <guoren@linux.alibaba.com>
We don't have native hw xchg16 instruction, so let qspinlock
generic code to deal with it.
Using the full-word atomic xchg instructions implement xchg16 has
the semantic risk for atomic operations.
This patch cancels the dependency of on qspinlock generic code on
architecture's xchg16.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Jonas Bonn <jonas@southpole.se>
Cc: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
Cc: Stafford Horne <shorne@gmail.com>
Cc: openrisc@lists.librecores.org
---
arch/openrisc/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
index 591acc5990dc..b299e409429f 100644
--- a/arch/openrisc/Kconfig
+++ b/arch/openrisc/Kconfig
@@ -33,6 +33,7 @@ config OPENRISC
select OR1K_PIC
select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1
select ARCH_USE_QUEUED_SPINLOCKS
+ select ARCH_USE_QUEUED_SPINLOCKS_XCHG32
select ARCH_USE_QUEUED_RWLOCKS
select OMPIC if SMP
select ARCH_WANT_FRAME_POINTERS
--
2.17.1
^ permalink raw reply related
* [PATCH v5 6/7] sparc: qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32
From: guoren @ 2021-03-28 6:30 UTC (permalink / raw)
To: guoren
Cc: linux-arch, linux-xtensa, Guo Ren, Arnd Bergmann, Rob Gardner,
linux-kernel, linux-csky, openrisc, sparclinux, linux-riscv,
linuxppc-dev, David S . Miller
In-Reply-To: <1616913028-83376-1-git-send-email-guoren@kernel.org>
From: Guo Ren <guoren@linux.alibaba.com>
We don't have native hw xchg16 instruction, so let qspinlock
generic code to deal with it.
Using the full-word atomic xchg instructions implement xchg16 has
the semantic risk for atomic operations.
This patch cancels the dependency of on qspinlock generic code on
architecture's xchg16.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: David S. Miller <davem@davemloft.net>
Cc: Rob Gardner <rob.gardner@oracle.com>
---
arch/sparc/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig
index 164a5254c91c..1079fe3f058c 100644
--- a/arch/sparc/Kconfig
+++ b/arch/sparc/Kconfig
@@ -91,6 +91,7 @@ config SPARC64
select HAVE_REGS_AND_STACK_ACCESS_API
select ARCH_USE_QUEUED_RWLOCKS
select ARCH_USE_QUEUED_SPINLOCKS
+ select ARCH_USE_QUEUED_SPINLOCKS_XCHG32
select GENERIC_TIME_VSYSCALL
select ARCH_CLOCKSOURCE_DATA
select ARCH_HAS_PTE_SPECIAL
--
2.17.1
^ permalink raw reply related
* [PATCH v5 7/7] xtensa: qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32
From: guoren @ 2021-03-28 6:30 UTC (permalink / raw)
To: guoren
Cc: linux-arch, linux-xtensa, Guo Ren, Arnd Bergmann, Chris Zankel,
linux-kernel, linux-csky, Max Filippov, openrisc, sparclinux,
linux-riscv, linuxppc-dev
In-Reply-To: <1616913028-83376-1-git-send-email-guoren@kernel.org>
From: Guo Ren <guoren@linux.alibaba.com>
We don't have native hw xchg16 instruction, so let qspinlock
generic code to deal with it.
Using the full-word atomic xchg instructions implement xchg16 has
the semantic risk for atomic operations.
This patch cancels the dependency of on qspinlock generic code on
architecture's xchg16.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Chris Zankel <chris@zankel.net>
Cc: Max Filippov <jcmvbkbc@gmail.com>
---
arch/xtensa/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig
index 9ad6b7b82707..f19d780638f7 100644
--- a/arch/xtensa/Kconfig
+++ b/arch/xtensa/Kconfig
@@ -9,6 +9,7 @@ config XTENSA
select ARCH_HAS_DMA_SET_UNCACHED if MMU
select ARCH_USE_QUEUED_RWLOCKS
select ARCH_USE_QUEUED_SPINLOCKS
+ select ARCH_USE_QUEUED_SPINLOCKS_XCHG32
select ARCH_WANT_FRAME_POINTERS
select ARCH_WANT_IPC_PARSE_VERSION
select BUILDTIME_TABLE_SORT
--
2.17.1
^ permalink raw reply related
* Re: [PATCH] powerpc: Fix HAVE_HARDLOCKUP_DETECTOR_ARCH build configuration
From: Christophe Leroy @ 2021-03-28 11:06 UTC (permalink / raw)
To: Chen Huang, Michael Ellerman, Benjamin Herrenschmidt,
Paul Mackerras
Cc: Don Zickus, linux-kernel, Nicholas Piggin, Hulk Robot,
Andrew Morton, linuxppc-dev
In-Reply-To: <20210327094900.938555-1-chenhuang5@huawei.com>
Le 27/03/2021 à 10:49, Chen Huang a écrit :
> When compiling the powerpc with the SMP disabled, it shows the issue:
>
> arch/powerpc/kernel/watchdog.c: In function ‘watchdog_smp_panic’:
> arch/powerpc/kernel/watchdog.c:177:4: error: implicit declaration of function ‘smp_send_nmi_ipi’; did you mean ‘smp_send_stop’? [-Werror=implicit-function-declaration]
> 177 | smp_send_nmi_ipi(c, wd_lockup_ipi, 1000000);
> | ^~~~~~~~~~~~~~~~
> | smp_send_stop
> cc1: all warnings being treated as errors
> make[2]: *** [scripts/Makefile.build:273: arch/powerpc/kernel/watchdog.o] Error 1
> make[1]: *** [scripts/Makefile.build:534: arch/powerpc/kernel] Error 2
> make: *** [Makefile:1980: arch/powerpc] Error 2
> make: *** Waiting for unfinished jobs....
>
> We found that powerpc used ipi to implement hardlockup watchdog, so the
> HAVE_HARDLOCKUP_DETECTOR_ARCH should depend on the SMP.
>
> Fixes: 2104180a5369 ("powerpc/64s: implement arch-specific hardlockup watchdog")
> Reported-by: Hulk Robot <hulkci@huawei.com>
> Signed-off-by: Chen Huang <chenhuang5@huawei.com>
> ---
> arch/powerpc/Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
> index 764df010baee..2d4f37b117ce 100644
> --- a/arch/powerpc/Kconfig
> +++ b/arch/powerpc/Kconfig
> @@ -225,7 +225,7 @@ config PPC
> select HAVE_LIVEPATCH if HAVE_DYNAMIC_FTRACE_WITH_REGS
> select HAVE_MOD_ARCH_SPECIFIC
> select HAVE_NMI if PERF_EVENTS || (PPC64 && PPC_BOOK3S)
> - select HAVE_HARDLOCKUP_DETECTOR_ARCH if (PPC64 && PPC_BOOK3S)
> + select HAVE_HARDLOCKUP_DETECTOR_ARCH if PPC64 && PPC_BOOK3S && SMP
While modifying this line, you should restore the alphabetic order by moving it up.
You can use PPC_BOOK3S_64 instead of PPC64 && PPC_BOOK3S
> select HAVE_OPTPROBES if PPC64
> select HAVE_PERF_EVENTS
> select HAVE_PERF_EVENTS_NMI if PPC64
>
^ permalink raw reply
* Re: [PATCH v5 4/7] powerpc/qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32
From: Christophe Leroy @ 2021-03-28 11:14 UTC (permalink / raw)
To: guoren
Cc: linux-arch, linux-xtensa, Guo Ren, linux-kernel, linux-csky,
openrisc, Paul Mackerras, sparclinux, linux-riscv, linuxppc-dev
In-Reply-To: <1616913028-83376-5-git-send-email-guoren@kernel.org>
Le 28/03/2021 à 08:30, guoren@kernel.org a écrit :
> From: Guo Ren <guoren@linux.alibaba.com>
>
> We don't have native hw xchg16 instruction, so let qspinlock
> generic code to deal with it.
We have lharx/sthcx pair on some versions of powerpc.
See https://patchwork.ozlabs.org/project/linuxppc-dev/patch/20201107032328.2454582-1-npiggin@gmail.com/
Christophe
>
> Using the full-word atomic xchg instructions implement xchg16 has
> the semantic risk for atomic operations.
>
> This patch cancels the dependency of on qspinlock generic code on
> architecture's xchg16.
>
> Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
> Cc: Michael Ellerman <mpe@ellerman.id.au>
> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> Cc: Paul Mackerras <paulus@samba.org>
> ---
> arch/powerpc/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
> index 386ae12d8523..69ec4ade6521 100644
> --- a/arch/powerpc/Kconfig
> +++ b/arch/powerpc/Kconfig
> @@ -151,6 +151,7 @@ config PPC
> select ARCH_USE_CMPXCHG_LOCKREF if PPC64
> select ARCH_USE_QUEUED_RWLOCKS if PPC_QUEUED_SPINLOCKS
> select ARCH_USE_QUEUED_SPINLOCKS if PPC_QUEUED_SPINLOCKS
> + select ARCH_USE_QUEUED_SPINLOCKS_XCHG32 if PPC_QUEUED_SPINLOCKS
> select ARCH_WANT_IPC_PARSE_VERSION
> select ARCH_WANT_IRQS_OFF_ACTIVATE_MM
> select ARCH_WANT_LD_ORPHAN_WARN
>
^ permalink raw reply
* Re: [PATCH v5 4/7] powerpc/qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32
From: Guo Ren @ 2021-03-28 11:36 UTC (permalink / raw)
To: Christophe Leroy
Cc: linux-arch, linux-xtensa, Guo Ren, Linux Kernel Mailing List,
linux-csky, openrisc, Paul Mackerras, sparclinux, linux-riscv,
linuxppc-dev
In-Reply-To: <e27af5e0-a462-cb75-6311-1b5a6b4ee4f1@csgroup.eu>
On Sun, Mar 28, 2021 at 7:14 PM Christophe Leroy
<christophe.leroy@csgroup.eu> wrote:
>
>
>
> Le 28/03/2021 à 08:30, guoren@kernel.org a écrit :
> > From: Guo Ren <guoren@linux.alibaba.com>
> >
> > We don't have native hw xchg16 instruction, so let qspinlock
> > generic code to deal with it.
>
> We have lharx/sthcx pair on some versions of powerpc.
>
> See https://patchwork.ozlabs.org/project/linuxppc-dev/patch/20201107032328.2454582-1-npiggin@gmail.com/
Got it, thx for the information.
>
> Christophe
>
> >
> > Using the full-word atomic xchg instructions implement xchg16 has
> > the semantic risk for atomic operations.
> >
> > This patch cancels the dependency of on qspinlock generic code on
> > architecture's xchg16.
> >
> > Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
> > Cc: Michael Ellerman <mpe@ellerman.id.au>
> > Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> > Cc: Paul Mackerras <paulus@samba.org>
> > ---
> > arch/powerpc/Kconfig | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
> > index 386ae12d8523..69ec4ade6521 100644
> > --- a/arch/powerpc/Kconfig
> > +++ b/arch/powerpc/Kconfig
> > @@ -151,6 +151,7 @@ config PPC
> > select ARCH_USE_CMPXCHG_LOCKREF if PPC64
> > select ARCH_USE_QUEUED_RWLOCKS if PPC_QUEUED_SPINLOCKS
> > select ARCH_USE_QUEUED_SPINLOCKS if PPC_QUEUED_SPINLOCKS
> > + select ARCH_USE_QUEUED_SPINLOCKS_XCHG32 if PPC_QUEUED_SPINLOCKS
> > select ARCH_WANT_IPC_PARSE_VERSION
> > select ARCH_WANT_IRQS_OFF_ACTIVATE_MM
> > select ARCH_WANT_LD_ORPHAN_WARN
> >
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
^ permalink raw reply
* [PATCH] powerpc/signal32: Fix Oops on sigreturn with unmapped VDSO
From: Christophe Leroy @ 2021-03-28 14:02 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman
Cc: linuxppc-dev, linux-kernel
PPC32 encounters a KUAP fault when trying to handle a signal with
VDSO unmapped.
Kernel attempted to read user page (7fc07ec0) - exploit attempt? (uid: 0)
BUG: Unable to handle kernel data access on read at 0x7fc07ec0
Faulting instruction address: 0xc00111d4
Oops: Kernel access of bad area, sig: 11 [#1]
BE PAGE_SIZE=16K PREEMPT CMPC885
CPU: 0 PID: 353 Comm: sigreturn_vdso Not tainted 5.12.0-rc4-s3k-dev-01553-gb30c310ea220 #4814
NIP: c00111d4 LR: c0005a28 CTR: 00000000
REGS: cadb3dd0 TRAP: 0300 Not tainted (5.12.0-rc4-s3k-dev-01553-gb30c310ea220)
MSR: 00009032 <EE,ME,IR,DR,RI> CR: 48000884 XER: 20000000
DAR: 7fc07ec0 DSISR: 88000000
GPR00: c0007788 cadb3e90 c28d4a40 7fc07ec0 7fc07ed0 000004e0 7fc07ce0 00000000
GPR08: 00000001 00000001 7fc07ec0 00000000 28000282 1001b828 100a0920 00000000
GPR16: 100cac0c 100b0000 105c43a4 105c5685 100d0000 100d0000 100d0000 100b2e9e
GPR24: ffffffff 105c43c8 00000000 7fc07ec8 cadb3f40 cadb3ec8 c28d4a40 00000000
NIP [c00111d4] flush_icache_range+0x90/0xb4
LR [c0005a28] handle_signal32+0x1bc/0x1c4
Call Trace:
[cadb3e90] [100d0000] 0x100d0000 (unreliable)
[cadb3ec0] [c0007788] do_notify_resume+0x260/0x314
[cadb3f20] [c000c764] syscall_exit_prepare+0x120/0x184
[cadb3f30] [c00100b4] ret_from_syscall+0xc/0x28
--- interrupt: c00 at 0xfe807f8
NIP: 0fe807f8 LR: 10001060 CTR: c0139378
REGS: cadb3f40 TRAP: 0c00 Not tainted (5.12.0-rc4-s3k-dev-01553-gb30c310ea220)
MSR: 0000d032 <EE,PR,ME,IR,DR,RI> CR: 28000482 XER: 20000000
GPR00: 00000025 7fc081c0 77bb1690 00000000 0000000a 28000482 00000001 0ff03a38
GPR08: 0000d032 00006de5 c28d4a40 00000009 88000482 1001b828 100a0920 00000000
GPR16: 100cac0c 100b0000 105c43a4 105c5685 100d0000 100d0000 100d0000 100b2e9e
GPR24: ffffffff 105c43c8 00000000 77ba7628 10002398 10010000 10002124 00024000
NIP [0fe807f8] 0xfe807f8
LR [10001060] 0x10001060
--- interrupt: c00
Instruction dump:
38630010 7c001fac 38630010 4200fff0 7c0004ac 4c00012c 4e800020 7c001fac
2c0a0000 38630010 4082ffcc 4bffffe4 <7c00186c> 2c070000 39430010 4082ff8c
---[ end trace 3973fb72b049cb06 ]---
This is because flush_icache_range() is called on user addresses.
The same problem was detected some time ago on PPC64. It was fixed by
enabling KUAP in commit 59bee45b9712 ("powerpc/mm: Fix missing KUAP
disable in flush_coherent_icache()").
PPC32 doesn't use flush_coherent_icache() and fallbacks on
clean_dcache_range() and invalidate_icache_range().
We could fix it similarly by enabling user access in those functions,
but this is overkill for just flushing two instructions.
The two instructions are 8 bytes aligned, so a single dcbst/icbi is
enough to flush them. Do like __patch_instruction() and inline
a dcbst followed by an icbi just after the write of the instructions,
while user access is still allowed. The isync is not required because
rfi will be used to return to user.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
---
arch/powerpc/kernel/signal_32.c | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/kernel/signal_32.c b/arch/powerpc/kernel/signal_32.c
index 75ee918a120a..5b2ba2731957 100644
--- a/arch/powerpc/kernel/signal_32.c
+++ b/arch/powerpc/kernel/signal_32.c
@@ -809,6 +809,7 @@ int handle_rt_signal32(struct ksignal *ksig, sigset_t *oldset,
unsafe_put_user(PPC_INST_ADDI + __NR_rt_sigreturn, &mctx->mc_pad[0],
failed);
unsafe_put_user(PPC_INST_SC, &mctx->mc_pad[1], failed);
+ asm("dcbst %y0; sync; icbi %y0; sync" :: "Z" (mctx->mc_pad[0]));
}
unsafe_put_sigset_t(&frame->uc.uc_sigmask, oldset, failed);
@@ -817,9 +818,6 @@ int handle_rt_signal32(struct ksignal *ksig, sigset_t *oldset,
if (copy_siginfo_to_user(&frame->info, &ksig->info))
goto badframe;
- if (tramp == (unsigned long)mctx->mc_pad)
- flush_icache_range(tramp, tramp + 2 * sizeof(unsigned long));
-
regs->link = tramp;
#ifdef CONFIG_PPC_FPU_REGS
@@ -908,12 +906,10 @@ int handle_signal32(struct ksignal *ksig, sigset_t *oldset,
/* Set up the sigreturn trampoline: li r0,sigret; sc */
unsafe_put_user(PPC_INST_ADDI + __NR_sigreturn, &mctx->mc_pad[0], failed);
unsafe_put_user(PPC_INST_SC, &mctx->mc_pad[1], failed);
+ asm("dcbst %y0; sync; icbi %y0; sync" :: "Z" (mctx->mc_pad[0]));
}
user_write_access_end();
- if (tramp == (unsigned long)mctx->mc_pad)
- flush_icache_range(tramp, tramp + 2 * sizeof(unsigned long));
-
regs->link = tramp;
#ifdef CONFIG_PPC_FPU_REGS
--
2.25.0
^ permalink raw reply related
* Re: [PATCH] powerpc/process: Enhance readability for trap types.
From: Christophe Leroy @ 2021-03-28 15:21 UTC (permalink / raw)
To: Xiongwei Song, mpe, benh, paulus, npiggin, ravi.bangoria, mikey,
aneesh.kumar, haren
Cc: Xiongwei Song, linuxppc-dev, linux-kernel
In-Reply-To: <20210328143545.24324-1-sxwjean@me.com>
Le 28/03/2021 à 16:35, Xiongwei Song a écrit :
> From: Xiongwei Song <sxwjean@gmail.com>
>
> Define macros to enhance the code readability on ppc trap types.
Good idea
>
> Signed-off-by: Xiongwei Song <sxwjean@gmail.com>
> ---
> arch/powerpc/kernel/process.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
> index 3231c2df9e26..3bbd3cf353a7 100644
> --- a/arch/powerpc/kernel/process.c
> +++ b/arch/powerpc/kernel/process.c
> @@ -1451,6 +1451,10 @@ static void print_msr_bits(unsigned long val)
> #define LAST_VOLATILE 12
> #endif
>
> +#define TRAP_MC 0x200 /* Machine Check */
I think usually we use MCE, so TRAP_MCE would be better
> +#define TRAP_DSI 0x300 /* DSI exception */
> +#define TRAP_AM 0x600 /* Alignment exception */
Don't know what AM means. TRAP_ALIGN would be more explicit.
> +
The defines should go in a header file, for instance asm/ptrace.h in order to be re-used in other files.
You should do more. You can find other places to improve with:
git grep "trap ==" arch/powerpc/
git grep "TRAP(regs) ==" arch/powerpc/
> static void __show_regs(struct pt_regs *regs)
> {
> int i, trap;
> @@ -1465,7 +1469,7 @@ static void __show_regs(struct pt_regs *regs)
> trap = TRAP(regs);
> if (!trap_is_syscall(regs) && cpu_has_feature(CPU_FTR_CFAR))
> pr_cont("CFAR: "REG" ", regs->orig_gpr3);
> - if (trap == 0x200 || trap == 0x300 || trap == 0x600) {
> + if (trap == TRAP_MC || trap == TRAP_DSI || trap == TRAP_AM) {
> if (IS_ENABLED(CONFIG_4xx) || IS_ENABLED(CONFIG_BOOKE))
> pr_cont("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr);
> else
>
^ permalink raw reply
* [PATCH] powerpc/process: Enhance readability for trap types.
From: Xiongwei Song @ 2021-03-28 14:35 UTC (permalink / raw)
To: mpe, benh, paulus, npiggin, christophe.leroy, ravi.bangoria,
mikey, aneesh.kumar, haren
Cc: Xiongwei Song, linuxppc-dev, linux-kernel
From: Xiongwei Song <sxwjean@gmail.com>
Define macros to enhance the code readability on ppc trap types.
Signed-off-by: Xiongwei Song <sxwjean@gmail.com>
---
arch/powerpc/kernel/process.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index 3231c2df9e26..3bbd3cf353a7 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -1451,6 +1451,10 @@ static void print_msr_bits(unsigned long val)
#define LAST_VOLATILE 12
#endif
+#define TRAP_MC 0x200 /* Machine Check */
+#define TRAP_DSI 0x300 /* DSI exception */
+#define TRAP_AM 0x600 /* Alignment exception */
+
static void __show_regs(struct pt_regs *regs)
{
int i, trap;
@@ -1465,7 +1469,7 @@ static void __show_regs(struct pt_regs *regs)
trap = TRAP(regs);
if (!trap_is_syscall(regs) && cpu_has_feature(CPU_FTR_CFAR))
pr_cont("CFAR: "REG" ", regs->orig_gpr3);
- if (trap == 0x200 || trap == 0x300 || trap == 0x600) {
+ if (trap == TRAP_MC || trap == TRAP_DSI || trap == TRAP_AM) {
if (IS_ENABLED(CONFIG_4xx) || IS_ENABLED(CONFIG_BOOKE))
pr_cont("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr);
else
--
2.17.1
^ permalink raw reply related
* Re: [PATCH] powerpc/process: Enhance readability for trap types.
From: Xiongwei Song @ 2021-03-28 23:11 UTC (permalink / raw)
To: Christophe Leroy
Cc: ravi.bangoria, mikey, Xiongwei Song, haren, linux-kernel, npiggin,
paulus, aneesh.kumar, linuxppc-dev
In-Reply-To: <8de71b45-efea-b493-ee90-b89062e8e30f@csgroup.eu>
> On Mar 28, 2021, at 11:21 PM, Christophe Leroy <christophe.leroy@csgroup.eu> wrote:
>
>
>
> Le 28/03/2021 à 16:35, Xiongwei Song a écrit :
>> From: Xiongwei Song <sxwjean@gmail.com>
>> Define macros to enhance the code readability on ppc trap types.
>
> Good idea
>
>> Signed-off-by: Xiongwei Song <sxwjean@gmail.com>
>> ---
>> arch/powerpc/kernel/process.c | 6 +++++-
>> 1 file changed, 5 insertions(+), 1 deletion(-)
>> diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
>> index 3231c2df9e26..3bbd3cf353a7 100644
>> --- a/arch/powerpc/kernel/process.c
>> +++ b/arch/powerpc/kernel/process.c
>> @@ -1451,6 +1451,10 @@ static void print_msr_bits(unsigned long val)
>> #define LAST_VOLATILE 12
>> #endif
>> +#define TRAP_MC 0x200 /* Machine Check */
>
> I think usually we use MCE, so TRAP_MCE would be better
Ok.
>
>> +#define TRAP_DSI 0x300 /* DSI exception */
>> +#define TRAP_AM 0x600 /* Alignment exception */
>
> Don't know what AM means. TRAP_ALIGN would be more explicit.
No Problem.
>
>> +
>
> The defines should go in a header file, for instance asm/ptrace.h in order to be re-used in other files.
Agree.
>
> You should do more. You can find other places to improve with:
>
> git grep "trap ==" arch/powerpc/
> git grep "TRAP(regs) ==" arch/powerpc/
Just ran “git grep”, looks like the work is much bigger than what I imagined.
>
>> static void __show_regs(struct pt_regs *regs)
>> {
>> int i, trap;
>> @@ -1465,7 +1469,7 @@ static void __show_regs(struct pt_regs *regs)
>> trap = TRAP(regs);
>> if (!trap_is_syscall(regs) && cpu_has_feature(CPU_FTR_CFAR))
>> pr_cont("CFAR: "REG" ", regs->orig_gpr3);
>> - if (trap == 0x200 || trap == 0x300 || trap == 0x600) {
>> + if (trap == TRAP_MC || trap == TRAP_DSI || trap == TRAP_AM) {
>> if (IS_ENABLED(CONFIG_4xx) || IS_ENABLED(CONFIG_BOOKE))
>> pr_cont("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr);
>> else
Thanks for the response. I will send v2.
Regards,
Xiongwei
^ permalink raw reply
* [PATCH 00/30] DMA: Mundane typo fixes
From: Bhaskar Chowdhury @ 2021-03-28 23:52 UTC (permalink / raw)
To: dmaengine, dri-devel, hch, iommu, linuxppc-dev, dave.jiang,
dan.j.williams
Cc: rdunlap, Bhaskar Chowdhury, linux-kernel
This patch series fixes some trivial and rudimentary spellings in the COMMENT
sections.
Bhaskar Chowdhury (30):
acpi-dma.c: Fix couple of typos
altera-msgdma.c: Couple of typos fixed
amba-pl08x.c: Fixed couple of typos
bcm-sba-raid.c: Few typos fixed
bcm2835-dma.c: Fix a typo
idma64.c: Fix couple of typos
iop-adma.c: Few typos fixed
mv_xor.c: Fix a typo
mv_xor.h: Fixed a typo
mv_xor_v2.c: Fix a typo
nbpfaxi.c: Fixed a typo
of-dma.c: Fixed a typo
s3c24xx-dma.c: Fix a typo
Revert "s3c24xx-dma.c: Fix a typo"
s3c24xx-dma.c: Few typos fixed
st_fdma.h: Fix couple of typos
ste_dma40_ll.h: Fix a typo
tegra20-apb-dma.c: Fixed a typo
xgene-dma.c: Few spello fixes
at_hdmac.c: Quite a few spello fixes
owl-dma.c: Fix a typo
at_hdmac_regs.h: Couple of typo fixes
dma-jz4780.c: Fix a typo
Kconfig: Change Synopsys to Synopsis
ste_dma40.c: Few spello fixes
dw-axi-dmac-platform.c: Few typos fixed
dpaa2-qdma.c: Fix a typo
usb-dmac.c: Fix a typo
edma.c: Fix a typo
xilinx_dma.c: Fix a typo
drivers/dma/Kconfig | 8 ++++----
drivers/dma/acpi-dma.c | 4 ++--
drivers/dma/altera-msgdma.c | 4 ++--
drivers/dma/amba-pl08x.c | 4 ++--
drivers/dma/at_hdmac.c | 14 +++++++-------
drivers/dma/at_hdmac_regs.h | 4 ++--
drivers/dma/bcm-sba-raid.c | 8 ++++----
drivers/dma/bcm2835-dma.c | 2 +-
drivers/dma/dma-jz4780.c | 2 +-
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 8 ++++----
drivers/dma/idma64.c | 4 ++--
drivers/dma/iop-adma.c | 6 +++---
drivers/dma/mv_xor.c | 2 +-
drivers/dma/mv_xor.h | 2 +-
drivers/dma/mv_xor_v2.c | 2 +-
drivers/dma/nbpfaxi.c | 2 +-
drivers/dma/of-dma.c | 2 +-
drivers/dma/owl-dma.c | 2 +-
drivers/dma/s3c24xx-dma.c | 6 +++---
drivers/dma/sh/shdmac.c | 2 +-
drivers/dma/sh/usb-dmac.c | 2 +-
drivers/dma/st_fdma.h | 4 ++--
drivers/dma/ste_dma40.c | 10 +++++-----
drivers/dma/ste_dma40_ll.h | 2 +-
drivers/dma/tegra20-apb-dma.c | 2 +-
drivers/dma/ti/edma.c | 2 +-
drivers/dma/xgene-dma.c | 6 +++---
drivers/dma/xilinx/xilinx_dma.c | 2 +-
28 files changed, 59 insertions(+), 59 deletions(-)
--
2.26.3
^ permalink raw reply
* [PATCH 01/30] acpi-dma.c: Fix couple of typos
From: Bhaskar Chowdhury @ 2021-03-28 23:52 UTC (permalink / raw)
To: dmaengine, dri-devel, hch, iommu, linuxppc-dev, dave.jiang,
dan.j.williams
Cc: rdunlap, Bhaskar Chowdhury, linux-kernel
In-Reply-To: <cover.1616971780.git.unixbhaskar@gmail.com>
s/exctract/extract/
s/avaiable/available/
Signed-off-by: Bhaskar Chowdhury <unixbhaskar@gmail.com>
---
drivers/dma/acpi-dma.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/dma/acpi-dma.c b/drivers/dma/acpi-dma.c
index 235f1396f968..4b1d5183bf64 100644
--- a/drivers/dma/acpi-dma.c
+++ b/drivers/dma/acpi-dma.c
@@ -100,7 +100,7 @@ static int acpi_dma_parse_resource_group(const struct acpi_csrt_group *grp,
}
/**
- * acpi_dma_parse_csrt - parse CSRT to exctract additional DMA resources
+ * acpi_dma_parse_csrt - parse CSRT to extract additional DMA resources
* @adev: ACPI device to match with
* @adma: struct acpi_dma of the given DMA controller
*
@@ -293,7 +293,7 @@ EXPORT_SYMBOL_GPL(devm_acpi_dma_controller_free);
* found.
*
* Return:
- * 0, if no information is avaiable, -1 on mismatch, and 1 otherwise.
+ * 0, if no information is available, -1 on mismatch, and 1 otherwise.
*/
static int acpi_dma_update_dma_spec(struct acpi_dma *adma,
struct acpi_dma_spec *dma_spec)
--
2.26.3
^ permalink raw reply related
* [PATCH 02/30] altera-msgdma.c: Couple of typos fixed
From: Bhaskar Chowdhury @ 2021-03-28 23:52 UTC (permalink / raw)
To: dmaengine, dri-devel, hch, iommu, linuxppc-dev, dave.jiang,
dan.j.williams
Cc: rdunlap, Bhaskar Chowdhury, linux-kernel
In-Reply-To: <cover.1616971780.git.unixbhaskar@gmail.com>
s/assosiated/associated/
s/oder/order/
Signed-off-by: Bhaskar Chowdhury <unixbhaskar@gmail.com>
---
drivers/dma/altera-msgdma.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/dma/altera-msgdma.c b/drivers/dma/altera-msgdma.c
index 9a841ce5f0c5..c3483bf2aaa7 100644
--- a/drivers/dma/altera-msgdma.c
+++ b/drivers/dma/altera-msgdma.c
@@ -152,7 +152,7 @@ struct msgdma_extended_desc {
/**
* struct msgdma_sw_desc - implements a sw descriptor
* @async_tx: support for the async_tx api
- * @hw_desc: assosiated HW descriptor
+ * @hw_desc: associated HW descriptor
* @node: node to move from the free list to the tx list
* @tx_list: transmit list node
*/
@@ -510,7 +510,7 @@ static void msgdma_copy_one(struct msgdma_device *mdev,
* of the DMA controller. The descriptor will get flushed to the
* FIFO, once the last word (control word) is written. Since we
* are not 100% sure that memcpy() writes all word in the "correct"
- * oder (address from low to high) on all architectures, we make
+ * order (address from low to high) on all architectures, we make
* sure this control word is written last by single coding it and
* adding some write-barriers here.
*/
--
2.26.3
^ permalink raw reply related
* [PATCH 03/30] amba-pl08x.c: Fixed couple of typos
From: Bhaskar Chowdhury @ 2021-03-28 23:52 UTC (permalink / raw)
To: dmaengine, dri-devel, hch, iommu, linuxppc-dev, dave.jiang,
dan.j.williams
Cc: rdunlap, Bhaskar Chowdhury, linux-kernel
In-Reply-To: <cover.1616971780.git.unixbhaskar@gmail.com>
s/busses/buses/
s/accound/account/
Signed-off-by: Bhaskar Chowdhury <unixbhaskar@gmail.com>
---
drivers/dma/amba-pl08x.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index a24882ba3764..d15182634789 100644
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -121,7 +121,7 @@ struct vendor_data {
/**
* struct pl08x_bus_data - information of source or destination
- * busses for a transfer
+ * buses for a transfer
* @addr: current address
* @maxwidth: the maximum width of a transfer on this bus
* @buswidth: the width of this bus in bytes: 1, 2 or 4
@@ -1010,7 +1010,7 @@ static inline u32 pl08x_lli_control_bits(struct pl08x_driver_data *pl08x,
/*
* Remove all src, dst and transfer size bits, then set the
* width and size according to the parameters. The bit offsets
- * are different in the FTDMAC020 so we need to accound for this.
+ * are different in the FTDMAC020 so we need to account for this.
*/
if (pl08x->vd->ftdmac020) {
retbits &= ~FTDMAC020_LLI_DST_WIDTH_MSK;
--
2.26.3
^ permalink raw reply related
* [PATCH 04/30] bcm-sba-raid.c: Few typos fixed
From: Bhaskar Chowdhury @ 2021-03-28 23:53 UTC (permalink / raw)
To: dmaengine, dri-devel, hch, iommu, linuxppc-dev, dave.jiang,
dan.j.williams
Cc: rdunlap, Bhaskar Chowdhury, linux-kernel
In-Reply-To: <cover.1616971780.git.unixbhaskar@gmail.com>
s/Maibox/Mailbox/
s/alloced/allocated/
s/atleast/"at least"/
s/parallely/parallel/
Signed-off-by: Bhaskar Chowdhury <unixbhaskar@gmail.com>
---
drivers/dma/bcm-sba-raid.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/dma/bcm-sba-raid.c b/drivers/dma/bcm-sba-raid.c
index 64239da02e74..fba1585eb7ad 100644
--- a/drivers/dma/bcm-sba-raid.c
+++ b/drivers/dma/bcm-sba-raid.c
@@ -25,7 +25,7 @@
* number of hardware rings over one or more SBA hardware devices. By
* design, the internal buffer size of SBA hardware device is limited
* but all offload operations supported by SBA can be broken down into
- * multiple small size requests and executed parallely on multiple SBA
+ * multiple small size requests and executed parallel on multiple SBA
* hardware devices for achieving high through-put.
*
* The Broadcom SBA RAID driver does not require any register programming
@@ -143,7 +143,7 @@ struct sba_device {
u32 max_xor_srcs;
u32 max_resp_pool_size;
u32 max_cmds_pool_size;
- /* Maibox client and Mailbox channels */
+ /* Mailbox client and Mailbox channels */
struct mbox_client client;
struct mbox_chan *mchan;
struct device *mbox_dev;
@@ -328,7 +328,7 @@ static void sba_cleanup_nonpending_requests(struct sba_device *sba)
spin_lock_irqsave(&sba->reqs_lock, flags);
- /* Freeup all alloced request */
+ /* Freeup all allocated request */
list_for_each_entry_safe(req, req1, &sba->reqs_alloc_list, node)
_sba_free_request(sba, req);
@@ -1633,7 +1633,7 @@ static int sba_probe(struct platform_device *pdev)
sba->dev = &pdev->dev;
platform_set_drvdata(pdev, sba);
- /* Number of mailbox channels should be atleast 1 */
+ /* Number of mailbox channels should be at least 1 */
ret = of_count_phandle_with_args(pdev->dev.of_node,
"mboxes", "#mbox-cells");
if (ret <= 0)
--
2.26.3
^ permalink raw reply related
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