* [PATCH 15/16] crypto/nx: Get NX capabilities for GZIP coprocessor type
From: Haren Myneni @ 2021-04-11 0:44 UTC (permalink / raw)
To: linuxppc-dev, linux-crypto, mpe, herbert, npiggin; +Cc: haren
In-Reply-To: <b4631127bd025d9585246606c350ec88dbe1e99a.camel@linux.ibm.com>
phyp provides NX capabilities which gives recommended minimum
compression / decompression length and maximum request buffer size
in bytes.
Changes to get NX overall capabilities which points to the specific
features phyp supports. Then retrieve NXGZIP specific capabilities.
Signed-off-by: Haren Myneni <haren@linux.ibm.com>
---
drivers/crypto/nx/nx-common-pseries.c | 83 +++++++++++++++++++++++++++
1 file changed, 83 insertions(+)
diff --git a/drivers/crypto/nx/nx-common-pseries.c b/drivers/crypto/nx/nx-common-pseries.c
index 9a40fca8a9e6..49224870d05e 100644
--- a/drivers/crypto/nx/nx-common-pseries.c
+++ b/drivers/crypto/nx/nx-common-pseries.c
@@ -9,6 +9,7 @@
*/
#include <asm/vio.h>
+#include <asm/hvcall.h>
#include <asm/vas.h>
#include "nx-842.h"
@@ -20,6 +21,24 @@ MODULE_DESCRIPTION("842 H/W Compression driver for IBM Power processors");
MODULE_ALIAS_CRYPTO("842");
MODULE_ALIAS_CRYPTO("842-nx");
+struct nx_ct_capabs_be {
+ __be64 descriptor;
+ __be64 req_max_processed_len; /* Max bytes in one GZIP request */
+ __be64 min_compress_len; /* Min compression size in bytes */
+ __be64 min_decompress_len; /* Min decompression size in bytes */
+} __packed __aligned(0x1000);
+
+struct nx_ct_capabs {
+ char name[VAS_DESCR_LEN + 1];
+ u64 descriptor;
+ u64 req_max_processed_len; /* Max bytes in one GZIP request */
+ u64 min_compress_len; /* Min compression in bytes */
+ u64 min_decompress_len; /* Min decompression in bytes */
+};
+
+u64 capab_feat = 0;
+struct nx_ct_capabs nx_ct_capab;
+
static struct nx842_constraints nx842_pseries_constraints = {
.alignment = DDE_BUFFER_ALIGN,
.multiple = DDE_BUFFER_LAST_MULT,
@@ -1066,6 +1085,66 @@ static void nx842_remove(struct vio_dev *viodev)
kfree(old_devdata);
}
+/*
+ * Get NX capabilities from pHyp.
+ * Only NXGZIP capabilities are available right now and these values
+ * are available through sysfs.
+ */
+static void __init nxct_get_capabilities(void)
+{
+ struct vas_all_capabs_be *capabs_be;
+ struct nx_ct_capabs_be *nxc_be;
+ int rc;
+
+ capabs_be = kmalloc(sizeof(*capabs_be), GFP_KERNEL);
+ if (!capabs_be)
+ return;
+ /*
+ * Get NX overall capabilities with feature type=0
+ */
+ rc = plpar_vas_query_capabilities(H_QUERY_NX_CAPABILITIES, 0,
+ (u64)virt_to_phys(capabs_be));
+ if (rc)
+ goto out;
+
+ capab_feat = be64_to_cpu(capabs_be->feat_type);
+ /*
+ * NX-GZIP feature available
+ */
+ if (capab_feat & VAS_NX_GZIP_FEAT_BIT) {
+ nxc_be = kmalloc(sizeof(*nxc_be), GFP_KERNEL);
+ if (!nxc_be)
+ goto out;
+ /*
+ * Get capabilities for NX-GZIP feature
+ */
+ rc = plpar_vas_query_capabilities(H_QUERY_NX_CAPABILITIES,
+ VAS_NX_GZIP_FEAT,
+ (u64)virt_to_phys(nxc_be));
+ } else {
+ pr_err("NX-GZIP feature is not available\n");
+ rc = -EINVAL;
+ }
+
+ if (!rc) {
+ snprintf(nx_ct_capab.name, VAS_DESCR_LEN + 1, "%.8s",
+ (char *)&nxc_be->descriptor);
+ nx_ct_capab.descriptor = be64_to_cpu(nxc_be->descriptor);
+ nx_ct_capab.req_max_processed_len =
+ be64_to_cpu(nxc_be->req_max_processed_len);
+ nx_ct_capab.min_compress_len =
+ be64_to_cpu(nxc_be->min_compress_len);
+ nx_ct_capab.min_decompress_len =
+ be64_to_cpu(nxc_be->min_decompress_len);
+ } else {
+ capab_feat = 0;
+ }
+
+ kfree(nxc_be);
+out:
+ kfree(capabs_be);
+}
+
static const struct vio_device_id nx842_vio_driver_ids[] = {
{"ibm,compression-v1", "ibm,compression"},
{"", ""},
@@ -1093,6 +1172,10 @@ static int __init nx842_pseries_init(void)
return -ENOMEM;
RCU_INIT_POINTER(devdata, new_devdata);
+ /*
+ * Get NX capabilities from pHyp which is used for NX-GZIP.
+ */
+ nxct_get_capabilities();
ret = vio_register_driver(&nx842_vio_driver);
if (ret) {
--
2.18.2
^ permalink raw reply related
* [PATCH 16/16] crypto/nx: sysfs interface to export NX capabilities
From: Haren Myneni @ 2021-04-11 0:45 UTC (permalink / raw)
To: linuxppc-dev, linux-crypto, mpe, herbert, npiggin; +Cc: haren
In-Reply-To: <b4631127bd025d9585246606c350ec88dbe1e99a.camel@linux.ibm.com>
Changes to export the following NXGZIP capabilities through sysfs:
/sys/devices/vio/ibm,compression-v1/NxGzCaps:
min_compress_len /*Recommended minimum compress length in bytes*/
min_decompress_len /*Recommended minimum decompress length in bytes*/
req_max_processed_len /* Maximum number of bytes processed in one
request */
Signed-off-by: Haren Myneni <haren@linux.ibm.com>
---
drivers/crypto/nx/nx-common-pseries.c | 43 +++++++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/drivers/crypto/nx/nx-common-pseries.c b/drivers/crypto/nx/nx-common-pseries.c
index 49224870d05e..cc258d2c6475 100644
--- a/drivers/crypto/nx/nx-common-pseries.c
+++ b/drivers/crypto/nx/nx-common-pseries.c
@@ -962,6 +962,36 @@ static struct attribute_group nx842_attribute_group = {
.attrs = nx842_sysfs_entries,
};
+#define nxct_capab_read(_name) \
+static ssize_t nxct_##_name##_show(struct device *dev, \
+ struct device_attribute *attr, char *buf) \
+{ \
+ return sprintf(buf, "%lld\n", nx_ct_capab._name); \
+}
+
+#define NXCT_ATTR_RO(_name) \
+ nxct_capab_read(_name); \
+ static struct device_attribute dev_attr_##_name = __ATTR(_name, \
+ 0444, \
+ nxct_##_name##_show, \
+ NULL);
+
+NXCT_ATTR_RO(req_max_processed_len);
+NXCT_ATTR_RO(min_compress_len);
+NXCT_ATTR_RO(min_decompress_len);
+
+static struct attribute *nxct_capab_sysfs_entries[] = {
+ &dev_attr_req_max_processed_len.attr,
+ &dev_attr_min_compress_len.attr,
+ &dev_attr_min_decompress_len.attr,
+ NULL,
+};
+
+static struct attribute_group nxct_capab_attr_group = {
+ .name = nx_ct_capab.name,
+ .attrs = nxct_capab_sysfs_entries,
+};
+
static struct nx842_driver nx842_pseries_driver = {
.name = KBUILD_MODNAME,
.owner = THIS_MODULE,
@@ -1051,6 +1081,16 @@ static int nx842_probe(struct vio_dev *viodev,
goto error;
}
+ if (capab_feat) {
+ if (sysfs_create_group(&viodev->dev.kobj,
+ &nxct_capab_attr_group)) {
+ dev_err(&viodev->dev,
+ "Could not create sysfs NX capability entries\n");
+ ret = -1;
+ goto error;
+ }
+ }
+
return 0;
error_unlock:
@@ -1070,6 +1110,9 @@ static void nx842_remove(struct vio_dev *viodev)
pr_info("Removing IBM Power 842 compression device\n");
sysfs_remove_group(&viodev->dev.kobj, &nx842_attribute_group);
+ if (capab_feat)
+ sysfs_remove_group(&viodev->dev.kobj, &nxct_capab_attr_group);
+
crypto_unregister_alg(&nx842_pseries_alg);
spin_lock_irqsave(&devdata_mutex, flags);
--
2.18.2
^ permalink raw reply related
* [powerpc:merge] BUILD SUCCESS d02429becbe77bc4d27a7357afaf28f9294945bb
From: kernel test robot @ 2021-04-11 3:36 UTC (permalink / raw)
To: Michael Ellerman; +Cc: linuxppc-dev
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git merge
branch HEAD: d02429becbe77bc4d27a7357afaf28f9294945bb Automatic merge of 'master' into merge (2021-04-11 00:30)
elapsed time: 720m
configs tested: 117
configs skipped: 2
The following configs have been built successfully.
More configs may be tested in the coming days.
gcc tested configs:
arm defconfig
arm64 allyesconfig
arm allyesconfig
arm allmodconfig
arm64 defconfig
x86_64 allyesconfig
riscv allmodconfig
i386 allyesconfig
sh sh7724_generic_defconfig
xtensa xip_kc705_defconfig
powerpc ppc64e_defconfig
arm hisi_defconfig
xtensa iss_defconfig
sh se7722_defconfig
m68k m5307c3_defconfig
powerpc ppc64_defconfig
xtensa generic_kc705_defconfig
mips db1xxx_defconfig
arm netwinder_defconfig
openrisc simple_smp_defconfig
sh ecovec24_defconfig
s390 debug_defconfig
powerpc ebony_defconfig
sh secureedge5410_defconfig
powerpc tqm8xx_defconfig
nios2 3c120_defconfig
sh se7724_defconfig
arc haps_hs_defconfig
xtensa smp_lx200_defconfig
arm multi_v5_defconfig
sh rts7751r2d1_defconfig
h8300 edosk2674_defconfig
powerpc pasemi_defconfig
m68k amcore_defconfig
powerpc ksi8560_defconfig
ia64 allmodconfig
ia64 defconfig
ia64 allyesconfig
m68k allmodconfig
m68k defconfig
m68k allyesconfig
nios2 defconfig
arc allyesconfig
nds32 allnoconfig
nds32 defconfig
nios2 allyesconfig
csky defconfig
alpha defconfig
alpha allyesconfig
xtensa allyesconfig
h8300 allyesconfig
arc defconfig
sh allmodconfig
parisc defconfig
s390 allyesconfig
s390 allmodconfig
parisc allyesconfig
s390 defconfig
sparc allyesconfig
sparc defconfig
i386 defconfig
mips allyesconfig
mips allmodconfig
powerpc allyesconfig
powerpc allmodconfig
powerpc allnoconfig
i386 randconfig-a006-20210409
i386 randconfig-a003-20210409
i386 randconfig-a001-20210409
i386 randconfig-a004-20210409
i386 randconfig-a002-20210409
i386 randconfig-a005-20210409
x86_64 randconfig-a014-20210410
x86_64 randconfig-a015-20210410
x86_64 randconfig-a011-20210410
x86_64 randconfig-a013-20210410
x86_64 randconfig-a012-20210410
x86_64 randconfig-a016-20210410
i386 randconfig-a015-20210411
i386 randconfig-a014-20210411
i386 randconfig-a013-20210411
i386 randconfig-a012-20210411
i386 randconfig-a016-20210411
i386 randconfig-a011-20210411
x86_64 randconfig-a003-20210411
x86_64 randconfig-a002-20210411
x86_64 randconfig-a001-20210411
x86_64 randconfig-a005-20210411
x86_64 randconfig-a006-20210411
x86_64 randconfig-a004-20210411
riscv nommu_k210_defconfig
riscv allyesconfig
riscv nommu_virt_defconfig
riscv allnoconfig
riscv defconfig
riscv rv32_defconfig
um allmodconfig
um allnoconfig
um allyesconfig
um defconfig
x86_64 rhel-8.3-kselftests
x86_64 defconfig
x86_64 rhel-8.3
x86_64 rhel-8.3-kbuiltin
x86_64 kexec
clang tested configs:
x86_64 randconfig-a004-20210409
x86_64 randconfig-a005-20210409
x86_64 randconfig-a003-20210409
x86_64 randconfig-a001-20210409
x86_64 randconfig-a002-20210409
x86_64 randconfig-a006-20210409
x86_64 randconfig-a014-20210411
x86_64 randconfig-a015-20210411
x86_64 randconfig-a011-20210411
x86_64 randconfig-a013-20210411
x86_64 randconfig-a012-20210411
x86_64 randconfig-a016-20210411
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
^ permalink raw reply
* Re: [PATCH v2 05/14] powerpc/kernel/iommu: Add new iommu_table_in_use() helper
From: Leonardo Bras @ 2021-04-11 6:55 UTC (permalink / raw)
To: Alexey Kardashevskiy, Michael Ellerman, Benjamin Herrenschmidt,
Paul Mackerras, Joel Stanley, Christophe Leroy,
Thiago Jung Bauermann, Ram Pai, Brian King,
Murilo Fossa Vicentini, David Dai
Cc: linuxppc-dev
In-Reply-To: <7af21a72-507b-42ce-77ad-d7fc377590d1@ozlabs.ru>
Hello Alexey, thanks for the feedback!
On Tue, 2020-09-29 at 13:57 +1000, Alexey Kardashevskiy wrote:
>
> On 12/09/2020 03:07, Leonardo Bras wrote:
> > diff --git a/arch/powerpc/kernel/iommu.c b/arch/powerpc/kernel/iommu.c
> > index ffb2637dc82b..c838da3d8f32 100644
> > --- a/arch/powerpc/kernel/iommu.c
> > +++ b/arch/powerpc/kernel/iommu.c
> > @@ -655,34 +655,21 @@ static void iommu_table_reserve_pages(struct iommu_table *tbl,
> > if (tbl->it_offset == 0)
> > set_bit(0, tbl->it_map);
> >
> >
> >
> >
> > + /* Check if res_start..res_end is a valid range in the table */
> > + if (res_start >= res_end || res_start < tbl->it_offset ||
> > + res_end > (tbl->it_offset + tbl->it_size)) {
> > + tbl->it_reserved_start = tbl->it_offset;
> > + tbl->it_reserved_end = tbl->it_offset;
>
>
> This silently ignores overlapped range of the reserved area and the
> window which does not seem right.
Humm, that makes sense.
Would it be better to do something like this?
if (res_start < tbl->it_offset)
res_start = tbl->it_offset;
if (res_end > (tbl->it_offset + tbl->it_size))
res_end = tbl->it_offset + tbl->it_size;
if (res_start >= res_end) {
tbl->it_reserved_start = tbl->it_offset;
tbl->it_reserved_end = tbl->it_offset;
return;
}
> > + return;
> > + }
> > +
> > tbl->it_reserved_start = res_start;
> > tbl->it_reserved_end = res_end;
> > - /* Check if res_start..res_end isn't empty and overlaps the table */
> > - if (res_start && res_end &&
> > - (tbl->it_offset + tbl->it_size < res_start ||
> > - res_end < tbl->it_offset))
> > - return;
> > -
> > for (i = tbl->it_reserved_start; i < tbl->it_reserved_end; ++i)
> > set_bit(i - tbl->it_offset, tbl->it_map);
> > }
> > +bool iommu_table_in_use(struct iommu_table *tbl)
> > +{
> > + unsigned long start = 0, end;
> > +
> > + /* ignore reserved bit0 */
> > + if (tbl->it_offset == 0)
> > + start = 1;
> > + end = tbl->it_reserved_start - tbl->it_offset;
> > + if (find_next_bit(tbl->it_map, end, start) != end)
> > + return true;
> > +
> > + start = tbl->it_reserved_end - tbl->it_offset;
> > + end = tbl->it_size;
> > + return find_next_bit(tbl->it_map, end, start) != end;
> > +
>
> Unnecessary empty line.
Sure, removing.
Thanks!
^ permalink raw reply
* Re: [PATCH 14/16] crypto/nx: Register and unregister VAS interface
From: kernel test robot @ 2021-04-11 7:48 UTC (permalink / raw)
To: Haren Myneni, linuxppc-dev, linux-crypto, mpe, herbert, npiggin
Cc: kbuild-all, haren
In-Reply-To: <3b7f3ec660db031e84306e8d9c4917bc737a58d3.camel@linux.ibm.com>
[-- Attachment #1: Type: text/plain, Size: 1832 bytes --]
Hi Haren,
I love your patch! Yet something to improve:
[auto build test ERROR on powerpc/next]
[also build test ERROR on cryptodev/master crypto/master v5.12-rc6 next-20210409]
[cannot apply to scottwood/next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Haren-Myneni/Enable-VAS-and-NX-GZIP-support-on-powerVM/20210411-084631
base: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next
config: powerpc-allmodconfig (attached as .config)
compiler: powerpc64-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/8650d30be9c22ee8fdc59063b993bfbafe88a328
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Haren-Myneni/Enable-VAS-and-NX-GZIP-support-on-powerVM/20210411-084631
git checkout 8650d30be9c22ee8fdc59063b993bfbafe88a328
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=powerpc
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>, old ones prefixed by <<):
>> ERROR: modpost: ".vas_unregister_api_pseries" [drivers/crypto/nx/nx-compress-pseries.ko] undefined!
>> ERROR: modpost: ".vas_register_api_pseries" [drivers/crypto/nx/nx-compress-pseries.ko] undefined!
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 72704 bytes --]
^ permalink raw reply
* Re: [PATCH 15/16] crypto/nx: Get NX capabilities for GZIP coprocessor type
From: kernel test robot @ 2021-04-11 7:48 UTC (permalink / raw)
To: Haren Myneni, linuxppc-dev, linux-crypto, mpe, herbert, npiggin
Cc: kbuild-all, haren
In-Reply-To: <27f6fef4852a3fdbb36c3a35a357a0082c581be5.camel@linux.ibm.com>
[-- Attachment #1: Type: text/plain, Size: 2030 bytes --]
Hi Haren,
I love your patch! Yet something to improve:
[auto build test ERROR on powerpc/next]
[also build test ERROR on cryptodev/master crypto/master v5.12-rc6 next-20210409]
[cannot apply to scottwood/next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Haren-Myneni/Enable-VAS-and-NX-GZIP-support-on-powerVM/20210411-084631
base: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next
config: powerpc-allyesconfig (attached as .config)
compiler: powerpc64-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/3dc0fb58cbf2543e4f3cb016ef3ed475a975f3c9
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Haren-Myneni/Enable-VAS-and-NX-GZIP-support-on-powerVM/20210411-084631
git checkout 3dc0fb58cbf2543e4f3cb016ef3ed475a975f3c9
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=powerpc
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
powerpc64-linux-ld: drivers/crypto/nx/nx-common-pseries.o: in function `.nx842_pseries_init':
>> nx-common-pseries.c:(.init.text+0x184): undefined reference to `.plpar_vas_query_capabilities'
>> powerpc64-linux-ld: nx-common-pseries.c:(.init.text+0x28c): undefined reference to `.plpar_vas_query_capabilities'
>> powerpc64-linux-ld: nx-common-pseries.c:(.init.text+0x488): undefined reference to `.vas_register_api_pseries'
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 72709 bytes --]
^ permalink raw reply
* Re: [PATCH v2 09/14] powerpc/pseries/iommu: Add ddw_property_create() and refactor enable_ddw()
From: Leonardo Bras @ 2021-04-11 7:52 UTC (permalink / raw)
To: Alexey Kardashevskiy, Michael Ellerman, Benjamin Herrenschmidt,
Paul Mackerras, Joel Stanley, Christophe Leroy,
Thiago Jung Bauermann, Ram Pai, Brian King,
Murilo Fossa Vicentini, David Dai
Cc: linuxppc-dev
In-Reply-To: <8442d9df-d9f9-f919-211b-e94cc1822e26@ozlabs.ru>
On Tue, 2020-09-29 at 13:56 +1000, Alexey Kardashevskiy wrote:
> >
> > dev_dbg(&dev->dev, "created tce table LIOBN 0x%x for %pOF\n",
> > - create.liobn, dn);
> > + create.liobn, dn);
>
>
> Unrelated. If you think the spaces/tabs thing needs to be fixed, make it
> a separate patch and do all these changes there at once.
Sorry, it was some issue with my editor / diff.
I removed those changes for next version.
> > -out_free_prop:
> > +out_prop_free:
>
>
> Really? :) s/out_prop_del/out_del_prop/ may be? The less unrelated
> changes the better.
I changed all labels I added to have out_<action>_<target>, I think
that will allow it to stay like existing labels.
Thanks for reviewing!
Leonardo Bras
^ permalink raw reply
* Re: [PATCH 00/16] Enable VAS and NX-GZIP support on powerVM
From: Christophe Leroy @ 2021-04-11 8:07 UTC (permalink / raw)
To: Haren Myneni, linuxppc-dev, linux-crypto, mpe, herbert, npiggin
In-Reply-To: <b4631127bd025d9585246606c350ec88dbe1e99a.camel@linux.ibm.com>
Le 11/04/2021 à 02:27, Haren Myneni a écrit :
>
> This patch series enables VAS / NX-GZIP on powerVM which allows
> the user space to do copy/paste with the same existing interface
> that is available on powerNV.
Can you explain (here and in patch 1 at least) what VAS and NX means ?
Is that Vector Addition System ? Is that Virtual Address Space ?
(https://en.wikipedia.org/wiki/VAS)
>
> VAS Enablement:
> - Get all VAS capabilities using H_QUERY_VAS_CAPABILITIES that are
> available in the hypervisor. These capabilities tells OS which
> type of features (credit types such as Default and Quality of
> Service (QoS)). Also gives specific capabilities for each credit
> type: Maximum window credits, Maximum LPAR credits, Target credits
> in that parition (varies from max LPAR credits based DLPAR
> operation), whether supports user mode COPY/PASTE and etc.
> - Register LPAR VAS operations such as open window. get paste
> address and close window with the current VAS user space API.
> - Open window operation - Use H_ALLOCATE_VAS_WINDOW HCALL to open
> window and H_MODIFY_VAS_WINDOW HCALL to setup the window with LPAR
> PID and etc.
> - mmap to paste address returned in H_ALLOCATE_VAS_WINDOW HCALL
> - To close window, H_DEALLOCATE_VAS_WINDOW HCALL is used to close in
> the hypervisor.
>
> NX Enablement:
> - Get NX capabilities from the the hypervisor which provides Maximum
> buffer length in a single GZIP request, recommended minimum
> compression / decompression lengths.
> - Register to VAS to enable user space VAS API
>
> Main feature differences with powerNV implementation:
> - Each VAS window will be configured with a number of credits which
> means that many requests can be issues simultaniously on that
> window. On powerNV, 1K credits are configured per window.
> Whereas on powerVM, the hypervisor allows 1 credit per window
> at present.
> - The hypervisor introduced 2 different types of credits: Default -
> Uses normal priority FIFO and Quality of Service (QoS) - Uses high
> priority FIFO. On powerVM, VAS/NX HW resources are shared across
> LPARs. The total number of credits available on a system depends
> on cores configured. We may see more credits are assigned across
> the system than the NX HW resources can handle. So to avoid NX HW
> contention, pHyp introduced QoS credits which can be configured
> by system administration with HMC API. Then the total number of
> available default credits on LPAR varies based on QoS credits
> configured.
> - On powerNV, windows are allocated on a specific VAS instance
> and the user space can select VAS instance with the open window
> ioctl. Since VAS instances can be shared across partitions on
> powerVM, the hypervisor manages window allocations on different
> VAS instances. So H_ALLOCATE_VAS_WINDOW allows to select by domain
> indentifiers (H_HOME_NODE_ASSOCIATIVITY values by cpu). By default
> the hypervisor selects VAS instance closer to CPU resources that the
> parition uses. So vas_id in ioctl interface is ignored on powerVM
> except vas_id=-1 which is used to allocate window based on CPU that
> the process is executing. This option is needed for process affinity
> to NUMA node.
>
> The existing applications that linked with libnxz should work as
> long as the job request length is restricted to
> req_max_processed_len.
>
> Tested the following patches on P10 successfully with test cases
> given: https://github.com/libnxz/power-gzip
>
> Note: The hypervisor supports user mode NX from p10 onwards. Linux
> supports user mode VAS/NX on P10 only with radix page tables.
>
> Patches 1- 4: Make the code that is needed for both powerNV and
> powerVM to powerpc platform independent.
> Patch5: Modify vas-window struct to support both and the
> related changes.
> Patch 6: Define HCALL and the related VAS/NXGZIP specific
> structs.
> Patch 7: Define QoS credit flag in window open ioctl
> Patch 8: Implement Allocate, Modify and Deallocate HCALLs
> Patch 9: Retrieve VAS capabilities from the hypervisor
> Patch 10; Implement window operations and integrate with API
> Patch 11: Setup IRQ and NX fault handling
> Patch 12; Add sysfs interface to expose VAS capabilities
> Patch 13 - 14: Make the code common to add NX-GZIP enablement
> Patch 15: Get NX capabilities from the hypervisor
> patch 16; Add sysfs interface to expose NX capabilities
>
> Haren Myneni (16):
> powerpc/powernv/vas: Rename register/unregister functions
> powerpc/vas: Make VAS API powerpc platform independent
> powerpc/vas: Create take/drop task reference functions
> powerpc/vas: Move update_csb/dump_crb to platform independent
> powerpc/vas: Define and use common vas_window struct
> powerpc/pseries/vas: Define VAS/NXGZIP HCALLs and structs
> powerpc/vas: Define QoS credit flag to allocate window
> powerpc/pseries/vas: Implement allocate/modify/deallocate HCALLS
> powerpc/pseries/vas: Implement to get all capabilities
> powerpc/pseries/vas: Integrate API with open/close windows
> powerpc/pseries/vas: Setup IRQ and fault handling
> powerpc/pseries/vas: sysfs interface to export capabilities
> crypto/nx: Rename nx-842-pseries file name to nx-common-pseries
> crypto/nx: Register and unregister VAS interface
> crypto/nx: Get NX capabilities for GZIP coprocessor type
> crypto/nx: sysfs interface to export NX capabilities
>
> arch/powerpc/Kconfig | 15 +
> arch/powerpc/include/asm/hvcall.h | 7 +
> arch/powerpc/include/asm/vas.h | 122 +++-
> arch/powerpc/include/uapi/asm/vas-api.h | 6 +-
> arch/powerpc/kernel/Makefile | 1 +
> arch/powerpc/kernel/vas-api.c | 485 +++++++++++++
> arch/powerpc/platforms/powernv/Kconfig | 14 -
> arch/powerpc/platforms/powernv/Makefile | 2 +-
> arch/powerpc/platforms/powernv/vas-api.c | 278 --------
> arch/powerpc/platforms/powernv/vas-debug.c | 12 +-
> arch/powerpc/platforms/powernv/vas-fault.c | 155 +---
> arch/powerpc/platforms/powernv/vas-trace.h | 6 +-
> arch/powerpc/platforms/powernv/vas-window.c | 250 ++++---
> arch/powerpc/platforms/powernv/vas.h | 42 +-
> arch/powerpc/platforms/pseries/Makefile | 1 +
> arch/powerpc/platforms/pseries/vas-sysfs.c | 173 +++++
> arch/powerpc/platforms/pseries/vas.c | 674 ++++++++++++++++++
> arch/powerpc/platforms/pseries/vas.h | 98 +++
> drivers/crypto/nx/Makefile | 2 +-
> drivers/crypto/nx/nx-common-powernv.c | 6 +-
> .../{nx-842-pseries.c => nx-common-pseries.c} | 135 ++++
> 21 files changed, 1885 insertions(+), 599 deletions(-)
> create mode 100644 arch/powerpc/kernel/vas-api.c
> delete mode 100644 arch/powerpc/platforms/powernv/vas-api.c
> create mode 100644 arch/powerpc/platforms/pseries/vas-sysfs.c
> create mode 100644 arch/powerpc/platforms/pseries/vas.c
> create mode 100644 arch/powerpc/platforms/pseries/vas.h
> rename drivers/crypto/nx/{nx-842-pseries.c => nx-common-pseries.c} (90%)
>
^ permalink raw reply
* Re: [PATCH v2 10/14] powerpc/pseries/iommu: Reorganize iommu_table_setparms*() with new helper
From: Leonardo Bras @ 2021-04-11 8:16 UTC (permalink / raw)
To: Alexey Kardashevskiy, Michael Ellerman, Benjamin Herrenschmidt,
Paul Mackerras, Joel Stanley, Christophe Leroy,
Thiago Jung Bauermann, Ram Pai, Brian King,
Murilo Fossa Vicentini, David Dai
Cc: linuxppc-dev
In-Reply-To: <aecd317f-ba69-5676-ba30-c51cf5d4ed44@ozlabs.ru>
On Tue, 2020-09-29 at 13:56 +1000, Alexey Kardashevskiy wrote:
>
> On 12/09/2020 03:07, Leonardo Bras wrote:
> > Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org,
> >
> > Add a new helper _iommu_table_setparms(), and use it in
> > iommu_table_setparms() and iommu_table_setparms_lpar() to avoid duplicated
> > code.
> >
> > Also, setting tbl->it_ops was happening outsite iommu_table_setparms*(),
> > so move it to the new helper. Since we need the iommu_table_ops to be
> > declared before used, move iommu_table_lpar_multi_ops and
> > iommu_table_pseries_ops to before their respective iommu_table_setparms*().
> >
> > The tce_exchange_pseries() also had to be moved up, since it's used in
> > iommu_table_lpar_multi_ops.xchg_no_kill.
>
>
> Use forward declarations (preferred) or make a separate patch for moving
> chunks (I do not see much point).
Fixed :)
> > @@ -509,8 +559,13 @@ static void iommu_table_setparms(struct pci_controller *phb,
> > const unsigned long *basep;
> > const u32 *sizep;
> > - node = phb->dn;
> > + /* Test if we are going over 2GB of DMA space */
> >
> >
> >
> > + if (phb->dma_window_base_cur + phb->dma_window_size > 0x80000000ul) {
> > + udbg_printf("PCI_DMA: Unexpected number of IOAs under this PHB.\n");
> > + panic("PCI_DMA: Unexpected number of IOAs under this PHB.\n");
> > + }
>
>
> s/0x80000000ul/2*SZ_1G/
Done!
>
> but more to the point - why this check? QEMU can create windows at 0 and
> as big as the VM requested. And I am pretty sure I can construct QEMU
> command line such as it won't have MMIO32 at all and a 4GB default DMA
> window.
>
Oh, the diff was a little strange here. I did not add this snippet, it
was already in that function, but since I created the helper, the diff
made it look like I introduced this piece of code.
Please take a look in the diff snippet bellow. (This same lines were
there.)
> > @@ -519,33 +574,25 @@ static void iommu_table_setparms(struct pci_controller *phb,
> > return;
> > }
> >
> > - tbl->it_base = (unsigned long)__va(*basep);
> >
> >
> >
> > + _iommu_table_setparms(tbl, phb->bus->number, 0, phb->dma_window_base_cur,
> > + phb->dma_window_size, IOMMU_PAGE_SHIFT_4K,
> > + (unsigned long)__va(*basep), &iommu_table_pseries_ops);
> > if (!is_kdump_kernel())
> >
> >
> >
> > memset((void *)tbl->it_base, 0, *sizep);
> >
> > - tbl->it_busno = phb->bus->number;
> > - tbl->it_page_shift = IOMMU_PAGE_SHIFT_4K;
> > -
> > - /* Units of tce entries */
> > - tbl->it_offset = phb->dma_window_base_cur >> tbl->it_page_shift;
> > -
> > - /* Test if we are going over 2GB of DMA space */
> > - if (phb->dma_window_base_cur + phb->dma_window_size > 0x80000000ul) {
> > - udbg_printf("PCI_DMA: Unexpected number of IOAs under this PHB.\n");
> > - panic("PCI_DMA: Unexpected number of IOAs under this PHB.\n");
> > - }
> > -
> > phb->dma_window_base_cur += phb->dma_window_size;
> > -
> > - /* Set the tce table size - measured in entries */
> > - tbl->it_size = phb->dma_window_size >> tbl->it_page_shift;
> > -
> > - tbl->it_index = 0;
> > - tbl->it_blocksize = 16;
> > - tbl->it_type = TCE_PCI;
> > }
> >
Thanks for reviewing, Alexey!
^ permalink raw reply
* Re: [PATCH 02/16] powerpc/vas: Make VAS API powerpc platform independent
From: Christophe Leroy @ 2021-04-11 8:49 UTC (permalink / raw)
To: Haren Myneni, linuxppc-dev, linux-crypto, mpe, herbert, npiggin
In-Reply-To: <d416c7c03dfa20211bf84b760ceaeed307364509.camel@linux.ibm.com>
Le 11/04/2021 à 02:31, Haren Myneni a écrit :
>
> Using the same /dev/crypto/nx-gzip interface for both powerNV and
> pseries. So this patcb moves VAS API to powerpc platform indepedent
> directory. The actual functionality is not changed in this patch.
This patch seems to do a lot more than moving VAS API to independent directory. A more detailed
description would help.
And it is not something defined in the powerpc architecture I think, so it should
remain in some common platform related directory.
>
> Signed-off-by: Haren Myneni <haren@linux.ibm.com>
> ---
> arch/powerpc/Kconfig | 15 +++++
> arch/powerpc/include/asm/vas.h | 22 ++++++-
> arch/powerpc/kernel/Makefile | 1 +
> .../{platforms/powernv => kernel}/vas-api.c | 64 ++++++++++--------
> arch/powerpc/platforms/powernv/Kconfig | 14 ----
> arch/powerpc/platforms/powernv/Makefile | 2 +-
> arch/powerpc/platforms/powernv/vas-window.c | 66 +++++++++++++++++++
> 7 files changed, 140 insertions(+), 44 deletions(-)
> rename arch/powerpc/{platforms/powernv => kernel}/vas-api.c (83%)
>
> diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
> index 386ae12d8523..7aa1fbf7c1dc 100644
> --- a/arch/powerpc/Kconfig
> +++ b/arch/powerpc/Kconfig
> @@ -478,6 +478,21 @@ config PPC_UV
>
> If unsure, say "N".
>
> +config PPC_VAS
> + bool "IBM Virtual Accelerator Switchboard (VAS)"
> + depends on PPC_POWERNV && PPC_64K_PAGES
> + default y
> + help
> + This enables support for IBM Virtual Accelerator Switchboard (VAS).
IIUC is a functionnality in a coprocessor of some IBM processors. Something similar in principle to
the communication coprocessors we find in Freescale processors.
It is not a generic functionnality part of the powerpc architecture, I don't think this belongs to
arch/powerpc/Kconfig
I think it should go in arch/powerpc/platform/Kconfig
Or maybe in drivers/soc/ibm/ ?
> +
> + VAS allows accelerators in co-processors like NX-GZIP and NX-842
> + to be accessible to kernel subsystems and user processes.
> + VAS adapters are found in POWER9 and later based systems.
> + The user mode NX-GZIP support is added on P9 for powerNV and on
> + P10 for powerVM.
> +
> + If unsure, say "N".
> +
> config LD_HEAD_STUB_CATCH
> bool "Reserve 256 bytes to cope with linker stubs in HEAD text" if EXPERT
> depends on PPC64
> diff --git a/arch/powerpc/include/asm/vas.h b/arch/powerpc/include/asm/vas.h
> index 41f73fae7ab8..6bbade60d8f4 100644
> --- a/arch/powerpc/include/asm/vas.h
> +++ b/arch/powerpc/include/asm/vas.h
> @@ -5,6 +5,8 @@
>
> #ifndef _ASM_POWERPC_VAS_H
> #define _ASM_POWERPC_VAS_H
> +#include <uapi/asm/vas-api.h>
> +
>
> struct vas_window;
>
> @@ -48,6 +50,16 @@ enum vas_cop_type {
> VAS_COP_TYPE_MAX,
> };
>
> +/*
> + * User space window operations used for powernv and powerVM
> + */
> +struct vas_user_win_ops {
> + struct vas_window * (*open_win)(struct vas_tx_win_open_attr *,
> + enum vas_cop_type);
> + u64 (*paste_addr)(void *);
> + int (*close_win)(void *);
> +};
> +
> /*
> * Receive window attributes specified by the (in-kernel) owner of window.
> */
> @@ -161,6 +173,9 @@ int vas_copy_crb(void *crb, int offset);
> * assumed to be true for NX windows.
> */
> int vas_paste_crb(struct vas_window *win, int offset, bool re);
> +int vas_register_api_powernv(struct module *mod, enum vas_cop_type cop_type,
> + const char *name);
> +void vas_unregister_api_powernv(void);
>
> /*
> * Register / unregister coprocessor type to VAS API which will be exported
> @@ -170,8 +185,9 @@ int vas_paste_crb(struct vas_window *win, int offset, bool re);
> * Only NX GZIP coprocessor type is supported now, but this API can be
> * used for others in future.
> */
> -int vas_register_api_powernv(struct module *mod, enum vas_cop_type cop_type,
> - const char *name);
> -void vas_unregister_api_powernv(void);
> +int vas_register_coproc_api(struct module *mod, enum vas_cop_type cop_type,
> + const char *name,
> + struct vas_user_win_ops *vops);
> +void vas_unregister_coproc_api(void);
>
> #endif /* __ASM_POWERPC_VAS_H */
> diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
> index 6084fa499aa3..205d8f12bd36 100644
> --- a/arch/powerpc/kernel/Makefile
> +++ b/arch/powerpc/kernel/Makefile
> @@ -118,6 +118,7 @@ obj-$(CONFIG_PPC_UDBG_16550) += legacy_serial.o udbg_16550.o
> obj-$(CONFIG_STACKTRACE) += stacktrace.o
> obj-$(CONFIG_SWIOTLB) += dma-swiotlb.o
> obj-$(CONFIG_ARCH_HAS_DMA_SET_MASK) += dma-mask.o
> +obj-$(CONFIG_PPC_VAS) += vas-api.o
>
> pci64-$(CONFIG_PPC64) += pci_dn.o pci-hotplug.o isa-bridge.o
> obj-$(CONFIG_PCI) += pci_$(BITS).o $(pci64-y) \
> diff --git a/arch/powerpc/platforms/powernv/vas-api.c b/arch/powerpc/kernel/vas-api.c
> similarity index 83%
> rename from arch/powerpc/platforms/powernv/vas-api.c
> rename to arch/powerpc/kernel/vas-api.c
> index 72d8ce39e56c..05d7b99acf41 100644
> --- a/arch/powerpc/platforms/powernv/vas-api.c
> +++ b/arch/powerpc/kernel/vas-api.c
> @@ -4,15 +4,20 @@
> * Copyright (C) 2019 Haren Myneni, IBM Corp
> */
>
> +#include <linux/module.h>
> #include <linux/kernel.h>
> #include <linux/device.h>
> #include <linux/cdev.h>
> #include <linux/fs.h>
> #include <linux/slab.h>
> #include <linux/uaccess.h>
> +#include <linux/kthread.h>
> +#include <linux/sched/signal.h>
> +#include <linux/sched/mm.h>
> +#include <linux/mmu_context.h>
> #include <asm/vas.h>
> +#include <asm/icswx.h>
> #include <uapi/asm/vas-api.h>
> -#include "vas.h"
>
> /*
> * The driver creates the device node that can be used as follows:
> @@ -42,6 +47,7 @@ static struct coproc_dev {
> dev_t devt;
> struct class *class;
> enum vas_cop_type cop_type;
> + struct vas_user_win_ops *vops;
> } coproc_device;
>
> struct coproc_instance {
> @@ -72,11 +78,10 @@ static int coproc_open(struct inode *inode, struct file *fp)
> static int coproc_ioc_tx_win_open(struct file *fp, unsigned long arg)
> {
> void __user *uptr = (void __user *)arg;
> - struct vas_tx_win_attr txattr = {};
> struct vas_tx_win_open_attr uattr;
> struct coproc_instance *cp_inst;
> struct vas_window *txwin;
> - int rc, vasid;
> + int rc;
>
> cp_inst = fp->private_data;
>
> @@ -93,27 +98,20 @@ static int coproc_ioc_tx_win_open(struct file *fp, unsigned long arg)
> }
>
> if (uattr.version != 1) {
> - pr_err("Invalid version\n");
> + pr_err("Invalid window open API version\n");
> return -EINVAL;
> }
>
> - vasid = uattr.vas_id;
> -
> - vas_init_tx_win_attr(&txattr, cp_inst->coproc->cop_type);
> -
> - txattr.lpid = mfspr(SPRN_LPID);
> - txattr.pidr = mfspr(SPRN_PID);
> - txattr.user_win = true;
> - txattr.rsvd_txbuf_count = false;
> - txattr.pswid = false;
> -
> - pr_devel("Pid %d: Opening txwin, PIDR %ld\n", txattr.pidr,
> - mfspr(SPRN_PID));
> + if (!cp_inst->coproc->vops && !cp_inst->coproc->vops->open_win) {
> + pr_err("VAS API is not registered\n");
> + return -EACCES;
> + }
>
> - txwin = vas_tx_win_open(vasid, cp_inst->coproc->cop_type, &txattr);
> + txwin = cp_inst->coproc->vops->open_win(&uattr,
> + cp_inst->coproc->cop_type);
> if (IS_ERR(txwin)) {
> - pr_err("%s() vas_tx_win_open() failed, %ld\n", __func__,
> - PTR_ERR(txwin));
> + pr_err("%s() VAS window open failed, %ld\n", __func__,
> + PTR_ERR(txwin));
> return PTR_ERR(txwin);
> }
>
> @@ -125,9 +123,14 @@ static int coproc_ioc_tx_win_open(struct file *fp, unsigned long arg)
> static int coproc_release(struct inode *inode, struct file *fp)
> {
> struct coproc_instance *cp_inst = fp->private_data;
> + int rc = 0;
>
> if (cp_inst->txwin) {
> - vas_win_close(cp_inst->txwin);
> + if (cp_inst->coproc->vops && cp_inst->coproc->vops->close_win) {
> + rc = cp_inst->coproc->vops->close_win(cp_inst->txwin);
> + if (rc)
> + return rc;
> + }
> cp_inst->txwin = NULL;
> }
>
> @@ -168,7 +171,17 @@ static int coproc_mmap(struct file *fp, struct vm_area_struct *vma)
> return -EINVAL;
> }
>
> - vas_win_paste_addr(txwin, &paste_addr, NULL);
> + if (!cp_inst->coproc->vops && !cp_inst->coproc->vops->paste_addr) {
> + pr_err("%s(): VAS API is not registered\n", __func__);
> + return -EACCES;
> + }
> +
> + paste_addr = cp_inst->coproc->vops->paste_addr(txwin);
> + if (!paste_addr) {
> + pr_err("%s(): Window paste address failed\n", __func__);
> + return -EINVAL;
> + }
> +
> pfn = paste_addr >> PAGE_SHIFT;
>
> /* flags, page_prot from cxl_mmap(), except we want cachable */
> @@ -207,8 +220,8 @@ static struct file_operations coproc_fops = {
> * Supporting only nx-gzip coprocessor type now, but this API code
> * extended to other coprocessor types later.
> */
> -int vas_register_api_powernv(struct module *mod, enum vas_cop_type cop_type,
> - const char *name)
> +int vas_register_coproc_api(struct module *mod, enum vas_cop_type cop_type,
> + const char *name, struct vas_user_win_ops *vops)
> {
> int rc = -EINVAL;
> dev_t devno;
> @@ -230,6 +243,7 @@ int vas_register_api_powernv(struct module *mod, enum vas_cop_type cop_type,
> }
> coproc_device.class->devnode = coproc_devnode;
> coproc_device.cop_type = cop_type;
> + coproc_device.vops = vops;
>
> coproc_fops.owner = mod;
> cdev_init(&coproc_device.cdev, &coproc_fops);
> @@ -262,9 +276,8 @@ int vas_register_api_powernv(struct module *mod, enum vas_cop_type cop_type,
> unregister_chrdev_region(coproc_device.devt, 1);
> return rc;
> }
> -EXPORT_SYMBOL_GPL(vas_register_api_powernv);
>
> -void vas_unregister_api_powernv(void)
> +void vas_unregister_coproc_api(void)
> {
> dev_t devno;
>
> @@ -275,4 +288,3 @@ void vas_unregister_api_powernv(void)
> class_destroy(coproc_device.class);
> unregister_chrdev_region(coproc_device.devt, 1);
> }
> -EXPORT_SYMBOL_GPL(vas_unregister_api_powernv);
> diff --git a/arch/powerpc/platforms/powernv/Kconfig b/arch/powerpc/platforms/powernv/Kconfig
> index 619b093a0657..043eefbbdd28 100644
> --- a/arch/powerpc/platforms/powernv/Kconfig
> +++ b/arch/powerpc/platforms/powernv/Kconfig
> @@ -33,20 +33,6 @@ config PPC_MEMTRACE
> Enabling this option allows for runtime allocation of memory (RAM)
> for hardware tracing.
>
> -config PPC_VAS
> - bool "IBM Virtual Accelerator Switchboard (VAS)"
> - depends on PPC_POWERNV && PPC_64K_PAGES
> - default y
> - help
> - This enables support for IBM Virtual Accelerator Switchboard (VAS).
> -
> - VAS allows accelerators in co-processors like NX-GZIP and NX-842
> - to be accessible to kernel subsystems and user processes.
> -
> - VAS adapters are found in POWER9 based systems.
> -
> - If unsure, say N.
> -
> config SCOM_DEBUGFS
> bool "Expose SCOM controllers via debugfs"
> depends on DEBUG_FS
> diff --git a/arch/powerpc/platforms/powernv/Makefile b/arch/powerpc/platforms/powernv/Makefile
> index 2eb6ae150d1f..c747a1f1d25b 100644
> --- a/arch/powerpc/platforms/powernv/Makefile
> +++ b/arch/powerpc/platforms/powernv/Makefile
> @@ -18,7 +18,7 @@ obj-$(CONFIG_MEMORY_FAILURE) += opal-memory-errors.o
> obj-$(CONFIG_OPAL_PRD) += opal-prd.o
> obj-$(CONFIG_PERF_EVENTS) += opal-imc.o
> obj-$(CONFIG_PPC_MEMTRACE) += memtrace.o
> -obj-$(CONFIG_PPC_VAS) += vas.o vas-window.o vas-debug.o vas-fault.o vas-api.o
> +obj-$(CONFIG_PPC_VAS) += vas.o vas-window.o vas-debug.o vas-fault.o
> obj-$(CONFIG_OCXL_BASE) += ocxl.o
> obj-$(CONFIG_SCOM_DEBUGFS) += opal-xscom.o
> obj-$(CONFIG_PPC_SECURE_BOOT) += opal-secvar.o
> diff --git a/arch/powerpc/platforms/powernv/vas-window.c b/arch/powerpc/platforms/powernv/vas-window.c
> index 5f5fe63a3d1c..b973dd574b47 100644
> --- a/arch/powerpc/platforms/powernv/vas-window.c
> +++ b/arch/powerpc/platforms/powernv/vas-window.c
> @@ -16,6 +16,8 @@
> #include <linux/mmu_context.h>
> #include <asm/switch_to.h>
> #include <asm/ppc-opcode.h>
> +#include <asm/vas.h>
> +#include <uapi/asm/vas-api.h>
> #include "vas.h"
> #include "copy-paste.h"
>
> @@ -1441,3 +1443,67 @@ struct vas_window *vas_pswid_to_window(struct vas_instance *vinst,
>
> return window;
> }
> +
> +static struct vas_window *vas_user_win_open(struct vas_tx_win_open_attr *uattr,
> + enum vas_cop_type cop_type)
> +{
> + struct vas_tx_win_attr txattr = {};
> +
> + vas_init_tx_win_attr(&txattr, cop_type);
> +
> + txattr.lpid = mfspr(SPRN_LPID);
> + txattr.pidr = mfspr(SPRN_PID);
> + txattr.user_win = true;
> + txattr.rsvd_txbuf_count = false;
> + txattr.pswid = false;
> +
> + pr_devel("Pid %d: Opening txwin, PIDR %ld\n", txattr.pidr,
> + mfspr(SPRN_PID));
> +
> + return vas_tx_win_open(uattr->vas_id, cop_type, &txattr);
> +}
> +
> +static u64 vas_user_win_paste_addr(void *addr)
> +{
> + u64 paste_addr;
> +
> + vas_win_paste_addr((struct vas_window *)addr, &paste_addr, NULL);
> +
> + return paste_addr;
> +}
> +
> +static int vas_user_win_close(void *addr)
> +{
> + struct vas_window *txwin = addr;
> +
> + vas_win_close(txwin);
> +
> + return 0;
> +}
> +
> +static struct vas_user_win_ops vops = {
> + .open_win = vas_user_win_open,
> + .paste_addr = vas_user_win_paste_addr,
> + .close_win = vas_user_win_close,
> +};
> +
> +/*
> + * Supporting only nx-gzip coprocessor type now, but this API code
> + * extended to other coprocessor types later.
> + */
> +int vas_register_api_powernv(struct module *mod, enum vas_cop_type cop_type,
> + const char *name)
> +{
> + int rc;
> +
> + rc = vas_register_coproc_api(mod, cop_type, name, &vops);
> +
> + return rc;
> +}
> +EXPORT_SYMBOL_GPL(vas_register_api_powernv);
> +
> +void vas_unregister_api_powernv(void)
> +{
> + vas_unregister_coproc_api();
> +}
> +EXPORT_SYMBOL_GPL(vas_unregister_api_powernv);
>
^ permalink raw reply
* Re: [PATCH 1/1] mm: Fix struct page layout on 32-bit systems
From: Jesper Dangaard Brouer @ 2021-04-11 9:43 UTC (permalink / raw)
To: Matthew Wilcox (Oracle)
Cc: Arnd Bergmann, Grygorii Strashko, Ivan Khoronzhuk, netdev,
Ilias Apalodimas, linux-mips, linux-kernel, linux-mm, brouer,
Matteo Croce, linuxppc-dev, Christoph Hellwig, linux-arm-kernel
In-Reply-To: <20210410205246.507048-2-willy@infradead.org>
On Sat, 10 Apr 2021 21:52:45 +0100
"Matthew Wilcox (Oracle)" <willy@infradead.org> wrote:
> 32-bit architectures which expect 8-byte alignment for 8-byte integers
> and need 64-bit DMA addresses (arc, arm, mips, ppc) had their struct
> page inadvertently expanded in 2019. When the dma_addr_t was added,
> it forced the alignment of the union to 8 bytes, which inserted a 4 byte
> gap between 'flags' and the union.
>
> We could fix this by telling the compiler to use a smaller alignment
> for the dma_addr, but that seems a little fragile. Instead, move the
> 'flags' into the union. That causes dma_addr to shift into the same
> bits as 'mapping', so it would have to be cleared on free. To avoid
> this, insert three words of padding and use the same bits as ->index
> and ->private, neither of which have to be cleared on free.
>
> Fixes: c25fff7171be ("mm: add dma_addr_t to struct page")
> Signed-off-by: Matthew Wilcox (Oracle) <willy@infradead.org>
> ---
> include/linux/mm_types.h | 38 ++++++++++++++++++++++++++------------
> 1 file changed, 26 insertions(+), 12 deletions(-)
>
> diff --git a/include/linux/mm_types.h b/include/linux/mm_types.h
> index 6613b26a8894..45c563e9b50e 100644
> --- a/include/linux/mm_types.h
> +++ b/include/linux/mm_types.h
> @@ -68,16 +68,22 @@ struct mem_cgroup;
> #endif
>
> struct page {
> - unsigned long flags; /* Atomic flags, some possibly
> - * updated asynchronously */
> /*
> - * Five words (20/40 bytes) are available in this union.
> - * WARNING: bit 0 of the first word is used for PageTail(). That
> - * means the other users of this union MUST NOT use the bit to
> + * This union is six words (24 / 48 bytes) in size.
> + * The first word is reserved for atomic flags, often updated
> + * asynchronously. Use the PageFoo() macros to access it. Some
> + * of the flags can be reused for your own purposes, but the
> + * word as a whole often contains other information and overwriting
> + * it will cause functions like page_zone() and page_node() to stop
> + * working correctly.
> + *
> + * Bit 0 of the second word is used for PageTail(). That
> + * means the other users of this union MUST leave the bit zero to
> * avoid collision and false-positive PageTail().
> */
> union {
> struct { /* Page cache and anonymous pages */
> + unsigned long flags;
> /**
> * @lru: Pageout list, eg. active_list protected by
> * lruvec->lru_lock. Sometimes used as a generic list
> @@ -96,13 +102,14 @@ struct page {
> unsigned long private;
> };
> struct { /* page_pool used by netstack */
> - /**
> - * @dma_addr: might require a 64-bit value even on
> - * 32-bit architectures.
> - */
> - dma_addr_t dma_addr;
The original intend of placing member @dma_addr here is that it overlap
with @LRU (type struct list_head) which contains two pointers. Thus, in
case of CONFIG_ARCH_DMA_ADDR_T_64BIT=y on 32-bit architectures it would
use both pointers.
Thinking more about this, this design is flawed as bit 0 of the first
word is used for compound pages (see PageTail and @compound_head), is
reserved. We knew DMA addresses were aligned, thus we though this
satisfied that need. BUT for DMA_ADDR_T_64BIT=y on 32-bit arch the
first word will contain the "upper" part of the DMA addr, which I don't
think gives this guarantee.
I guess, nobody are using this combination?!? I though we added this
to satisfy TI (Texas Instrument) driver cpsw (code in
drivers/net/ethernet/ti/cpsw*). Thus, I assumed it was in use?
> + unsigned long _pp_flags;
> + unsigned long pp_magic;
> + unsigned long xmi;
Matteo notice, I think intent is we can store xdp_mem_info in @xmi.
> + unsigned long _pp_mapping_pad;
> + dma_addr_t dma_addr; /* might be one or two words */
> };
Could you explain your intent here?
I worry about @index.
As I mentioned in other thread[1] netstack use page_is_pfmemalloc()
(code copy-pasted below signature) which imply that the member @index
have to be kept intact. In above, I'm unsure @index is untouched.
[1] https://lore.kernel.org/lkml/20210410082158.79ad09a6@carbon/
--
Best regards,
Jesper Dangaard Brouer
MSc.CS, Principal Kernel Engineer at Red Hat
LinkedIn: http://www.linkedin.com/in/brouer
/*
* Return true only if the page has been allocated with
* ALLOC_NO_WATERMARKS and the low watermark was not
* met implying that the system is under some pressure.
*/
static inline bool page_is_pfmemalloc(const struct page *page)
{
/*
* Page index cannot be this large so this must be
* a pfmemalloc page.
*/
return page->index == -1UL;
}
/*
* Only to be called by the page allocator on a freshly allocated
* page.
*/
static inline void set_page_pfmemalloc(struct page *page)
{
page->index = -1UL;
}
static inline void clear_page_pfmemalloc(struct page *page)
{
page->index = 0;
}
^ permalink raw reply
* Re: [PATCH 1/1] mm: Fix struct page layout on 32-bit systems
From: Matthew Wilcox @ 2021-04-11 10:33 UTC (permalink / raw)
To: Jesper Dangaard Brouer
Cc: Arnd Bergmann, Grygorii Strashko, Ivan Khoronzhuk, netdev,
Ilias Apalodimas, linux-mips, linux-kernel, linux-mm,
Matteo Croce, linuxppc-dev, Christoph Hellwig, linux-arm-kernel
In-Reply-To: <20210411114307.5087f958@carbon>
On Sun, Apr 11, 2021 at 11:43:07AM +0200, Jesper Dangaard Brouer wrote:
> On Sat, 10 Apr 2021 21:52:45 +0100
> "Matthew Wilcox (Oracle)" <willy@infradead.org> wrote:
>
> > 32-bit architectures which expect 8-byte alignment for 8-byte integers
> > and need 64-bit DMA addresses (arc, arm, mips, ppc) had their struct
> > page inadvertently expanded in 2019. When the dma_addr_t was added,
> > it forced the alignment of the union to 8 bytes, which inserted a 4 byte
> > gap between 'flags' and the union.
> >
> > We could fix this by telling the compiler to use a smaller alignment
> > for the dma_addr, but that seems a little fragile. Instead, move the
> > 'flags' into the union. That causes dma_addr to shift into the same
> > bits as 'mapping', so it would have to be cleared on free. To avoid
> > this, insert three words of padding and use the same bits as ->index
> > and ->private, neither of which have to be cleared on free.
> >
> > Fixes: c25fff7171be ("mm: add dma_addr_t to struct page")
> > Signed-off-by: Matthew Wilcox (Oracle) <willy@infradead.org>
> > ---
> > include/linux/mm_types.h | 38 ++++++++++++++++++++++++++------------
> > 1 file changed, 26 insertions(+), 12 deletions(-)
> >
> > diff --git a/include/linux/mm_types.h b/include/linux/mm_types.h
> > index 6613b26a8894..45c563e9b50e 100644
> > --- a/include/linux/mm_types.h
> > +++ b/include/linux/mm_types.h
> > @@ -68,16 +68,22 @@ struct mem_cgroup;
> > #endif
> >
> > struct page {
> > - unsigned long flags; /* Atomic flags, some possibly
> > - * updated asynchronously */
> > /*
> > - * Five words (20/40 bytes) are available in this union.
> > - * WARNING: bit 0 of the first word is used for PageTail(). That
> > - * means the other users of this union MUST NOT use the bit to
> > + * This union is six words (24 / 48 bytes) in size.
> > + * The first word is reserved for atomic flags, often updated
> > + * asynchronously. Use the PageFoo() macros to access it. Some
> > + * of the flags can be reused for your own purposes, but the
> > + * word as a whole often contains other information and overwriting
> > + * it will cause functions like page_zone() and page_node() to stop
> > + * working correctly.
> > + *
> > + * Bit 0 of the second word is used for PageTail(). That
> > + * means the other users of this union MUST leave the bit zero to
> > * avoid collision and false-positive PageTail().
> > */
> > union {
> > struct { /* Page cache and anonymous pages */
> > + unsigned long flags;
> > /**
> > * @lru: Pageout list, eg. active_list protected by
> > * lruvec->lru_lock. Sometimes used as a generic list
> > @@ -96,13 +102,14 @@ struct page {
> > unsigned long private;
> > };
> > struct { /* page_pool used by netstack */
> > - /**
> > - * @dma_addr: might require a 64-bit value even on
> > - * 32-bit architectures.
> > - */
> > - dma_addr_t dma_addr;
>
> The original intend of placing member @dma_addr here is that it overlap
> with @LRU (type struct list_head) which contains two pointers. Thus, in
> case of CONFIG_ARCH_DMA_ADDR_T_64BIT=y on 32-bit architectures it would
> use both pointers.
>
> Thinking more about this, this design is flawed as bit 0 of the first
> word is used for compound pages (see PageTail and @compound_head), is
> reserved. We knew DMA addresses were aligned, thus we though this
> satisfied that need. BUT for DMA_ADDR_T_64BIT=y on 32-bit arch the
> first word will contain the "upper" part of the DMA addr, which I don't
> think gives this guarantee.
>
> I guess, nobody are using this combination?!? I though we added this
> to satisfy TI (Texas Instrument) driver cpsw (code in
> drivers/net/ethernet/ti/cpsw*). Thus, I assumed it was in use?
It may be in use, but we've got away with it? It's relatively rare
that this is going to bite us. I think what has to happen is:
page is mapped to userspace
task calls get_user_page_fast(), loads the PTE
<preempted>
page is unmapped & freed
page is reallocated to the page_pool
page is DMA mapped to an address that happens to have that bit set
<first task resumes>
task looks for the compound_head() of that PTE, and attempts to bump
the refcount. *oops*
If it has happened, would it have turned into a bug report?
If we had seen such a bug report, would we have noticed it?
> > + unsigned long _pp_flags;
> > + unsigned long pp_magic;
> > + unsigned long xmi;
>
> Matteo notice, I think intent is we can store xdp_mem_info in @xmi.
Yep.
> > + unsigned long _pp_mapping_pad;
> > + dma_addr_t dma_addr; /* might be one or two words */
> > };
>
> Could you explain your intent here?
> I worry about @index.
>
> As I mentioned in other thread[1] netstack use page_is_pfmemalloc()
> (code copy-pasted below signature) which imply that the member @index
> have to be kept intact. In above, I'm unsure @index is untouched.
Argh, I read that piece of your message, and then promptly forgot about
it. I really don't like page_is_pfmemalloc() using the entirety of
page->index for this. How about we just do what slab does anyway
and use PageActive for page_is_pfmemalloc()?
Basically, we have three aligned dwords here. We can either alias with
@flags and the first word of @lru, or the second word of @lru and @mapping,
or @index and @private. @flags is a non-starter. If we use @mapping,
then you have to set it to NULL before you free it, and I'm not sure
how easy that will be for you. If that's trivial, then we could use
the layout:
unsigned long _pp_flags;
unsigned long pp_magic;
union {
dma_addr_t dma_addr; /* might be one or two words */
unsigned long _pp_align[2];
};
unsigned long pp_pfmemalloc;
unsigned long xmi;
^ permalink raw reply
* sysctl: setting key "net.core.bpf_jit_enable": Invalid argument
From: Paul Menzel @ 2021-04-11 11:09 UTC (permalink / raw)
To: Naveen N. Rao, Sandipan Das; +Cc: it+linux-bpf, netdev, bpf, linuxppc-dev
Dear Linux folks,
Related to * [CVE-2021-29154] Linux kernel incorrect computation of
branch displacements in BPF JIT compiler can be abused to execute
arbitrary code in Kernel mode* [1], on the POWER8 system IBM S822LC with
self-built Linux 5.12.0-rc5+, I am unable to disable `bpf_jit_enable`.
$ /sbin/sysctl net.core.bpf_jit_enable
net.core.bpf_jit_enable = 1
$ sudo /sbin/sysctl -w net.core.bpf_jit_enable=0
sysctl: setting key "net.core.bpf_jit_enable": Invalid argument
It works on an x86 with Debian sid/unstable and Linux 5.10.26-1.
Kind regards,
Paul
[1]: https://seclists.org/oss-sec/2021/q2/12
^ permalink raw reply
* Re: [PATCH 1/2] powerpc: syscalls: switch to generic syscalltbl.sh
From: Masahiro Yamada @ 2021-04-11 12:51 UTC (permalink / raw)
To: Michael Ellerman, Benjamin Herrenschmidt, Paul Mackerras,
linuxppc-dev
Cc: Arnd Bergmann, Sean Christopherson, Randy Dunlap,
Linux Kernel Mailing List, Nicholas Piggin, Geert Uytterhoeven,
Ben Gardon, Paolo Bonzini, Andrew Morton, Michal Suchanek
In-Reply-To: <20210301153019.362742-1-masahiroy@kernel.org>
Hi Michael,
On Tue, Mar 2, 2021 at 12:31 AM Masahiro Yamada <masahiroy@kernel.org> wrote:
>
> Many architectures duplicate similar shell scripts.
>
> This commit converts powerpc to use scripts/syscalltbl.sh. This also
> unifies syscall_table_32.h and syscall_table_c32.h.
>
> Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
Could you check this series?
Thanks.
Masahiro
> ---
>
> arch/powerpc/include/asm/Kbuild | 1 -
> arch/powerpc/kernel/syscalls/Makefile | 22 +++----------
> arch/powerpc/kernel/syscalls/syscalltbl.sh | 36 ---------------------
> arch/powerpc/kernel/systbl.S | 5 ++-
> arch/powerpc/platforms/cell/spu_callbacks.c | 2 +-
> 5 files changed, 10 insertions(+), 56 deletions(-)
> delete mode 100644 arch/powerpc/kernel/syscalls/syscalltbl.sh
>
> diff --git a/arch/powerpc/include/asm/Kbuild b/arch/powerpc/include/asm/Kbuild
> index e1f9b4ea1c53..bcf95ce0964f 100644
> --- a/arch/powerpc/include/asm/Kbuild
> +++ b/arch/powerpc/include/asm/Kbuild
> @@ -1,7 +1,6 @@
> # SPDX-License-Identifier: GPL-2.0
> generated-y += syscall_table_32.h
> generated-y += syscall_table_64.h
> -generated-y += syscall_table_c32.h
> generated-y += syscall_table_spu.h
> generic-y += export.h
> generic-y += kvm_types.h
> diff --git a/arch/powerpc/kernel/syscalls/Makefile b/arch/powerpc/kernel/syscalls/Makefile
> index 9e3be295dbba..df21c731c806 100644
> --- a/arch/powerpc/kernel/syscalls/Makefile
> +++ b/arch/powerpc/kernel/syscalls/Makefile
> @@ -7,7 +7,7 @@ _dummy := $(shell [ -d '$(uapi)' ] || mkdir -p '$(uapi)') \
>
> syscall := $(src)/syscall.tbl
> syshdr := $(srctree)/$(src)/syscallhdr.sh
> -systbl := $(srctree)/$(src)/syscalltbl.sh
> +systbl := $(srctree)/scripts/syscalltbl.sh
>
> quiet_cmd_syshdr = SYSHDR $@
> cmd_syshdr = $(CONFIG_SHELL) '$(syshdr)' '$<' '$@' \
> @@ -16,10 +16,7 @@ quiet_cmd_syshdr = SYSHDR $@
> '$(syshdr_offset_$(basetarget))'
>
> quiet_cmd_systbl = SYSTBL $@
> - cmd_systbl = $(CONFIG_SHELL) '$(systbl)' '$<' '$@' \
> - '$(systbl_abis_$(basetarget))' \
> - '$(systbl_abi_$(basetarget))' \
> - '$(systbl_offset_$(basetarget))'
> + cmd_systbl = $(CONFIG_SHELL) $(systbl) --abis $(abis) $< $@
>
> syshdr_abis_unistd_32 := common,nospu,32
> $(uapi)/unistd_32.h: $(syscall) $(syshdr) FORCE
> @@ -29,30 +26,21 @@ syshdr_abis_unistd_64 := common,nospu,64
> $(uapi)/unistd_64.h: $(syscall) $(syshdr) FORCE
> $(call if_changed,syshdr)
>
> -systbl_abis_syscall_table_32 := common,nospu,32
> -systbl_abi_syscall_table_32 := 32
> +$(kapi)/syscall_table_32.h: abis := common,nospu,32
> $(kapi)/syscall_table_32.h: $(syscall) $(systbl) FORCE
> $(call if_changed,systbl)
>
> -systbl_abis_syscall_table_64 := common,nospu,64
> -systbl_abi_syscall_table_64 := 64
> +$(kapi)/syscall_table_64.h: abis := common,nospu,64
> $(kapi)/syscall_table_64.h: $(syscall) $(systbl) FORCE
> $(call if_changed,systbl)
>
> -systbl_abis_syscall_table_c32 := common,nospu,32
> -systbl_abi_syscall_table_c32 := c32
> -$(kapi)/syscall_table_c32.h: $(syscall) $(systbl) FORCE
> - $(call if_changed,systbl)
> -
> -systbl_abis_syscall_table_spu := common,spu
> -systbl_abi_syscall_table_spu := spu
> +$(kapi)/syscall_table_spu.h: abis := common,spu
> $(kapi)/syscall_table_spu.h: $(syscall) $(systbl) FORCE
> $(call if_changed,systbl)
>
> uapisyshdr-y += unistd_32.h unistd_64.h
> kapisyshdr-y += syscall_table_32.h \
> syscall_table_64.h \
> - syscall_table_c32.h \
> syscall_table_spu.h
>
> uapisyshdr-y := $(addprefix $(uapi)/, $(uapisyshdr-y))
> diff --git a/arch/powerpc/kernel/syscalls/syscalltbl.sh b/arch/powerpc/kernel/syscalls/syscalltbl.sh
> deleted file mode 100644
> index f7393a7b18aa..000000000000
> --- a/arch/powerpc/kernel/syscalls/syscalltbl.sh
> +++ /dev/null
> @@ -1,36 +0,0 @@
> -#!/bin/sh
> -# SPDX-License-Identifier: GPL-2.0
> -
> -in="$1"
> -out="$2"
> -my_abis=`echo "($3)" | tr ',' '|'`
> -my_abi="$4"
> -offset="$5"
> -
> -emit() {
> - t_nxt="$1"
> - t_nr="$2"
> - t_entry="$3"
> -
> - while [ $t_nxt -lt $t_nr ]; do
> - printf "__SYSCALL(%s,sys_ni_syscall)\n" "${t_nxt}"
> - t_nxt=$((t_nxt+1))
> - done
> - printf "__SYSCALL(%s,%s)\n" "${t_nxt}" "${t_entry}"
> -}
> -
> -grep -E "^[0-9A-Fa-fXx]+[[:space:]]+${my_abis}" "$in" | sort -n | (
> - nxt=0
> - if [ -z "$offset" ]; then
> - offset=0
> - fi
> -
> - while read nr abi name entry compat ; do
> - if [ "$my_abi" = "c32" ] && [ ! -z "$compat" ]; then
> - emit $((nxt+offset)) $((nr+offset)) $compat
> - else
> - emit $((nxt+offset)) $((nr+offset)) $entry
> - fi
> - nxt=$((nr+1))
> - done
> -) > "$out"
> diff --git a/arch/powerpc/kernel/systbl.S b/arch/powerpc/kernel/systbl.S
> index d34276f3c495..cb3358886203 100644
> --- a/arch/powerpc/kernel/systbl.S
> +++ b/arch/powerpc/kernel/systbl.S
> @@ -21,6 +21,7 @@
> #define __SYSCALL(nr, entry) .long entry
> #endif
>
> +#define __SYSCALL_WITH_COMPAT(nr, native, compat) __SYSCALL(nr, native)
> .globl sys_call_table
> sys_call_table:
> #ifdef CONFIG_PPC64
> @@ -30,8 +31,10 @@ sys_call_table:
> #endif
>
> #ifdef CONFIG_COMPAT
> +#undef __SYSCALL_WITH_COMPAT
> +#define __SYSCALL_WITH_COMPAT(nr, native, compat) __SYSCALL(nr, compat)
> .globl compat_sys_call_table
> compat_sys_call_table:
> #define compat_sys_sigsuspend sys_sigsuspend
> -#include <asm/syscall_table_c32.h>
> +#include <asm/syscall_table_32.h>
> #endif
> diff --git a/arch/powerpc/platforms/cell/spu_callbacks.c b/arch/powerpc/platforms/cell/spu_callbacks.c
> index abdef9bcf432..fe0d8797a00a 100644
> --- a/arch/powerpc/platforms/cell/spu_callbacks.c
> +++ b/arch/powerpc/platforms/cell/spu_callbacks.c
> @@ -35,9 +35,9 @@
> */
>
> static void *spu_syscall_table[] = {
> +#define __SYSCALL_WITH_COMPAT(nr, entry, compat) __SYSCALL(nr, entry)
> #define __SYSCALL(nr, entry) [nr] = entry,
> #include <asm/syscall_table_spu.h>
> -#undef __SYSCALL
> };
>
> long spu_sys_callback(struct spu_syscall_block *s)
> --
> 2.27.0
>
--
Best Regards
Masahiro Yamada
^ permalink raw reply
* Re: [PATCH] ASoC: fsl_sai: Don't use devm_regmap_init_mmio_clk
From: Guenter Roeck @ 2021-04-11 14:41 UTC (permalink / raw)
To: Shengjiu Wang
Cc: alsa-devel, timur, Xiubo.Lee, linuxppc-dev, tiwai, lgirdwood,
perex, nicoleotsuka, broonie, festevam, linux-kernel
In-Reply-To: <1616141203-13344-1-git-send-email-shengjiu.wang@nxp.com>
On Fri, Mar 19, 2021 at 04:06:43PM +0800, Shengjiu Wang wrote:
> When there is power domain bind with bus clock,
>
> The call flow:
> devm_regmap_init_mmio_clk
> - clk_prepare()
> - clk_pm_runtime_get()
>
> cause the power domain of clock always be enabled after
> regmap_init(). which impact the power consumption.
>
> So use devm_regmap_init_mmio instead of
> devm_regmap_init_mmio_clk, then explicitly enable clock when
> using by pm_runtime_get(), if CONFIG_PM=n, then
> fsl_sai_runtime_resume will be explicitly called.
>
> Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
> Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
This patch results in a crash when running mcimx6ul-evk in qemu.
Reverting it fixes the problem.
Crash and bisect logs attached.
Guenter
---
[ 19.196778] 8<--- cut here ---
[ 19.197011] Unhandled fault: external abort on non-linefetch (0x808) at 0xd1588000
[ 19.197135] pgd = (ptrval)
[ 19.197203] [d1588000] *pgd=824da811, *pte=0202c653, *ppte=0202c453
[ 19.197764] Internal error: : 808 [#1] SMP ARM
[ 19.197953] Modules linked in:
[ 19.198108] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 5.12.0-rc6-next-20210409 #1
[ 19.198234] Hardware name: Freescale i.MX6 Ultralite (Device Tree)
[ 19.198354] PC is at regmap_mmio_write32le+0x24/0x2c
[ 19.198482] LR is at regmap_mmio_write32le+0x1c/0x2c
[ 19.198544] pc : [<c0965d6c>] lr : [<c0965d64>] psr: 60000093
[ 19.198611] sp : c20b5cf0 ip : 00000000 fp : c017a344
[ 19.198669] r10: c217c1b0 r9 : c20b4000 r8 : c26fcc00
[ 19.198729] r7 : 01000000 r6 : c26ff580 r5 : 00000000 r4 : 01000000
[ 19.198801] r3 : d1588000 r2 : 01000000 r1 : d1588000 r0 : c26ff580
[ 19.198896] Flags: nZCv IRQs off FIQs on Mode SVC_32 ISA ARM Segment none
[ 19.198982] Control: 10c5387d Table: 826bc06a DAC: 00000051
[ 19.199060] Register r0 information: slab kmalloc-64 start c26ff580 pointer offset 0 size 64
[ 19.199421] Register r1 information: 0-page vmalloc region starting at 0xd1588000 allocated at __devm_ioremap+0x90/0xa4
[ 19.199587] Register r2 information: non-paged memory
[ 19.199667] Register r3 information: 0-page vmalloc region starting at 0xd1588000 allocated at __devm_ioremap+0x90/0xa4
[ 19.199774] Register r4 information: non-paged memory
[ 19.199832] Register r5 information: NULL pointer
[ 19.199888] Register r6 information: slab kmalloc-64 start c26ff580 pointer offset 0 size 64
[ 19.199998] Register r7 information: non-paged memory
[ 19.200056] Register r8 information: slab kmalloc-1k start c26fcc00 pointer offset 0 size 1024
[ 19.200167] Register r9 information: non-slab/vmalloc memory
[ 19.200252] Register r10 information: slab kmalloc-1k start c217c000 pointer offset 432 size 1024
[ 19.200367] Register r11 information: non-slab/vmalloc memory
[ 19.200431] Register r12 information: NULL pointer
[ 19.200495] Process swapper/0 (pid: 1, stack limit = 0x(ptrval))
[ 19.200596] Stack: (0xc20b5cf0 to 0xc20b6000)
[ 19.200755] 5ce0: c26ff580 00000000 01000000 c0965f40
[ 19.200932] 5d00: c26fcc00 00000000 00000000 c095f3cc c20c0000 c26fcc00 00000000 01000000
[ 19.201096] 5d20: c269b840 00000000 c20b4000 c217c1b0 c017a344 c0961130 00000080 c217c010
[ 19.201259] 5d40: c26ff5c0 c0d21354 c217c010 c0946e24 00000000 c0946e24 c217c114 c094a894
[ 19.201420] 5d60: c217c010 c0946e24 c2173810 c217c114 c2173914 c20b4000 c217c1b0 c094a930
[ 19.201582] 5d80: c217c010 c0946e24 c2173810 c094a468 c20c0000 c20b4000 c094a6a0 60000013
[ 19.201744] 5da0: 00000002 cbdc8024 c217c114 5bdc6b72 60000013 60000013 c217c114 00000004
[ 19.201906] 5dc0: 00000002 cbdc8024 c20b4000 c269b880 00000000 c094a6b4 c269b840 c217c010
[ 19.202067] 5de0: c217c000 c0d2176c 00000000 00000000 00000000 00000000 c2176340 c21d5c00
[ 19.202228] 5e00: 00000000 6b6c636d 00000033 5bdc6b72 00000000 00000000 c217c010 c18d47fc
[ 19.202389] 5e20: c1f70c20 00000000 c18d47fc 00000000 00000000 c093f540 c217c010 c1f70c1c
[ 19.202551] 5e40: 00000000 c1f70c20 00000000 c093cdec c217c010 c18d47fc c18d47fc c20b4000
[ 19.202712] 5e60: 00000000 c166e854 c20af880 c093d0fc c217c010 00000000 c18d47fc c093d418
[ 19.202873] 5e80: 00000000 c18d47fc c217c010 c093d484 00000000 c18d47fc c093d420 c093aefc
[ 19.203035] 5ea0: c26fe980 c20ae2b0 c214be94 5bdc6b72 c20ae2e4 c18d47fc c26fe980 00000000
[ 19.203196] 5ec0: c187bcf8 c093c0b8 c14db3fc c1661678 c18f4c20 c18d47fc c1661678 c18f4c20
[ 19.203357] 5ee0: c17093d0 c093e1e4 c20b4000 c1661678 c18f4c20 c01022b0 00000000 00000000
[ 19.203533] 5f00: c20af8ec 00000000 c17e0b10 c0f39294 c17093d0 ffffffff c14a1cb8 c20b4000
[ 19.203696] 5f20: c18f4c20 c17093d0 c15644e0 c18ff000 c166e854 000001c6 00000000 c01af994
[ 19.203858] 5f40: 00000000 5bdc6b72 c168dca8 00000007 c166e874 c15644e0 c18ff000 c166e854
[ 19.204019] 5f60: c20af880 c16010a0 00000006 00000006 00000000 c16003e8 c0f46080 000001c6
[ 19.204180] 5f80: c17097d0 00000000 c0f3a784 00000000 00000000 00000000 00000000 00000000
[ 19.204342] 5fa0: 00000000 c0f3a78c 00000000 c010013c 00000000 00000000 00000000 00000000
[ 19.204503] 5fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
[ 19.204663] 5fe0: 00000000 00000000 00000000 00000000 00000013 00000000 00000000 00000000
[ 19.204828] [<c0965d6c>] (regmap_mmio_write32le) from [<c0965f40>] (regmap_mmio_write+0x3c/0x54)
[ 19.204947] [<c0965f40>] (regmap_mmio_write) from [<c095f3cc>] (_regmap_write+0x4c/0x1f4)
[ 19.205034] [<c095f3cc>] (_regmap_write) from [<c0961130>] (regmap_write+0x3c/0x60)
[ 19.205114] [<c0961130>] (regmap_write) from [<c0d21354>] (fsl_sai_runtime_resume+0x9c/0x1ec)
[ 19.205206] [<c0d21354>] (fsl_sai_runtime_resume) from [<c094a894>] (__rpm_callback+0xb4/0x130)
[ 19.205297] [<c094a894>] (__rpm_callback) from [<c094a930>] (rpm_callback+0x20/0x80)
[ 19.205379] [<c094a930>] (rpm_callback) from [<c094a468>] (rpm_resume+0x604/0x7ec)
[ 19.205459] [<c094a468>] (rpm_resume) from [<c094a6b4>] (__pm_runtime_resume+0x64/0xa4)
[ 19.205543] [<c094a6b4>] (__pm_runtime_resume) from [<c0d2176c>] (fsl_sai_probe+0x2c8/0x674)
[ 19.205630] [<c0d2176c>] (fsl_sai_probe) from [<c093f540>] (platform_probe+0x58/0xb8)
[ 19.205694] [<c093f540>] (platform_probe) from [<c093cdec>] (really_probe+0xec/0x398)
[ 19.205765] [<c093cdec>] (really_probe) from [<c093d0fc>] (driver_probe_device+0x64/0xc0)
[ 19.205854] [<c093d0fc>] (driver_probe_device) from [<c093d418>] (device_driver_attach+0x58/0x60)
[ 19.205944] [<c093d418>] (device_driver_attach) from [<c093d484>] (__driver_attach+0x64/0xdc)
[ 19.206028] [<c093d484>] (__driver_attach) from [<c093aefc>] (bus_for_each_dev+0x78/0xb8)
[ 19.206113] [<c093aefc>] (bus_for_each_dev) from [<c093c0b8>] (bus_add_driver+0x150/0x1dc)
[ 19.206200] [<c093c0b8>] (bus_add_driver) from [<c093e1e4>] (driver_register+0x74/0x108)
[ 19.206285] [<c093e1e4>] (driver_register) from [<c01022b0>] (do_one_initcall+0x80/0x3a8)
[ 19.206374] [<c01022b0>] (do_one_initcall) from [<c16010a0>] (kernel_init_freeable+0x158/0x1f4)
[ 19.206466] [<c16010a0>] (kernel_init_freeable) from [<c0f3a78c>] (kernel_init+0x8/0x11c)
[ 19.206556] [<c0f3a78c>] (kernel_init) from [<c010013c>] (ret_from_fork+0x14/0x38)
[ 19.206653] Exception stack(0xc20b5fb0 to 0xc20b5ff8)
[ 19.206749] 5fa0: 00000000 00000000 00000000 00000000
[ 19.206916] 5fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
[ 19.207063] 5fe0: 00000000 00000000 00000000 00000000 00000013 00000000
[ 19.207290] Code: ee073f9a ebdeca40 e5963000 e0831005 (e5814000)
[ 19.207813] ---[ end trace 4c72393d5e30d6c1 ]---
---
# bad: [e99d8a8495175df8cb8b739f8cf9b0fc9d0cd3b5] Add linux-next specific files for 20210409
# good: [e49d033bddf5b565044e2abe4241353959bc9120] Linux 5.12-rc6
git bisect start 'HEAD' 'v5.12-rc6'
# good: [24c5f79572740c1744a7ec2e9e21b541acab6de3] Merge remote-tracking branch 'crypto/master'
git bisect good 24c5f79572740c1744a7ec2e9e21b541acab6de3
# bad: [4b90473874c7b6af320b9815f82ac305fd8807f7] Merge remote-tracking branch 'ftrace/for-next'
git bisect bad 4b90473874c7b6af320b9815f82ac305fd8807f7
# good: [9cf3382276b26848891c7e072db0a774fadd10e4] Merge remote-tracking branch 'sound/for-next'
git bisect good 9cf3382276b26848891c7e072db0a774fadd10e4
# bad: [f8d16164c586548d7ccedc058ca9ae547e0cebbe] Merge remote-tracking branch 'mmc/next'
git bisect bad f8d16164c586548d7ccedc058ca9ae547e0cebbe
# bad: [c7c19ec098b862a688291f5a1101f7de6e4b0a6c] ASoC: Intel: kbl: Add MST route change to kbl machine drivers
git bisect bad c7c19ec098b862a688291f5a1101f7de6e4b0a6c
# good: [1db19c151819dea7a0dc4d888250d25abaf229ca] ASoC: soc-pcm: fixup dpcm_be_dai_startup() user count
git bisect good 1db19c151819dea7a0dc4d888250d25abaf229ca
# bad: [f89c0a87b4066fbb0dc6f8039b211bd79a9ab663] Merge tag 'ib-mfd-extcon-v5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd into asoc-5.13
git bisect bad f89c0a87b4066fbb0dc6f8039b211bd79a9ab663
# good: [a2cc1568dc50020a807c94bd14a053dd54e9c35e] ASoC: tscs454: remove useless test on PLL disable
git bisect good a2cc1568dc50020a807c94bd14a053dd54e9c35e
# good: [cb11f79b4af65005584880eb408f9748c32661d0] ASoC: soc-pcm: indicate error message at soc_pcm_hw_params()
git bisect good cb11f79b4af65005584880eb408f9748c32661d0
# good: [60adbd8fbf486214f4ae1946e61df69c3867e20b] ASoC: don't indicate error message for snd_soc_[pcm_]component_xxx()
git bisect good 60adbd8fbf486214f4ae1946e61df69c3867e20b
# bad: [dfb81e3b5f47aa0ea5e4832eeb720bc22f07d0c1] ASoC: SOF: Intel: hda: drop display power on/off in D0i3 flows
git bisect bad dfb81e3b5f47aa0ea5e4832eeb720bc22f07d0c1
# good: [7e71b48f9e27e437ca523432ea285c2585a539dc] ASoC: amd: Add support for RT5682 codec in machine driver
git bisect good 7e71b48f9e27e437ca523432ea285c2585a539dc
# bad: [b951b51e2ca4d37dc9781e14d8a49d2f2b7e715b] ASoC: SOF: add a helper to get topology configured mclk
git bisect bad b951b51e2ca4d37dc9781e14d8a49d2f2b7e715b
# bad: [2277e7e36b4b8c27eb8d2fb33a20440bc800c2d7] ASoC: fsl_sai: Don't use devm_regmap_init_mmio_clk
git bisect bad 2277e7e36b4b8c27eb8d2fb33a20440bc800c2d7
# first bad commit: [2277e7e36b4b8c27eb8d2fb33a20440bc800c2d7] ASoC: fsl_sai: Don't use devm_regmap_init_mmio_clk
^ permalink raw reply
* Re: [PATCH v6 4/9] csky: locks: Optimize coding convention
From: Guo Ren @ 2021-04-11 16:01 UTC (permalink / raw)
To: Guo Ren
Cc: linux-arch, linux-xtensa, Guo Ren, Arnd Bergmann, Peter Zijlstra,
Linux Kernel Mailing List, linux-csky, openrisc, sparclinux,
linux-riscv, linuxppc-dev
In-Reply-To: <1617201040-83905-5-git-send-email-guoren@kernel.org>
On Wed, Mar 31, 2021 at 10:32 PM <guoren@kernel.org> wrote:
>
> From: Guo Ren <guoren@linux.alibaba.com>
>
> - Using smp_cond_load_acquire in arch_spin_lock by Peter's
> advice.
> - Using __smp_acquire_fence in arch_spin_trylock
> - Using smp_store_release in arch_spin_unlock
>
> All above are just coding conventions and won't affect the
> function.
>
> TODO in smp_cond_load_acquire for architecture:
> - current csky only has:
> lr.w val, <p0>
> sc.w <p0>. val2
> (Any other stores to p0 will let sc.w failed)
>
> - But smp_cond_load_acquire need:
> lr.w val, <p0>
> wfe
> (Any stores to p0 will send the event to let wfe retired)
>
> Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
> Link: https://lore.kernel.org/linux-riscv/CAAhSdy1JHLUFwu7RuCaQ+RUWRBks2KsDva7EpRt8--4ZfofSUQ@mail.gmail.com/T/#m13adac285b7f51f4f879a5d6b65753ecb1a7524e
> Cc: Peter Zijlstra <peterz@infradead.org>
> Cc: Arnd Bergmann <arnd@arndb.de>
> ---
> arch/csky/include/asm/spinlock.h | 11 ++++-------
> 1 file changed, 4 insertions(+), 7 deletions(-)
>
> diff --git a/arch/csky/include/asm/spinlock.h b/arch/csky/include/asm/spinlock.h
> index 69f5aa249c5f..69677167977a 100644
> --- a/arch/csky/include/asm/spinlock.h
> +++ b/arch/csky/include/asm/spinlock.h
> @@ -26,10 +26,8 @@ static inline void arch_spin_lock(arch_spinlock_t *lock)
> : "r"(p), "r"(ticket_next)
> : "cc");
>
> - while (lockval.tickets.next != lockval.tickets.owner)
> - lockval.tickets.owner = READ_ONCE(lock->tickets.owner);
> -
> - smp_mb();
> + smp_cond_load_acquire(&lock->tickets.owner,
> + VAL == lockval.tickets.next);
It's wrong, we should determine lockval before next read.
Fixup:
diff --git a/arch/csky/include/asm/spinlock.h b/arch/csky/include/asm/spinlock.h
index fe98ad8ece51..2be627ceb9df 100644
--- a/arch/csky/include/asm/spinlock.h
+++ b/arch/csky/include/asm/spinlock.h
@@ -27,7 +27,8 @@ static inline void arch_spin_lock(arch_spinlock_t *lock)
: "r"(p), "r"(ticket_next)
: "cc");
- smp_cond_load_acquire(&lock->tickets.owner,
+ if (lockval.owner != lockval.tickets.next)
+ smp_cond_load_acquire(&lock->tickets.owner,
VAL == lockval.tickets.next);
> }
>
> static inline int arch_spin_trylock(arch_spinlock_t *lock)
> @@ -55,15 +53,14 @@ static inline int arch_spin_trylock(arch_spinlock_t *lock)
> } while (!res);
>
> if (!contended)
> - smp_mb();
> + __smp_acquire_fence();
>
> return !contended;
> }
>
> static inline void arch_spin_unlock(arch_spinlock_t *lock)
> {
> - smp_mb();
> - WRITE_ONCE(lock->tickets.owner, lock->tickets.owner + 1);
> + smp_store_release(&lock->tickets.owner, lock->tickets.owner + 1);
> }
>
> static inline int arch_spin_value_unlocked(arch_spinlock_t lock)
> --
> 2.17.1
>
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
^ permalink raw reply related
* Re: [PATCH v6 3/9] riscv: locks: Introduce ticket-based spinlock implementation
From: Guo Ren @ 2021-04-11 16:02 UTC (permalink / raw)
To: Guo Ren
Cc: linux-arch, linux-xtensa, Guo Ren, Arnd Bergmann, Peter Zijlstra,
Anup Patel, Linux Kernel Mailing List, linux-csky, openrisc,
sparclinux, linux-riscv, linuxppc-dev
In-Reply-To: <1617201040-83905-4-git-send-email-guoren@kernel.org>
On Wed, Mar 31, 2021 at 10:32 PM <guoren@kernel.org> wrote:
>
> From: Guo Ren <guoren@linux.alibaba.com>
>
> This patch introduces a ticket lock implementation for riscv, along the
> same lines as the implementation for arch/arm & arch/csky.
>
> We still use qspinlock as default.
>
> Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
> Cc: Peter Zijlstra <peterz@infradead.org>
> Cc: Anup Patel <anup@brainfault.org>
> Cc: Arnd Bergmann <arnd@arndb.de>
> ---
> arch/riscv/Kconfig | 7 ++-
> arch/riscv/include/asm/spinlock.h | 84 +++++++++++++++++++++++++
> arch/riscv/include/asm/spinlock_types.h | 17 +++++
> 3 files changed, 107 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index 67cc65ba1ea1..34d0276f01d5 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -34,7 +34,7 @@ config RISCV
> select ARCH_WANT_FRAME_POINTERS
> select ARCH_WANT_HUGE_PMD_SHARE if 64BIT
> select ARCH_USE_QUEUED_RWLOCKS
> - select ARCH_USE_QUEUED_SPINLOCKS
> + select ARCH_USE_QUEUED_SPINLOCKS if !RISCV_TICKET_LOCK
> select ARCH_USE_QUEUED_SPINLOCKS_XCHG32
> select CLONE_BACKWARDS
> select CLINT_TIMER if !MMU
> @@ -344,6 +344,11 @@ config NEED_PER_CPU_EMBED_FIRST_CHUNK
> def_bool y
> depends on NUMA
>
> +config RISCV_TICKET_LOCK
> + bool "Ticket-based spin-locking"
> + help
> + Say Y here to use ticket-based spin-locking.
> +
> config RISCV_ISA_C
> bool "Emit compressed instructions when building Linux"
> default y
> diff --git a/arch/riscv/include/asm/spinlock.h b/arch/riscv/include/asm/spinlock.h
> index a557de67a425..90b7eaa950cf 100644
> --- a/arch/riscv/include/asm/spinlock.h
> +++ b/arch/riscv/include/asm/spinlock.h
> @@ -7,7 +7,91 @@
> #ifndef _ASM_RISCV_SPINLOCK_H
> #define _ASM_RISCV_SPINLOCK_H
>
> +#ifdef CONFIG_RISCV_TICKET_LOCK
> +#ifdef CONFIG_32BIT
> +#define __ASM_SLLIW "slli\t"
> +#define __ASM_SRLIW "srli\t"
> +#else
> +#define __ASM_SLLIW "slliw\t"
> +#define __ASM_SRLIW "srliw\t"
> +#endif
> +
> +/*
> + * Ticket-based spin-locking.
> + */
> +static inline void arch_spin_lock(arch_spinlock_t *lock)
> +{
> + arch_spinlock_t lockval;
> + u32 tmp;
> +
> + asm volatile (
> + "1: lr.w %0, %2 \n"
> + " mv %1, %0 \n"
> + " addw %0, %0, %3 \n"
> + " sc.w %0, %0, %2 \n"
> + " bnez %0, 1b \n"
> + : "=&r" (tmp), "=&r" (lockval), "+A" (lock->lock)
> + : "r" (1 << TICKET_NEXT)
> + : "memory");
> +
> + smp_cond_load_acquire(&lock->tickets.owner,
> + VAL == lockval.tickets.next);
It's wrong, blew is fixup:
diff --git a/arch/csky/include/asm/spinlock.h b/arch/csky/include/asm/spinlock.h
index fe98ad8ece51..2be627ceb9df 100644
--- a/arch/csky/include/asm/spinlock.h
+++ b/arch/csky/include/asm/spinlock.h
@@ -27,7 +27,8 @@ static inline void arch_spin_lock(arch_spinlock_t *lock)
: "r"(p), "r"(ticket_next)
: "cc");
- smp_cond_load_acquire(&lock->tickets.owner,
+ if (lockval.owner != lockval.tickets.next)
+ smp_cond_load_acquire(&lock->tickets.owner,
VAL == lockval.tickets.next);
> +}
> +
> +static inline int arch_spin_trylock(arch_spinlock_t *lock)
> +{
> + u32 tmp, contended, res;
> +
> + do {
> + asm volatile (
> + " lr.w %0, %3 \n"
> + __ASM_SRLIW "%1, %0, %5 \n"
> + __ASM_SLLIW "%2, %0, %5 \n"
> + " or %1, %2, %1 \n"
> + " li %2, 0 \n"
> + " sub %1, %1, %0 \n"
> + " bnez %1, 1f \n"
> + " addw %0, %0, %4 \n"
> + " sc.w %2, %0, %3 \n"
> + "1: \n"
> + : "=&r" (tmp), "=&r" (contended), "=&r" (res),
> + "+A" (lock->lock)
> + : "r" (1 << TICKET_NEXT), "I" (TICKET_NEXT)
> + : "memory");
> + } while (res);
> +
> + if (!contended)
> + __atomic_acquire_fence();
> +
> + return !contended;
> +}
> +
> +static inline void arch_spin_unlock(arch_spinlock_t *lock)
> +{
> + smp_store_release(&lock->tickets.owner, lock->tickets.owner + 1);
> +}
> +
> +static inline int arch_spin_value_unlocked(arch_spinlock_t lock)
> +{
> + return lock.tickets.owner == lock.tickets.next;
> +}
> +
> +static inline int arch_spin_is_locked(arch_spinlock_t *lock)
> +{
> + return !arch_spin_value_unlocked(READ_ONCE(*lock));
> +}
> +
> +static inline int arch_spin_is_contended(arch_spinlock_t *lock)
> +{
> + struct __raw_tickets tickets = READ_ONCE(lock->tickets);
> +
> + return (tickets.next - tickets.owner) > 1;
> +}
> +#define arch_spin_is_contended arch_spin_is_contended
> +#else /* CONFIG_RISCV_TICKET_LOCK */
> #include <asm/qspinlock.h>
> +#endif /* CONFIG_RISCV_TICKET_LOCK */
> +
> #include <asm/qrwlock.h>
>
> #endif /* _ASM_RISCV_SPINLOCK_H */
> diff --git a/arch/riscv/include/asm/spinlock_types.h b/arch/riscv/include/asm/spinlock_types.h
> index d033a973f287..afbb19841d0f 100644
> --- a/arch/riscv/include/asm/spinlock_types.h
> +++ b/arch/riscv/include/asm/spinlock_types.h
> @@ -10,7 +10,24 @@
> # error "please don't include this file directly"
> #endif
>
> +#ifdef CONFIG_RISCV_TICKET_LOCK
> +#define TICKET_NEXT 16
> +
> +typedef struct {
> + union {
> + u32 lock;
> + struct __raw_tickets {
> + /* little endian */
> + u16 owner;
> + u16 next;
> + } tickets;
> + };
> +} arch_spinlock_t;
> +
> +#define __ARCH_SPIN_LOCK_UNLOCKED { { 0 } }
> +#else
> #include <asm-generic/qspinlock_types.h>
> +#endif
> #include <asm-generic/qrwlock_types.h>
>
> #endif /* _ASM_RISCV_SPINLOCK_TYPES_H */
> --
> 2.17.1
>
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
^ permalink raw reply related
* Re: sysctl: setting key "net.core.bpf_jit_enable": Invalid argument
From: Christophe Leroy @ 2021-04-11 16:23 UTC (permalink / raw)
To: Paul Menzel, Naveen N. Rao, Sandipan Das
Cc: it+linux-bpf, netdev, bpf, linuxppc-dev
In-Reply-To: <412d88b2-fa9a-149e-6f6e-3cfbce9edef0@molgen.mpg.de>
Le 11/04/2021 à 13:09, Paul Menzel a écrit :
> Dear Linux folks,
>
>
> Related to * [CVE-2021-29154] Linux kernel incorrect computation of branch displacements in BPF JIT
> compiler can be abused to execute arbitrary code in Kernel mode* [1], on the POWER8 system IBM
> S822LC with self-built Linux 5.12.0-rc5+, I am unable to disable `bpf_jit_enable`.
>
> $ /sbin/sysctl net.core.bpf_jit_enable
> net.core.bpf_jit_enable = 1
> $ sudo /sbin/sysctl -w net.core.bpf_jit_enable=0
> sysctl: setting key "net.core.bpf_jit_enable": Invalid argument
>
> It works on an x86 with Debian sid/unstable and Linux 5.10.26-1.
Maybe you have selected CONFIG_BPF_JIT_ALWAYS_ON in your self-built kernel ?
config BPF_JIT_ALWAYS_ON
bool "Permanently enable BPF JIT and remove BPF interpreter"
depends on BPF_SYSCALL && HAVE_EBPF_JIT && BPF_JIT
help
Enables BPF JIT and removes BPF interpreter to avoid
speculative execution of BPF instructions by the interpreter
Christophe
^ permalink raw reply
* [PATCH] powerpc/signal32: Fix build failure with CONFIG_SPE
From: Christophe Leroy @ 2021-04-11 16:39 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman, linux
Cc: linuxppc-dev, linux-kernel
Add missing fault exit label in unsafe_copy_from_user() in order to
avoid following build failure with CONFIG_SPE
CC arch/powerpc/kernel/signal_32.o
arch/powerpc/kernel/signal_32.c: In function 'restore_user_regs':
arch/powerpc/kernel/signal_32.c:565:36: error: macro "unsafe_copy_from_user" requires 4 arguments, but only 3 given
565 | ELF_NEVRREG * sizeof(u32));
| ^
In file included from ./include/linux/uaccess.h:11,
from ./include/linux/sched/task.h:11,
from ./include/linux/sched/signal.h:9,
from ./include/linux/rcuwait.h:6,
from ./include/linux/percpu-rwsem.h:7,
from ./include/linux/fs.h:33,
from ./include/linux/huge_mm.h:8,
from ./include/linux/mm.h:707,
from arch/powerpc/kernel/signal_32.c:17:
./arch/powerpc/include/asm/uaccess.h:428: note: macro "unsafe_copy_from_user" defined here
428 | #define unsafe_copy_from_user(d, s, l, e) \
|
arch/powerpc/kernel/signal_32.c:564:3: error: 'unsafe_copy_from_user' undeclared (first use in this function); did you mean 'raw_copy_from_user'?
564 | unsafe_copy_from_user(current->thread.evr, &sr->mc_vregs,
| ^~~~~~~~~~~~~~~~~~~~~
| raw_copy_from_user
arch/powerpc/kernel/signal_32.c:564:3: note: each undeclared identifier is reported only once for each function it appears in
make[3]: *** [arch/powerpc/kernel/signal_32.o] Error 1
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Fixes: 627b72bee84d ("powerpc/signal32: Convert restore_[tm]_user_regs() to user access block")
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Guenter Roeck <linux@roeck-us.net>
---
arch/powerpc/kernel/signal_32.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/signal_32.c b/arch/powerpc/kernel/signal_32.c
index 23fdb364b511..d489ccea2ab3 100644
--- a/arch/powerpc/kernel/signal_32.c
+++ b/arch/powerpc/kernel/signal_32.c
@@ -562,7 +562,7 @@ static long restore_user_regs(struct pt_regs *regs,
if (msr & MSR_SPE) {
/* restore spe registers from the stack */
unsafe_copy_from_user(current->thread.evr, &sr->mc_vregs,
- ELF_NEVRREG * sizeof(u32));
+ ELF_NEVRREG * sizeof(u32), failed);
current->thread.used_spe = true;
} else if (current->thread.used_spe)
memset(current->thread.evr, 0, ELF_NEVRREG * sizeof(u32));
--
2.25.0
^ permalink raw reply related
* Re: [PATCH v6 3/9] riscv: locks: Introduce ticket-based spinlock implementation
From: Guo Ren @ 2021-04-11 16:51 UTC (permalink / raw)
To: Guo Ren
Cc: linux-arch, linux-xtensa, Guo Ren, Arnd Bergmann, Peter Zijlstra,
Anup Patel, Linux Kernel Mailing List, linux-csky, openrisc,
sparclinux, linux-riscv, linuxppc-dev
In-Reply-To: <CAJF2gTQRGWetpvvtXOn8_KzH8EQwL6VG02AoKBUWTkE69Xn6Kg@mail.gmail.com>
On Mon, Apr 12, 2021 at 12:02 AM Guo Ren <guoren@kernel.org> wrote:
>
> On Wed, Mar 31, 2021 at 10:32 PM <guoren@kernel.org> wrote:
> >
> > From: Guo Ren <guoren@linux.alibaba.com>
> >
> > This patch introduces a ticket lock implementation for riscv, along the
> > same lines as the implementation for arch/arm & arch/csky.
> >
> > We still use qspinlock as default.
> >
> > Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
> > Cc: Peter Zijlstra <peterz@infradead.org>
> > Cc: Anup Patel <anup@brainfault.org>
> > Cc: Arnd Bergmann <arnd@arndb.de>
> > ---
> > arch/riscv/Kconfig | 7 ++-
> > arch/riscv/include/asm/spinlock.h | 84 +++++++++++++++++++++++++
> > arch/riscv/include/asm/spinlock_types.h | 17 +++++
> > 3 files changed, 107 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > index 67cc65ba1ea1..34d0276f01d5 100644
> > --- a/arch/riscv/Kconfig
> > +++ b/arch/riscv/Kconfig
> > @@ -34,7 +34,7 @@ config RISCV
> > select ARCH_WANT_FRAME_POINTERS
> > select ARCH_WANT_HUGE_PMD_SHARE if 64BIT
> > select ARCH_USE_QUEUED_RWLOCKS
> > - select ARCH_USE_QUEUED_SPINLOCKS
> > + select ARCH_USE_QUEUED_SPINLOCKS if !RISCV_TICKET_LOCK
> > select ARCH_USE_QUEUED_SPINLOCKS_XCHG32
> > select CLONE_BACKWARDS
> > select CLINT_TIMER if !MMU
> > @@ -344,6 +344,11 @@ config NEED_PER_CPU_EMBED_FIRST_CHUNK
> > def_bool y
> > depends on NUMA
> >
> > +config RISCV_TICKET_LOCK
> > + bool "Ticket-based spin-locking"
> > + help
> > + Say Y here to use ticket-based spin-locking.
> > +
> > config RISCV_ISA_C
> > bool "Emit compressed instructions when building Linux"
> > default y
> > diff --git a/arch/riscv/include/asm/spinlock.h b/arch/riscv/include/asm/spinlock.h
> > index a557de67a425..90b7eaa950cf 100644
> > --- a/arch/riscv/include/asm/spinlock.h
> > +++ b/arch/riscv/include/asm/spinlock.h
> > @@ -7,7 +7,91 @@
> > #ifndef _ASM_RISCV_SPINLOCK_H
> > #define _ASM_RISCV_SPINLOCK_H
> >
> > +#ifdef CONFIG_RISCV_TICKET_LOCK
> > +#ifdef CONFIG_32BIT
> > +#define __ASM_SLLIW "slli\t"
> > +#define __ASM_SRLIW "srli\t"
> > +#else
> > +#define __ASM_SLLIW "slliw\t"
> > +#define __ASM_SRLIW "srliw\t"
> > +#endif
> > +
> > +/*
> > + * Ticket-based spin-locking.
> > + */
> > +static inline void arch_spin_lock(arch_spinlock_t *lock)
> > +{
> > + arch_spinlock_t lockval;
> > + u32 tmp;
> > +
> > + asm volatile (
> > + "1: lr.w %0, %2 \n"
> > + " mv %1, %0 \n"
> > + " addw %0, %0, %3 \n"
> > + " sc.w %0, %0, %2 \n"
> > + " bnez %0, 1b \n"
> > + : "=&r" (tmp), "=&r" (lockval), "+A" (lock->lock)
> > + : "r" (1 << TICKET_NEXT)
> > + : "memory");
> > +
> > + smp_cond_load_acquire(&lock->tickets.owner,
> > + VAL == lockval.tickets.next);
> It's wrong, blew is fixup:
>
> diff --git a/arch/csky/include/asm/spinlock.h b/arch/csky/include/asm/spinlock.h
> index fe98ad8ece51..2be627ceb9df 100644
> --- a/arch/csky/include/asm/spinlock.h
> +++ b/arch/csky/include/asm/spinlock.h
> @@ -27,7 +27,8 @@ static inline void arch_spin_lock(arch_spinlock_t *lock)
> : "r"(p), "r"(ticket_next)
> : "cc");
>
> - smp_cond_load_acquire(&lock->tickets.owner,
> + if (lockval.owner != lockval.tickets.next)
> + smp_cond_load_acquire(&lock->tickets.owner,
> VAL == lockval.tickets.next);
eh... plus __smp_acquire_fence:
if (lockval.owner != lockval.tickets.next)
smp_cond_load_acquire(&lock->tickets.owner,
VAL == lockval.tickets.next);
else
__smp_acquire_fence();
> > +}
> > +
> > +static inline int arch_spin_trylock(arch_spinlock_t *lock)
> > +{
> > + u32 tmp, contended, res;
> > +
> > + do {
> > + asm volatile (
> > + " lr.w %0, %3 \n"
> > + __ASM_SRLIW "%1, %0, %5 \n"
> > + __ASM_SLLIW "%2, %0, %5 \n"
> > + " or %1, %2, %1 \n"
> > + " li %2, 0 \n"
> > + " sub %1, %1, %0 \n"
> > + " bnez %1, 1f \n"
> > + " addw %0, %0, %4 \n"
> > + " sc.w %2, %0, %3 \n"
> > + "1: \n"
> > + : "=&r" (tmp), "=&r" (contended), "=&r" (res),
> > + "+A" (lock->lock)
> > + : "r" (1 << TICKET_NEXT), "I" (TICKET_NEXT)
> > + : "memory");
> > + } while (res);
> > +
> > + if (!contended)
> > + __atomic_acquire_fence();
> > +
> > + return !contended;
> > +}
> > +
> > +static inline void arch_spin_unlock(arch_spinlock_t *lock)
> > +{
> > + smp_store_release(&lock->tickets.owner, lock->tickets.owner + 1);
> > +}
> > +
> > +static inline int arch_spin_value_unlocked(arch_spinlock_t lock)
> > +{
> > + return lock.tickets.owner == lock.tickets.next;
> > +}
> > +
> > +static inline int arch_spin_is_locked(arch_spinlock_t *lock)
> > +{
> > + return !arch_spin_value_unlocked(READ_ONCE(*lock));
> > +}
> > +
> > +static inline int arch_spin_is_contended(arch_spinlock_t *lock)
> > +{
> > + struct __raw_tickets tickets = READ_ONCE(lock->tickets);
> > +
> > + return (tickets.next - tickets.owner) > 1;
> > +}
> > +#define arch_spin_is_contended arch_spin_is_contended
> > +#else /* CONFIG_RISCV_TICKET_LOCK */
> > #include <asm/qspinlock.h>
> > +#endif /* CONFIG_RISCV_TICKET_LOCK */
> > +
> > #include <asm/qrwlock.h>
> >
> > #endif /* _ASM_RISCV_SPINLOCK_H */
> > diff --git a/arch/riscv/include/asm/spinlock_types.h b/arch/riscv/include/asm/spinlock_types.h
> > index d033a973f287..afbb19841d0f 100644
> > --- a/arch/riscv/include/asm/spinlock_types.h
> > +++ b/arch/riscv/include/asm/spinlock_types.h
> > @@ -10,7 +10,24 @@
> > # error "please don't include this file directly"
> > #endif
> >
> > +#ifdef CONFIG_RISCV_TICKET_LOCK
> > +#define TICKET_NEXT 16
> > +
> > +typedef struct {
> > + union {
> > + u32 lock;
> > + struct __raw_tickets {
> > + /* little endian */
> > + u16 owner;
> > + u16 next;
> > + } tickets;
> > + };
> > +} arch_spinlock_t;
> > +
> > +#define __ARCH_SPIN_LOCK_UNLOCKED { { 0 } }
> > +#else
> > #include <asm-generic/qspinlock_types.h>
> > +#endif
> > #include <asm-generic/qrwlock_types.h>
> >
> > #endif /* _ASM_RISCV_SPINLOCK_TYPES_H */
> > --
> > 2.17.1
> >
>
>
> --
> Best Regards
> Guo Ren
>
> ML: https://lore.kernel.org/linux-csky/
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
^ permalink raw reply
* Re: sysctl: setting key "net.core.bpf_jit_enable": Invalid argument
From: Paul Menzel @ 2021-04-11 18:39 UTC (permalink / raw)
To: Christophe Leroy, Naveen N. Rao, Sandipan Das
Cc: it+linux-bpf, netdev, bpf, linuxppc-dev
In-Reply-To: <d880c38c-e410-0b69-0897-9cbf4b759045@csgroup.eu>
Dear Christophe,
Am 11.04.21 um 18:23 schrieb Christophe Leroy:
> Le 11/04/2021 à 13:09, Paul Menzel a écrit :
>> Related to * [CVE-2021-29154] Linux kernel incorrect computation of
>> branch displacements in BPF JIT compiler can be abused to execute
>> arbitrary code in Kernel mode* [1], on the POWER8 system IBM S822LC
>> with self-built Linux 5.12.0-rc5+, I am unable to disable
>> `bpf_jit_enable`.
>>
>> $ /sbin/sysctl net.core.bpf_jit_enable
>> net.core.bpf_jit_enable = 1
>> $ sudo /sbin/sysctl -w net.core.bpf_jit_enable=0
>> sysctl: setting key "net.core.bpf_jit_enable": Invalid argument
>>
>> It works on an x86 with Debian sid/unstable and Linux 5.10.26-1.
>
> Maybe you have selected CONFIG_BPF_JIT_ALWAYS_ON in your self-built
> kernel ?
>
> config BPF_JIT_ALWAYS_ON
> bool "Permanently enable BPF JIT and remove BPF interpreter"
> depends on BPF_SYSCALL && HAVE_EBPF_JIT && BPF_JIT
> help
> Enables BPF JIT and removes BPF interpreter to avoid
> speculative execution of BPF instructions by the interpreter
Thank you. Indeed. In contrast to Debian, Ubuntu’s Linux configuration
selects that option, and I copied that.
$ grep _BPF_JIT /boot/config-5.8.0-49-generic
/boot/config-5.8.0-49-generic:CONFIG_BPF_JIT_ALWAYS_ON=y
/boot/config-5.8.0-49-generic:CONFIG_BPF_JIT_DEFAULT_ON=y
/boot/config-5.8.0-49-generic:CONFIG_BPF_JIT=y
I wonder, if there is a way to better integrate that option into
`/proc/sys`, so it’s clear, that it’s always enabled.
Kind regards,
Paul
^ permalink raw reply
* Re: Bogus struct page layout on 32-bit
From: Matthew Wilcox @ 2021-04-11 22:35 UTC (permalink / raw)
To: Arnd Bergmann
Cc: kbuild-all, kernel test robot, clang-built-linux,
Jesper Dangaard Brouer, Linux Kernel Mailing List, Linux-MM,
Paul Mackerras, Linux FS-devel Mailing List, linuxppc-dev,
David S. Miller, Linux ARM
In-Reply-To: <CAK8P3a3uEGaEN-p06vFP+jwbFt3P=Bx4=aRN+kUyB4PcFPxLRg@mail.gmail.com>
On Sat, Apr 10, 2021 at 09:10:47PM +0200, Arnd Bergmann wrote:
> On Sat, Apr 10, 2021 at 4:44 AM Matthew Wilcox <willy@infradead.org> wrote:
> > + dma_addr_t dma_addr __packed;
> > };
> > struct { /* slab, slob and slub */
> > union {
> >
> > but I don't know if GCC is smart enough to realise that dma_addr is now
> > on an 8 byte boundary and it can use a normal instruction to access it,
> > or whether it'll do something daft like use byte loads to access it.
> >
> > We could also do:
> >
> > + dma_addr_t dma_addr __packed __aligned(sizeof(void *));
> >
> > and I see pahole, at least sees this correctly:
> >
> > struct {
> > long unsigned int _page_pool_pad; /* 4 4 */
> > dma_addr_t dma_addr __attribute__((__aligned__(4))); /* 8 8 */
> > } __attribute__((__packed__)) __attribute__((__aligned__(4)));
> >
> > This presumably affects any 32-bit architecture with a 64-bit phys_addr_t
> > / dma_addr_t. Advice, please?
>
> I've tried out what gcc would make of this: https://godbolt.org/z/aTEbxxbG3
>
> struct page {
> short a;
> struct {
> short b;
> long long c __attribute__((packed, aligned(2)));
> } __attribute__((packed));
> } __attribute__((aligned(8)));
>
> In this structure, 'c' is clearly aligned to eight bytes, and gcc does
> realize that
> it is safe to use the 'ldrd' instruction for 32-bit arm, which is forbidden on
> struct members with less than 4 byte alignment. However, it also complains
> that passing a pointer to 'c' into a function that expects a 'long long' is not
> allowed because alignof(c) is only '2' here.
>
> (I used 'short' here because I having a 64-bit member misaligned by four
> bytes wouldn't make a difference to the instructions on Arm, or any other
> 32-bit architecture I can think of, regardless of the ABI requirements).
So ... we could do this:
+++ b/include/linux/types.h
@@ -140,7 +140,7 @@ typedef u64 blkcnt_t;
* so they don't care about the size of the actual bus addresses.
*/
#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
-typedef u64 dma_addr_t;
+typedef u64 __attribute__((aligned(sizeof(void *)))) dma_addr_t;
#else
typedef u32 dma_addr_t;
#endif
but I'm a little scared that this might have unintended consequences.
And Jesper points out that a big-endian 64-bit dma_addr_t can impersonate
a PageTail page, and we should solve that problem while we're at it.
So I don't think we should do this, but thought I should mention it as
a possibility.
^ permalink raw reply
* Re: [PATCH 02/16] powerpc/vas: Make VAS API powerpc platform independent
From: Haren Myneni @ 2021-04-12 0:29 UTC (permalink / raw)
To: Christophe Leroy, linuxppc-dev, linux-crypto, mpe, herbert,
npiggin
In-Reply-To: <1804692b-f9d4-964d-bbe4-cb809dad5ee8@csgroup.eu>
Christophe,
Thanks for your comments. Please see below for my responses.
On Sun, 2021-04-11 at 10:49 +0200, Christophe Leroy wrote:
>
> Le 11/04/2021 à 02:31, Haren Myneni a écrit :
> > Using the same /dev/crypto/nx-gzip interface for both powerNV and
> > pseries. So this patcb moves VAS API to powerpc platform indepedent
> > directory. The actual functionality is not changed in this patch.
>
> This patch seems to do a lot more than moving VAS API to independent
> directory. A more detailed
> description would help.
Actually the functionality is not changed in this patch. Moved the
common interface code (needed for both powerNV and powerVM platforms)
to arch/powerpc/kernel and added hooks to invoke powerNV specific
functions (underline code is not changed). I will add some more
description.
>
> And it is not something defined in the powerpc architecture I think,
> so it should
> remain in some common platform related directory.
>
> > Signed-off-by: Haren Myneni <haren@linux.ibm.com>
> > ---
> > arch/powerpc/Kconfig | 15 +++++
> > arch/powerpc/include/asm/vas.h | 22 ++++++-
> > arch/powerpc/kernel/Makefile | 1 +
> > .../{platforms/powernv => kernel}/vas-api.c | 64 ++++++++++--
> > ------
> > arch/powerpc/platforms/powernv/Kconfig | 14 ----
> > arch/powerpc/platforms/powernv/Makefile | 2 +-
> > arch/powerpc/platforms/powernv/vas-window.c | 66
> > +++++++++++++++++++
> > 7 files changed, 140 insertions(+), 44 deletions(-)
> > rename arch/powerpc/{platforms/powernv => kernel}/vas-api.c (83%)
> >
> > diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
> > index 386ae12d8523..7aa1fbf7c1dc 100644
> > --- a/arch/powerpc/Kconfig
> > +++ b/arch/powerpc/Kconfig
> > @@ -478,6 +478,21 @@ config PPC_UV
> >
> > If unsure, say "N".
> >
> > +config PPC_VAS
> > + bool "IBM Virtual Accelerator Switchboard (VAS)"
> > + depends on PPC_POWERNV && PPC_64K_PAGES
> > + default y
> > + help
> > + This enables support for IBM Virtual Accelerator Switchboard
> > (VAS).
>
> IIUC is a functionnality in a coprocessor of some IBM processors.
> Something similar in principle to
> the communication coprocessors we find in Freescale processors.
>
> It is not a generic functionnality part of the powerpc architecture,
> I don't think this belongs to
> arch/powerpc/Kconfig
>
> I think it should go in arch/powerpc/platform/Kconfig
>
> Or maybe in drivers/soc/ibm/ ?
VAS (Virtual Accelerator Switchboard) is on powerpc chip which allows
userspace / kernel to communicate to accelerators (Right now supports
only Next (NX) accelerator). VAS can also provide other SW
functionalities such as fast thread wakeup, fast memory copy (using
copy/paste instructions). So introduced this VAS API to support any
accelerator and other SW functionalities in future.
VAS is introduced on P9 and will be available in all future powerpc
chips.
I will move config changes to arch/powerpc/platform/Kconfig but thought
easy to look / manage Kconfig changes if they are in same directory.
Thanks
Haren
>
>
> > +
> > + VAS allows accelerators in co-processors like NX-GZIP and NX-
> > 842
> > + to be accessible to kernel subsystems and user processes.
> > + VAS adapters are found in POWER9 and later based systems.
> > + The user mode NX-GZIP support is added on P9 for powerNV and
> > on
> > + P10 for powerVM.
> > +
> > + If unsure, say "N".
> > +
> > config LD_HEAD_STUB_CATCH
> > bool "Reserve 256 bytes to cope with linker stubs in HEAD text"
> > if EXPERT
> > depends on PPC64
> > diff --git a/arch/powerpc/include/asm/vas.h
> > b/arch/powerpc/include/asm/vas.h
> > index 41f73fae7ab8..6bbade60d8f4 100644
> > --- a/arch/powerpc/include/asm/vas.h
> > +++ b/arch/powerpc/include/asm/vas.h
> > @@ -5,6 +5,8 @@
> >
> > #ifndef _ASM_POWERPC_VAS_H
> > #define _ASM_POWERPC_VAS_H
> > +#include <uapi/asm/vas-api.h>
> > +
> >
> > struct vas_window;
> >
> > @@ -48,6 +50,16 @@ enum vas_cop_type {
> > VAS_COP_TYPE_MAX,
> > };
> >
> > +/*
> > + * User space window operations used for powernv and powerVM
> > + */
> > +struct vas_user_win_ops {
> > + struct vas_window * (*open_win)(struct vas_tx_win_open_attr *,
> > + enum vas_cop_type);
> > + u64 (*paste_addr)(void *);
> > + int (*close_win)(void *);
> > +};
> > +
> > /*
> > * Receive window attributes specified by the (in-kernel) owner
> > of window.
> > */
> > @@ -161,6 +173,9 @@ int vas_copy_crb(void *crb, int offset);
> > * assumed to be true for NX windows.
> > */
> > int vas_paste_crb(struct vas_window *win, int offset, bool re);
> > +int vas_register_api_powernv(struct module *mod, enum vas_cop_type
> > cop_type,
> > + const char *name);
> > +void vas_unregister_api_powernv(void);
> >
> > /*
> > * Register / unregister coprocessor type to VAS API which will
> > be exported
> > @@ -170,8 +185,9 @@ int vas_paste_crb(struct vas_window *win, int
> > offset, bool re);
> > * Only NX GZIP coprocessor type is supported now, but this API
> > can be
> > * used for others in future.
> > */
> > -int vas_register_api_powernv(struct module *mod, enum vas_cop_type
> > cop_type,
> > - const char *name);
> > -void vas_unregister_api_powernv(void);
> > +int vas_register_coproc_api(struct module *mod, enum vas_cop_type
> > cop_type,
> > + const char *name,
> > + struct vas_user_win_ops *vops);
> > +void vas_unregister_coproc_api(void);
> >
> > #endif /* __ASM_POWERPC_VAS_H */
> > diff --git a/arch/powerpc/kernel/Makefile
> > b/arch/powerpc/kernel/Makefile
> > index 6084fa499aa3..205d8f12bd36 100644
> > --- a/arch/powerpc/kernel/Makefile
> > +++ b/arch/powerpc/kernel/Makefile
> > @@ -118,6 +118,7 @@ obj-$(CONFIG_PPC_UDBG_16550) +=
> > legacy_serial.o udbg_16550.o
> > obj-$(CONFIG_STACKTRACE) += stacktrace.o
> > obj-$(CONFIG_SWIOTLB) += dma-swiotlb.o
> > obj-$(CONFIG_ARCH_HAS_DMA_SET_MASK) += dma-mask.o
> > +obj-$(CONFIG_PPC_VAS) += vas-api.o
> >
> > pci64-$(CONFIG_PPC64) += pci_dn.o pci-hotplug.o isa-
> > bridge.o
> > obj-$(CONFIG_PCI) += pci_$(BITS).o $(pci64-y) \
> > diff --git a/arch/powerpc/platforms/powernv/vas-api.c
> > b/arch/powerpc/kernel/vas-api.c
> > similarity index 83%
> > rename from arch/powerpc/platforms/powernv/vas-api.c
> > rename to arch/powerpc/kernel/vas-api.c
> > index 72d8ce39e56c..05d7b99acf41 100644
> > --- a/arch/powerpc/platforms/powernv/vas-api.c
> > +++ b/arch/powerpc/kernel/vas-api.c
> > @@ -4,15 +4,20 @@
> > * Copyright (C) 2019 Haren Myneni, IBM Corp
> > */
> >
> > +#include <linux/module.h>
> > #include <linux/kernel.h>
> > #include <linux/device.h>
> > #include <linux/cdev.h>
> > #include <linux/fs.h>
> > #include <linux/slab.h>
> > #include <linux/uaccess.h>
> > +#include <linux/kthread.h>
> > +#include <linux/sched/signal.h>
> > +#include <linux/sched/mm.h>
> > +#include <linux/mmu_context.h>
> > #include <asm/vas.h>
> > +#include <asm/icswx.h>
> > #include <uapi/asm/vas-api.h>
> > -#include "vas.h"
> >
> > /*
> > * The driver creates the device node that can be used as
> > follows:
> > @@ -42,6 +47,7 @@ static struct coproc_dev {
> > dev_t devt;
> > struct class *class;
> > enum vas_cop_type cop_type;
> > + struct vas_user_win_ops *vops;
> > } coproc_device;
> >
> > struct coproc_instance {
> > @@ -72,11 +78,10 @@ static int coproc_open(struct inode *inode,
> > struct file *fp)
> > static int coproc_ioc_tx_win_open(struct file *fp, unsigned long
> > arg)
> > {
> > void __user *uptr = (void __user *)arg;
> > - struct vas_tx_win_attr txattr = {};
> > struct vas_tx_win_open_attr uattr;
> > struct coproc_instance *cp_inst;
> > struct vas_window *txwin;
> > - int rc, vasid;
> > + int rc;
> >
> > cp_inst = fp->private_data;
> >
> > @@ -93,27 +98,20 @@ static int coproc_ioc_tx_win_open(struct file
> > *fp, unsigned long arg)
> > }
> >
> > if (uattr.version != 1) {
> > - pr_err("Invalid version\n");
> > + pr_err("Invalid window open API version\n");
> > return -EINVAL;
> > }
> >
> > - vasid = uattr.vas_id;
> > -
> > - vas_init_tx_win_attr(&txattr, cp_inst->coproc->cop_type);
> > -
> > - txattr.lpid = mfspr(SPRN_LPID);
> > - txattr.pidr = mfspr(SPRN_PID);
> > - txattr.user_win = true;
> > - txattr.rsvd_txbuf_count = false;
> > - txattr.pswid = false;
> > -
> > - pr_devel("Pid %d: Opening txwin, PIDR %ld\n", txattr.pidr,
> > - mfspr(SPRN_PID));
> > + if (!cp_inst->coproc->vops && !cp_inst->coproc->vops->open_win)
> > {
> > + pr_err("VAS API is not registered\n");
> > + return -EACCES;
> > + }
> >
> > - txwin = vas_tx_win_open(vasid, cp_inst->coproc->cop_type,
> > &txattr);
> > + txwin = cp_inst->coproc->vops->open_win(&uattr,
> > + cp_inst->coproc->cop_type);
> > if (IS_ERR(txwin)) {
> > - pr_err("%s() vas_tx_win_open() failed, %ld\n",
> > __func__,
> > - PTR_ERR(txwin));
> > + pr_err("%s() VAS window open failed, %ld\n", __func__,
> > + PTR_ERR(txwin));
> > return PTR_ERR(txwin);
> > }
> >
> > @@ -125,9 +123,14 @@ static int coproc_ioc_tx_win_open(struct file
> > *fp, unsigned long arg)
> > static int coproc_release(struct inode *inode, struct file *fp)
> > {
> > struct coproc_instance *cp_inst = fp->private_data;
> > + int rc = 0;
> >
> > if (cp_inst->txwin) {
> > - vas_win_close(cp_inst->txwin);
> > + if (cp_inst->coproc->vops && cp_inst->coproc->vops-
> > >close_win) {
> > + rc = cp_inst->coproc->vops->close_win(cp_inst-
> > >txwin);
> > + if (rc)
> > + return rc;
> > + }
> > cp_inst->txwin = NULL;
> > }
> >
> > @@ -168,7 +171,17 @@ static int coproc_mmap(struct file *fp, struct
> > vm_area_struct *vma)
> > return -EINVAL;
> > }
> >
> > - vas_win_paste_addr(txwin, &paste_addr, NULL);
> > + if (!cp_inst->coproc->vops && !cp_inst->coproc->vops-
> > >paste_addr) {
> > + pr_err("%s(): VAS API is not registered\n", __func__);
> > + return -EACCES;
> > + }
> > +
> > + paste_addr = cp_inst->coproc->vops->paste_addr(txwin);
> > + if (!paste_addr) {
> > + pr_err("%s(): Window paste address failed\n",
> > __func__);
> > + return -EINVAL;
> > + }
> > +
> > pfn = paste_addr >> PAGE_SHIFT;
> >
> > /* flags, page_prot from cxl_mmap(), except we want cachable */
> > @@ -207,8 +220,8 @@ static struct file_operations coproc_fops = {
> > * Supporting only nx-gzip coprocessor type now, but this API
> > code
> > * extended to other coprocessor types later.
> > */
> > -int vas_register_api_powernv(struct module *mod, enum vas_cop_type
> > cop_type,
> > - const char *name)
> > +int vas_register_coproc_api(struct module *mod, enum vas_cop_type
> > cop_type,
> > + const char *name, struct vas_user_win_ops
> > *vops)
> > {
> > int rc = -EINVAL;
> > dev_t devno;
> > @@ -230,6 +243,7 @@ int vas_register_api_powernv(struct module
> > *mod, enum vas_cop_type cop_type,
> > }
> > coproc_device.class->devnode = coproc_devnode;
> > coproc_device.cop_type = cop_type;
> > + coproc_device.vops = vops;
> >
> > coproc_fops.owner = mod;
> > cdev_init(&coproc_device.cdev, &coproc_fops);
> > @@ -262,9 +276,8 @@ int vas_register_api_powernv(struct module
> > *mod, enum vas_cop_type cop_type,
> > unregister_chrdev_region(coproc_device.devt, 1);
> > return rc;
> > }
> > -EXPORT_SYMBOL_GPL(vas_register_api_powernv);
> >
> > -void vas_unregister_api_powernv(void)
> > +void vas_unregister_coproc_api(void)
> > {
> > dev_t devno;
> >
> > @@ -275,4 +288,3 @@ void vas_unregister_api_powernv(void)
> > class_destroy(coproc_device.class);
> > unregister_chrdev_region(coproc_device.devt, 1);
> > }
> > -EXPORT_SYMBOL_GPL(vas_unregister_api_powernv);
> > diff --git a/arch/powerpc/platforms/powernv/Kconfig
> > b/arch/powerpc/platforms/powernv/Kconfig
> > index 619b093a0657..043eefbbdd28 100644
> > --- a/arch/powerpc/platforms/powernv/Kconfig
> > +++ b/arch/powerpc/platforms/powernv/Kconfig
> > @@ -33,20 +33,6 @@ config PPC_MEMTRACE
> > Enabling this option allows for runtime allocation of memory
> > (RAM)
> > for hardware tracing.
> >
> > -config PPC_VAS
> > - bool "IBM Virtual Accelerator Switchboard (VAS)"
> > - depends on PPC_POWERNV && PPC_64K_PAGES
> > - default y
> > - help
> > - This enables support for IBM Virtual Accelerator Switchboard
> > (VAS).
> > -
> > - VAS allows accelerators in co-processors like NX-GZIP and NX-
> > 842
> > - to be accessible to kernel subsystems and user processes.
> > -
> > - VAS adapters are found in POWER9 based systems.
> > -
> > - If unsure, say N.
> > -
> > config SCOM_DEBUGFS
> > bool "Expose SCOM controllers via debugfs"
> > depends on DEBUG_FS
> > diff --git a/arch/powerpc/platforms/powernv/Makefile
> > b/arch/powerpc/platforms/powernv/Makefile
> > index 2eb6ae150d1f..c747a1f1d25b 100644
> > --- a/arch/powerpc/platforms/powernv/Makefile
> > +++ b/arch/powerpc/platforms/powernv/Makefile
> > @@ -18,7 +18,7 @@ obj-$(CONFIG_MEMORY_FAILURE) += opal-memory-
> > errors.o
> > obj-$(CONFIG_OPAL_PRD) += opal-prd.o
> > obj-$(CONFIG_PERF_EVENTS) += opal-imc.o
> > obj-$(CONFIG_PPC_MEMTRACE) += memtrace.o
> > -obj-$(CONFIG_PPC_VAS) += vas.o vas-window.o vas-debug.o vas-
> > fault.o vas-api.o
> > +obj-$(CONFIG_PPC_VAS) += vas.o vas-window.o vas-debug.o vas-
> > fault.o
> > obj-$(CONFIG_OCXL_BASE) += ocxl.o
> > obj-$(CONFIG_SCOM_DEBUGFS) += opal-xscom.o
> > obj-$(CONFIG_PPC_SECURE_BOOT) += opal-secvar.o
> > diff --git a/arch/powerpc/platforms/powernv/vas-window.c
> > b/arch/powerpc/platforms/powernv/vas-window.c
> > index 5f5fe63a3d1c..b973dd574b47 100644
> > --- a/arch/powerpc/platforms/powernv/vas-window.c
> > +++ b/arch/powerpc/platforms/powernv/vas-window.c
> > @@ -16,6 +16,8 @@
> > #include <linux/mmu_context.h>
> > #include <asm/switch_to.h>
> > #include <asm/ppc-opcode.h>
> > +#include <asm/vas.h>
> > +#include <uapi/asm/vas-api.h>
> > #include "vas.h"
> > #include "copy-paste.h"
> >
> > @@ -1441,3 +1443,67 @@ struct vas_window
> > *vas_pswid_to_window(struct vas_instance *vinst,
> >
> > return window;
> > }
> > +
> > +static struct vas_window *vas_user_win_open(struct
> > vas_tx_win_open_attr *uattr,
> > + enum vas_cop_type cop_type)
> > +{
> > + struct vas_tx_win_attr txattr = {};
> > +
> > + vas_init_tx_win_attr(&txattr, cop_type);
> > +
> > + txattr.lpid = mfspr(SPRN_LPID);
> > + txattr.pidr = mfspr(SPRN_PID);
> > + txattr.user_win = true;
> > + txattr.rsvd_txbuf_count = false;
> > + txattr.pswid = false;
> > +
> > + pr_devel("Pid %d: Opening txwin, PIDR %ld\n", txattr.pidr,
> > + mfspr(SPRN_PID));
> > +
> > + return vas_tx_win_open(uattr->vas_id, cop_type, &txattr);
> > +}
> > +
> > +static u64 vas_user_win_paste_addr(void *addr)
> > +{
> > + u64 paste_addr;
> > +
> > + vas_win_paste_addr((struct vas_window *)addr, &paste_addr,
> > NULL);
> > +
> > + return paste_addr;
> > +}
> > +
> > +static int vas_user_win_close(void *addr)
> > +{
> > + struct vas_window *txwin = addr;
> > +
> > + vas_win_close(txwin);
> > +
> > + return 0;
> > +}
> > +
> > +static struct vas_user_win_ops vops = {
> > + .open_win = vas_user_win_open,
> > + .paste_addr = vas_user_win_paste_addr,
> > + .close_win = vas_user_win_close,
> > +};
> > +
> > +/*
> > + * Supporting only nx-gzip coprocessor type now, but this API code
> > + * extended to other coprocessor types later.
> > + */
> > +int vas_register_api_powernv(struct module *mod, enum vas_cop_type
> > cop_type,
> > + const char *name)
> > +{
> > + int rc;
> > +
> > + rc = vas_register_coproc_api(mod, cop_type, name, &vops);
> > +
> > + return rc;
> > +}
> > +EXPORT_SYMBOL_GPL(vas_register_api_powernv);
> > +
> > +void vas_unregister_api_powernv(void)
> > +{
> > + vas_unregister_coproc_api();
> > +}
> > +EXPORT_SYMBOL_GPL(vas_unregister_api_powernv);
> >
^ permalink raw reply
* Re: [PATCH 1/1] mm: Fix struct page layout on 32-bit systems
From: Matthew Wilcox @ 2021-04-12 1:15 UTC (permalink / raw)
To: Jesper Dangaard Brouer
Cc: Arnd Bergmann, Grygorii Strashko, Ivan Khoronzhuk, netdev,
Ilias Apalodimas, linux-mips, linux-kernel, linux-mm,
Matteo Croce, linuxppc-dev, Christoph Hellwig, linux-arm-kernel
In-Reply-To: <20210411103318.GC2531743@casper.infradead.org>
On Sun, Apr 11, 2021 at 11:33:18AM +0100, Matthew Wilcox wrote:
> Basically, we have three aligned dwords here. We can either alias with
> @flags and the first word of @lru, or the second word of @lru and @mapping,
> or @index and @private. @flags is a non-starter. If we use @mapping,
> then you have to set it to NULL before you free it, and I'm not sure
> how easy that will be for you. If that's trivial, then we could use
> the layout:
>
> unsigned long _pp_flags;
> unsigned long pp_magic;
> union {
> dma_addr_t dma_addr; /* might be one or two words */
> unsigned long _pp_align[2];
> };
> unsigned long pp_pfmemalloc;
> unsigned long xmi;
I forgot about the munmap path. That calls zap_page_range() which calls
set_page_dirty() which calls page_mapping(). If we use page->mapping,
that's going to get interpreted as an address_space pointer.
*sigh*. Foiled at every turn.
I'm kind of inclined towards using two (or more) bits for PageSlab as
we discussed here:
https://lore.kernel.org/linux-mm/01000163efe179fe-d6270c58-eaba-482f-a6bd-334667250ef7-000000@email.amazonses.com/
so we have PageKAlloc that's true for PageSlab, PagePool, PageDMAPool,
PageVMalloc, PageFrag and maybe a few other kernel-internal allocations.
(see also here:)
https://lore.kernel.org/linux-mm/20180518194519.3820-18-willy@infradead.org/
^ permalink raw reply
* [PATCH v1 01/12] KVM: PPC: Book3S HV P9: Restore host CTRL SPR after guest exit
From: Nicholas Piggin @ 2021-04-12 1:48 UTC (permalink / raw)
To: kvm-ppc; +Cc: linuxppc-dev, Nicholas Piggin
In-Reply-To: <20210412014845.1517916-1-npiggin@gmail.com>
The host CTRL (runlatch) value is not restored after guest exit. The
host CTRL should always be 1 except in CPU idle code, so this can result
in the host running with runlatch clear, and potentially switching to
a different vCPU which then runs with runlatch clear as well.
This has little effect on P9 machines, CTRL is only responsible for some
PMU counter logic in the host and so other than corner cases of software
relying on that, or explicitly reading the runlatch value (Linux does
not appear to be affected but it's possible non-Linux guests could be),
there should be no execution correctness problem, though it could be
used as a covert channel between guests.
There may be microcontrollers, firmware or monitoring tools that sample
the runlatch value out-of-band, however since the register is writable
by guests, these values would (should) not be relied upon for correct
operation of the host, so suboptimal performance or incorrect reporting
should be the worst problem.
Fixes: 95a6432ce9038 ("KVM: PPC: Book3S HV: Streamlined guest entry/exit path on P9 for radix guests")
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kvm/book3s_hv.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
index 13bad6bf4c95..208a053c9adf 100644
--- a/arch/powerpc/kvm/book3s_hv.c
+++ b/arch/powerpc/kvm/book3s_hv.c
@@ -3728,7 +3728,10 @@ static int kvmhv_p9_guest_entry(struct kvm_vcpu *vcpu, u64 time_limit,
vcpu->arch.dec_expires = dec + tb;
vcpu->cpu = -1;
vcpu->arch.thread_cpu = -1;
+ /* Save guest CTRL register, set runlatch to 1 */
vcpu->arch.ctrl = mfspr(SPRN_CTRLF);
+ if (!(vcpu->arch.ctrl & 1))
+ mtspr(SPRN_CTRLT, vcpu->arch.ctrl | 1);
vcpu->arch.iamr = mfspr(SPRN_IAMR);
vcpu->arch.pspb = mfspr(SPRN_PSPB);
--
2.23.0
^ permalink raw reply related
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox