* Re: [PATCH v5 5/9] powerpc/mm/book3s64: Update tlb flush routines to take a page walk cache flush argument
From: Guenter Roeck @ 2021-05-15 16:35 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: npiggin, linux-mm, kaleshsingh, joel, akpm, linuxppc-dev
In-Reply-To: <20210422054323.150993-6-aneesh.kumar@linux.ibm.com>
On Thu, Apr 22, 2021 at 11:13:19AM +0530, Aneesh Kumar K.V wrote:
> No functional change in this patch
>
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
> ---
> .../include/asm/book3s/64/tlbflush-radix.h | 19 +++++++-----
> arch/powerpc/include/asm/book3s/64/tlbflush.h | 23 ++++++++++++---
> arch/powerpc/mm/book3s64/radix_hugetlbpage.c | 4 +--
> arch/powerpc/mm/book3s64/radix_tlb.c | 29 +++++++------------
> 4 files changed, 42 insertions(+), 33 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h b/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h
> index 8b33601cdb9d..171441a43b35 100644
> --- a/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h
> +++ b/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h
> @@ -56,15 +56,18 @@ static inline void radix__flush_all_lpid_guest(unsigned int lpid)
> }
> #endif
>
> -extern void radix__flush_hugetlb_tlb_range(struct vm_area_struct *vma,
> - unsigned long start, unsigned long end);
> -extern void radix__flush_tlb_range_psize(struct mm_struct *mm, unsigned long start,
> - unsigned long end, int psize);
> -extern void radix__flush_pmd_tlb_range(struct vm_area_struct *vma,
> - unsigned long start, unsigned long end);
> -extern void radix__flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
> +void radix__flush_hugetlb_tlb_range(struct vm_area_struct *vma,
> + unsigned long start, unsigned long end,
> + bool flush_pwc);
> +void radix__flush_pmd_tlb_range(struct vm_area_struct *vma,
> + unsigned long start, unsigned long end,
> + bool flush_pwc);
> +void radix__flush_tlb_pwc_range_psize(struct mm_struct *mm, unsigned long start,
> + unsigned long end, int psize, bool flush_pwc);
> +void radix__flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
> unsigned long end);
> -extern void radix__flush_tlb_kernel_range(unsigned long start, unsigned long end);
> +void radix__flush_tlb_kernel_range(unsigned long start, unsigned long end);
> +
>
> extern void radix__local_flush_tlb_mm(struct mm_struct *mm);
> extern void radix__local_flush_all_mm(struct mm_struct *mm);
> diff --git a/arch/powerpc/include/asm/book3s/64/tlbflush.h b/arch/powerpc/include/asm/book3s/64/tlbflush.h
> index 215973b4cb26..f9f8a3a264f7 100644
> --- a/arch/powerpc/include/asm/book3s/64/tlbflush.h
> +++ b/arch/powerpc/include/asm/book3s/64/tlbflush.h
> @@ -45,13 +45,30 @@ static inline void tlbiel_all_lpid(bool radix)
> hash__tlbiel_all(TLB_INVAL_SCOPE_LPID);
> }
>
> +static inline void flush_pmd_tlb_pwc_range(struct vm_area_struct *vma,
^^^^
> + unsigned long start,
> + unsigned long end,
> + bool flush_pwc)
> +{
> + if (radix_enabled())
> + return radix__flush_pmd_tlb_range(vma, start, end, flush_pwc);
> + return hash__flush_tlb_range(vma, start, end);
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
> +}
>
> #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE
> static inline void flush_pmd_tlb_range(struct vm_area_struct *vma,
^^^^
> unsigned long start, unsigned long end)
> +{
> + return flush_pmd_tlb_pwc_range(vma, start, end, false);
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Doesn't that cause build warnings/errors all over the place ?
Guenter
^ permalink raw reply
* Re: [PATCH v5 5/9] powerpc/mm/book3s64: Update tlb flush routines to take a page walk cache flush argument
From: Andrew Morton @ 2021-05-15 20:41 UTC (permalink / raw)
To: Guenter Roeck
Cc: Aneesh Kumar K.V, npiggin, linux-mm, kaleshsingh, joel,
linuxppc-dev
In-Reply-To: <20210515163525.GA1106462@roeck-us.net>
On Sat, 15 May 2021 09:35:25 -0700 Guenter Roeck <linux@roeck-us.net> wrote:
> >
> > #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE
> > static inline void flush_pmd_tlb_range(struct vm_area_struct *vma,
> ^^^^
> > unsigned long start, unsigned long end)
> > +{
> > + return flush_pmd_tlb_pwc_range(vma, start, end, false);
> ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
>
> Doesn't that cause build warnings/errors all over the place ?
It will, thanks. I queued a fix.
^ permalink raw reply
* Re: [PATCH] powerpc/interrupts: Fix kuep_unlock() call
From: Michael Ellerman @ 2021-05-15 22:43 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman,
Christophe Leroy
Cc: linuxppc-dev, linux-kernel
In-Reply-To: <b831e54a2579db24fbef836ed415588ce2b3e825.1620312573.git.christophe.leroy@csgroup.eu>
On Thu, 6 May 2021 14:49:45 +0000 (UTC), Christophe Leroy wrote:
> Same as kuap_user_restore(), kuep_unlock() has to be called when
> really returning to user, that is in interrupt_exit_user_prepare(),
> not in interrupt_exit_prepare().
Applied to powerpc/fixes.
[1/1] powerpc/interrupts: Fix kuep_unlock() call
https://git.kernel.org/powerpc/c/a78339698ab1f43435fbe67fcd6de8f4f6eb9eec
cheers
^ permalink raw reply
* Re: [PATCH] powerpc/legacy_serial: Fix UBSAN: array-index-out-of-bounds
From: Michael Ellerman @ 2021-05-15 22:43 UTC (permalink / raw)
To: pmenzel, Benjamin Herrenschmidt, Christophe Leroy, Paul Mackerras,
Michael Ellerman
Cc: linuxppc-dev, linux-kernel
In-Reply-To: <d5e3c8e66bad3725d7d48d0e45c4b7eb7c02631d.1620455671.git.christophe.leroy@csgroup.eu>
On Sat, 8 May 2021 06:36:21 +0000 (UTC), Christophe Leroy wrote:
> UBSAN complains when a pointer is calculated with invalid
> 'legacy_serial_console' index, allthough the index is verified
> before dereferencing the pointer.
>
> Fix it by checking 'legacy_serial_console' validity before
> calculating pointers.
Applied to powerpc/fixes.
[1/1] powerpc/legacy_serial: Fix UBSAN: array-index-out-of-bounds
https://git.kernel.org/powerpc/c/63970f3c37e75997ed86dbdfdc83df35f2152bb1
cheers
^ permalink raw reply
* Re: [PATCH] powerpc/signal: Fix possible build failure with unsafe_copy_fpr_{to/from}_user
From: Michael Ellerman @ 2021-05-15 22:43 UTC (permalink / raw)
To: Paul Mackerras, Benjamin Herrenschmidt, Michael Ellerman,
Christophe Leroy
Cc: linuxppc-dev, linux-kernel
In-Reply-To: <cadc0a328bc8e6c5bf133193e7547d5c10ae7895.1620465920.git.christophe.leroy@csgroup.eu>
On Sat, 8 May 2021 09:25:44 +0000 (UTC), Christophe Leroy wrote:
> When neither CONFIG_VSX nor CONFIG_PPC_FPU_REGS are selected,
> unsafe_copy_fpr_to_user() and unsafe_copy_fpr_from_user() are
> doing nothing.
>
> Then, unless the 'label' operand is used elsewhere, GCC complains
> about it being defined but not used.
>
> [...]
Applied to powerpc/fixes.
[1/1] powerpc/signal: Fix possible build failure with unsafe_copy_fpr_{to/from}_user
https://git.kernel.org/powerpc/c/bc581dbab26edf0b6acc98c76943b4a0c7d672a2
cheers
^ permalink raw reply
* Re: [PATCH] powerpc/syscall: Calling kuap_save_and_lock() is wrong
From: Michael Ellerman @ 2021-05-15 22:43 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman,
Christophe Leroy
Cc: linuxppc-dev, linux-kernel
In-Reply-To: <332773775cf24a422105dee2d383fb8f04589045.1620302182.git.christophe.leroy@csgroup.eu>
On Thu, 6 May 2021 11:56:31 +0000 (UTC), Christophe Leroy wrote:
> kuap_save_and_lock() is only for interrupts inside kernel.
>
> system call are only from user, calling kuap_save_and_lock()
> is wrong.
Applied to powerpc/fixes.
[1/1] powerpc/syscall: Calling kuap_save_and_lock() is wrong
https://git.kernel.org/powerpc/c/5d510ed78bcfcbbd3b3891cbe79cd7543bce1d05
cheers
^ permalink raw reply
* Re: [PATCH] powerpc/uaccess: Fix __get_user() with CONFIG_CC_HAS_ASM_GOTO_OUTPUT
From: Michael Ellerman @ 2021-05-15 22:43 UTC (permalink / raw)
To: Paul Mackerras, Benjamin Herrenschmidt, Michael Ellerman,
Christophe Leroy
Cc: linuxppc-dev, linux-kernel
In-Reply-To: <cf0a050d124d4f426cdc7a74009d17b01d8d8969.1620465917.git.christophe.leroy@csgroup.eu>
On Sat, 8 May 2021 09:25:32 +0000 (UTC), Christophe Leroy wrote:
> Building kernel mainline with GCC 11 leads to following failure
> when starting 'init':
>
> init[1]: bad frame in sys_sigreturn: 7ff5a900 nip 001083cc lr 001083c4
> Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b
>
> This is an issue due to a segfault happening in
> __unsafe_restore_general_regs() in a loop copying registers from user
> to kernel:
>
> [...]
Applied to powerpc/fixes.
[1/1] powerpc/uaccess: Fix __get_user() with CONFIG_CC_HAS_ASM_GOTO_OUTPUT
https://git.kernel.org/powerpc/c/7315e457d6bc342d06ba0b7ee498221c5237a547
cheers
^ permalink raw reply
* Re: [PATCH 1/2] powerpc/64s: Fix entry flush patching w/strict RWX & hash
From: Michael Ellerman @ 2021-05-15 22:43 UTC (permalink / raw)
To: Michael Ellerman, linuxppc-dev
In-Reply-To: <20210513140800.1391706-1-mpe@ellerman.id.au>
On Fri, 14 May 2021 00:07:59 +1000, Michael Ellerman wrote:
> The entry flush mitigation can be enabled/disabled at runtime. When this
> happens it results in the kernel patching its own instructions to
> enable/disable the mitigation sequence.
>
> With strict kernel RWX enabled instruction patching happens via a
> secondary mapping of the kernel text, so that we don't have to make the
> primary mapping writable. With the hash MMU this leads to a hash fault,
> which causes us to execute the exception entry which contains the entry
> flush mitigation.
>
> [...]
Applied to powerpc/fixes.
[1/2] powerpc/64s: Fix entry flush patching w/strict RWX & hash
https://git.kernel.org/powerpc/c/49b39ec248af863781a13aa6d81c5f69a2928094
[2/2] powerpc/64s: Fix stf mitigation patching w/strict RWX & hash
https://git.kernel.org/powerpc/c/5b48ba2fbd77bc68feebd336ffad5ff166782bde
cheers
^ permalink raw reply
* Re: [PATCH] KVM: PPC: Book3S HV: Fix kvm_unmap_gfn_range_hv() for Hash MMU
From: Michael Ellerman @ 2021-05-15 22:43 UTC (permalink / raw)
To: Michael Ellerman, linuxppc-dev; +Cc: kvm-ppc, pbonzini, npiggin, kvm, seanjc
In-Reply-To: <20210511105459.800788-1-mpe@ellerman.id.au>
On Tue, 11 May 2021 20:54:59 +1000, Michael Ellerman wrote:
> Commit 32b48bf8514c ("KVM: PPC: Book3S HV: Fix conversion to gfn-based
> MMU notifier callbacks") fixed kvm_unmap_gfn_range_hv() by adding a for
> loop over each gfn in the range.
>
> But for the Hash MMU it repeatedly calls kvm_unmap_rmapp() with the
> first gfn of the range, rather than iterating through the range.
>
> [...]
Applied to powerpc/fixes.
[1/1] KVM: PPC: Book3S HV: Fix kvm_unmap_gfn_range_hv() for Hash MMU
https://git.kernel.org/powerpc/c/da3bb206c9ceb0736d9e2897ea697acabad35833
cheers
^ permalink raw reply
* Re: [PATCH v2 1/2] powerpc/64s: Fix crashes when toggling stf barrier
From: Michael Ellerman @ 2021-05-15 22:43 UTC (permalink / raw)
To: Michael Ellerman, linuxppc-dev; +Cc: nathanl, anton, npiggin, dja
In-Reply-To: <20210506044959.1298123-1-mpe@ellerman.id.au>
On Thu, 6 May 2021 14:49:58 +1000, Michael Ellerman wrote:
> The STF (store-to-load forwarding) barrier mitigation can be
> enabled/disabled at runtime via a debugfs file (stf_barrier), which
> causes the kernel to patch itself to enable/disable the relevant
> mitigations.
>
> However depending on which mitigation we're using, it may not be safe to
> do that patching while other CPUs are active. For example the following
> crash:
>
> [...]
Applied to powerpc/fixes.
[1/2] powerpc/64s: Fix crashes when toggling stf barrier
https://git.kernel.org/powerpc/c/8ec7791bae1327b1c279c5cd6e929c3b12daaf0a
[2/2] powerpc/64s: Fix crashes when toggling entry flush barrier
https://git.kernel.org/powerpc/c/aec86b052df6541cc97c5fca44e5934cbea4963b
cheers
^ permalink raw reply
* Re: [PATCH] powerpc/64e/interrupt: fix nvgprs being clobbered
From: Michael Ellerman @ 2021-05-15 22:43 UTC (permalink / raw)
To: Nicholas Piggin, linuxppc-dev; +Cc: Christian Zigotzky
In-Reply-To: <20210514044008.1955783-1-npiggin@gmail.com>
On Fri, 14 May 2021 14:40:08 +1000, Nicholas Piggin wrote:
> Some interrupt handlers have an "extra" that saves 1 or 2 registers
> (r14, r15) in the paca save area and makes them available to use by the
> handler.
>
> The change to always save nvgprs in exception handlers lead to some
> interrupt handlers saving those scratch r14 / r15 registers into the
> interrupt frame's GPR saves, which get restored on interrupt exit.
>
> [...]
Applied to powerpc/fixes.
[1/1] powerpc/64e/interrupt: fix nvgprs being clobbered
https://git.kernel.org/powerpc/c/c6ac667b07996929835b512de0e9a988977e6abc
cheers
^ permalink raw reply
* Re: [PATCH] powerpc/64s: Make NMI record implicitly soft-masked code as irqs disabled
From: Michael Ellerman @ 2021-05-15 22:43 UTC (permalink / raw)
To: Nicholas Piggin, linuxppc-dev; +Cc: Cédric Le Goater
In-Reply-To: <20210503111708.758261-1-npiggin@gmail.com>
On Mon, 3 May 2021 21:17:08 +1000, Nicholas Piggin wrote:
> scv support introduced the notion of code that implicitly soft-masks
> irqs due to the instruction addresses. This is required because scv
> enters the kernel with MSR[EE]=1.
>
> If a NMI (including soft-NMI) interrupt hits when we are implicitly
> soft-masked then its regs->softe does not reflect this because it is
> derived from the explicit soft mask state (paca->irq_soft_mask). This
> makes arch_irq_disabled_regs(regs) return false.
>
> [...]
Applied to powerpc/fixes.
[1/1] powerpc/64s: Make NMI record implicitly soft-masked code as irqs disabled
https://git.kernel.org/powerpc/c/4ec5feec1ad029bdf7d49bc50ccc0c195eeabe93
cheers
^ permalink raw reply
* Re: [PATCH v2 0/4] Fix queued spinlocks and a bit more
From: Michael Ellerman @ 2021-05-15 22:43 UTC (permalink / raw)
To: Nicholas Piggin, linuxppc-dev
In-Reply-To: <20210508101455.1578318-1-npiggin@gmail.com>
On Sat, 8 May 2021 20:14:51 +1000, Nicholas Piggin wrote:
> This didn't seem to send properly, apologies if you get a duplicate.
>
> Patch 1 is the important fix. 2 might fix something, although I haven't
> provoked a crash yet.
>
> Patch 3 is a small cleanup, and patch 4 I think is the right thing to do
> but these could wait for later.
>
> [...]
Applied to powerpc/fixes.
[1/4] powerpc/pseries: Fix hcall tracing recursion in pv queued spinlocks
https://git.kernel.org/powerpc/c/2c8c89b95831f46a2fb31a8d0fef4601694023ce
[2/4] powerpc/pseries: Don't trace hcall tracing wrapper
https://git.kernel.org/powerpc/c/a3f1a39a5643d5c5ed3eee4edd933e0ebfeeed6e
[3/4] powerpc/pseries: use notrace hcall variant for H_CEDE idle
https://git.kernel.org/powerpc/c/7058f4b13edd9dd2cb3c5b4fe340d8307dbe0208
[4/4] powerpc/pseries: warn if recursing into the hcall tracing code
https://git.kernel.org/powerpc/c/4f242fc5f2e24412b89e934dad025b10293b2712
cheers
^ permalink raw reply
* Re: [PATCH v5 5/9] powerpc/mm/book3s64: Update tlb flush routines to take a page walk cache flush argument
From: Guenter Roeck @ 2021-05-15 23:05 UTC (permalink / raw)
To: Andrew Morton
Cc: Aneesh Kumar K.V, npiggin, linux-mm, kaleshsingh, joel,
linuxppc-dev
In-Reply-To: <20210515134141.b719412dc9dc46bdf2a8ced2@linux-foundation.org>
On 5/15/21 1:41 PM, Andrew Morton wrote:
> On Sat, 15 May 2021 09:35:25 -0700 Guenter Roeck <linux@roeck-us.net> wrote:
>
>>>
>>> #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE
>>> static inline void flush_pmd_tlb_range(struct vm_area_struct *vma,
>> ^^^^
>>> unsigned long start, unsigned long end)
>>> +{
>>> + return flush_pmd_tlb_pwc_range(vma, start, end, false);
>> ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
>>
>> Doesn't that cause build warnings/errors all over the place ?
>
> It will, thanks. I queued a fix.
>
Also in mm/mremap.c, in case you didn't see it:
#ifndef flush_pte_tlb_pwc_range
#define flush_pte_tlb_pwc_range flush_pte_tlb_pwc_range
static inline void flush_pte_tlb_pwc_range(struct vm_area_struct *vma,
^^^^
unsigned long start,
unsigned long end)
{
return flush_tlb_range(vma, start, end);
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
}
^ permalink raw reply
* [GIT PULL] Please pull powerpc/linux.git powerpc-5.13-3 tag
From: Michael Ellerman @ 2021-05-15 23:35 UTC (permalink / raw)
To: Linus Torvalds; +Cc: linuxppc-dev, linux-kernel, npiggin
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA256
Hi Linus,
Please pull some more powerpc fixes for 5.13:
The following changes since commit 6efb943b8616ec53a5e444193dccf1af9ad627b5:
Linux 5.13-rc1 (2021-05-09 14:17:44 -0700)
are available in the git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git tags/powerpc-5.13-3
for you to fetch changes up to c6ac667b07996929835b512de0e9a988977e6abc:
powerpc/64e/interrupt: Fix nvgprs being clobbered (2021-05-14 17:28:54 +1000)
- ------------------------------------------------------------------
powerpc fixes for 5.13 #3
- Fix a regression in the conversion of the 64-bit BookE interrupt entry to C.
- Fix KVM hosts running with the hash MMU since the recent KVM gfn changes.
- Fix a deadlock in our paravirt spinlocks when hcall tracing is enabled.
- Several fixes for oopses in our runtime code patching for security mitigations.
- A couple of minor fixes for the recent conversion of 32-bit interrupt entry/exit to C.
- Fix __get_user() causing spurious crashes in sigreturn due to a bad inline asm
constraint, spotted with GCC 11.
- A fix for the way we track IRQ masking state vs NMI interrupts when using the new scv
system call entry path.
- A couple more minor fixes.
Thanks to: Cédric Le Goater, Christian Zigotzky, Christophe Leroy, Naveen N. Rao, Nicholas
Piggin Paul Menzel, Sean Christopherson.
- ------------------------------------------------------------------
Christophe Leroy (5):
powerpc/interrupts: Fix kuep_unlock() call
powerpc/syscall: Calling kuap_save_and_lock() is wrong
powerpc/uaccess: Fix __get_user() with CONFIG_CC_HAS_ASM_GOTO_OUTPUT
powerpc/signal: Fix possible build failure with unsafe_copy_fpr_{to/from}_user
powerpc/legacy_serial: Fix UBSAN: array-index-out-of-bounds
Michael Ellerman (5):
KVM: PPC: Book3S HV: Fix kvm_unmap_gfn_range_hv() for Hash MMU
powerpc/64s: Fix crashes when toggling stf barrier
powerpc/64s: Fix crashes when toggling entry flush barrier
powerpc/64s: Fix entry flush patching w/strict RWX & hash
powerpc/64s: Fix stf mitigation patching w/strict RWX & hash
Nicholas Piggin (6):
powerpc/pseries: Fix hcall tracing recursion in pv queued spinlocks
powerpc/pseries: Don't trace hcall tracing wrapper
powerpc/pseries: use notrace hcall variant for H_CEDE idle
powerpc/pseries: warn if recursing into the hcall tracing code
powerpc/64s: Make NMI record implicitly soft-masked code as irqs disabled
powerpc/64e/interrupt: Fix nvgprs being clobbered
arch/powerpc/include/asm/hvcall.h | 3 +
arch/powerpc/include/asm/interrupt.h | 9 +-
arch/powerpc/include/asm/paravirt.h | 22 +++-
arch/powerpc/include/asm/plpar_wrappers.h | 6 +-
arch/powerpc/include/asm/uaccess.h | 2 +-
arch/powerpc/kernel/exceptions-64e.S | 38 ++++---
arch/powerpc/kernel/interrupt.c | 4 +-
arch/powerpc/kernel/legacy_serial.c | 7 +-
arch/powerpc/kernel/signal.h | 4 +-
arch/powerpc/kvm/book3s_64_mmu_hv.c | 2 +-
arch/powerpc/lib/feature-fixups.c | 114 +++++++++++++++-----
arch/powerpc/platforms/pseries/hvCall.S | 10 ++
arch/powerpc/platforms/pseries/lpar.c | 29 +++--
13 files changed, 175 insertions(+), 75 deletions(-)
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^ permalink raw reply
* Re: [GIT PULL] Please pull powerpc/linux.git powerpc-5.13-3 tag
From: pr-tracker-bot @ 2021-05-15 23:50 UTC (permalink / raw)
To: Michael Ellerman; +Cc: linuxppc-dev, Linus Torvalds, linux-kernel, npiggin
In-Reply-To: <871ra7lge5.fsf@mpe.ellerman.id.au>
The pull request you sent on Sun, 16 May 2021 09:35:30 +1000:
> https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git tags/powerpc-5.13-3
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/63d1cb53e26a9a4168b84a8981b225c0a9cfa235
Thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/prtracker.html
^ permalink raw reply
* [powerpc:next-test] BUILD SUCCESS 4938c440ff7f2c27641f6639d1202f52759ea3ff
From: kernel test robot @ 2021-05-16 11:58 UTC (permalink / raw)
To: Michael Ellerman; +Cc: linuxppc-dev
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next-test
branch HEAD: 4938c440ff7f2c27641f6639d1202f52759ea3ff powerpc/pseries/ras: Delete a redundant condition branch
elapsed time: 723m
configs tested: 118
configs skipped: 2
The following configs have been built successfully.
More configs may be tested in the coming days.
gcc tested configs:
arm defconfig
arm64 allyesconfig
arm64 defconfig
arm allyesconfig
arm allmodconfig
powerpc mpc832x_rdb_defconfig
mips pic32mzda_defconfig
ia64 generic_defconfig
arm viper_defconfig
arm spear3xx_defconfig
arm shannon_defconfig
arm lubbock_defconfig
arm keystone_defconfig
openrisc simple_smp_defconfig
mips maltasmvp_defconfig
powerpc ppa8548_defconfig
powerpc tqm8541_defconfig
arm shmobile_defconfig
arm stm32_defconfig
arm versatile_defconfig
mips nlm_xlr_defconfig
sh dreamcast_defconfig
um x86_64_defconfig
powerpc acadia_defconfig
powerpc64 alldefconfig
sh sh7757lcr_defconfig
powerpc mpc836x_rdk_defconfig
sh sdk7780_defconfig
m68k amiga_defconfig
arm pcm027_defconfig
mips jmr3927_defconfig
arc nsimosci_hs_defconfig
mips db1xxx_defconfig
mips maltaup_xpa_defconfig
powerpc ksi8560_defconfig
mips lemote2f_defconfig
powerpc mpc8560_ads_defconfig
arm xcep_defconfig
m68k m5275evb_defconfig
h8300 alldefconfig
sh rts7751r2dplus_defconfig
arm qcom_defconfig
powerpc powernv_defconfig
mips loongson1c_defconfig
x86_64 allnoconfig
ia64 allmodconfig
ia64 defconfig
ia64 allyesconfig
m68k allmodconfig
m68k defconfig
m68k allyesconfig
nios2 defconfig
arc allyesconfig
nds32 allnoconfig
nds32 defconfig
nios2 allyesconfig
csky defconfig
alpha defconfig
alpha allyesconfig
xtensa allyesconfig
h8300 allyesconfig
arc defconfig
sh allmodconfig
parisc defconfig
s390 allyesconfig
s390 allmodconfig
parisc allyesconfig
s390 defconfig
i386 allyesconfig
sparc allyesconfig
sparc defconfig
i386 defconfig
mips allyesconfig
mips allmodconfig
powerpc allyesconfig
powerpc allmodconfig
powerpc allnoconfig
x86_64 randconfig-a004-20210516
x86_64 randconfig-a003-20210516
x86_64 randconfig-a001-20210516
x86_64 randconfig-a005-20210516
x86_64 randconfig-a002-20210516
x86_64 randconfig-a006-20210516
i386 randconfig-a003-20210516
i386 randconfig-a001-20210516
i386 randconfig-a004-20210516
i386 randconfig-a005-20210516
i386 randconfig-a002-20210516
i386 randconfig-a006-20210516
i386 randconfig-a016-20210516
i386 randconfig-a014-20210516
i386 randconfig-a011-20210516
i386 randconfig-a012-20210516
i386 randconfig-a015-20210516
i386 randconfig-a013-20210516
riscv nommu_k210_defconfig
riscv allyesconfig
riscv nommu_virt_defconfig
riscv allnoconfig
riscv defconfig
riscv rv32_defconfig
riscv allmodconfig
um allmodconfig
um allnoconfig
um allyesconfig
um defconfig
x86_64 allyesconfig
x86_64 rhel-8.3-kselftests
x86_64 defconfig
x86_64 rhel-8.3
x86_64 rhel-8.3-kbuiltin
x86_64 kexec
clang tested configs:
x86_64 randconfig-a015-20210516
x86_64 randconfig-a012-20210516
x86_64 randconfig-a011-20210516
x86_64 randconfig-a013-20210516
x86_64 randconfig-a016-20210516
x86_64 randconfig-a014-20210516
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
^ permalink raw reply
* [powerpc:merge] BUILD SUCCESS 3a81c0495fdb91fd9a9b4f617098c283131eeae1
From: kernel test robot @ 2021-05-16 11:58 UTC (permalink / raw)
To: Michael Ellerman; +Cc: linuxppc-dev
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git merge
branch HEAD: 3a81c0495fdb91fd9a9b4f617098c283131eeae1 Automatic merge of 'fixes' into merge (2021-05-16 08:46)
elapsed time: 723m
configs tested: 119
configs skipped: 2
The following configs have been built successfully.
More configs may be tested in the coming days.
gcc tested configs:
arm defconfig
arm64 allyesconfig
arm64 defconfig
arm allyesconfig
arm allmodconfig
powerpc mpc832x_rdb_defconfig
mips pic32mzda_defconfig
ia64 generic_defconfig
arm viper_defconfig
arm spear3xx_defconfig
arm shannon_defconfig
arm lubbock_defconfig
arm keystone_defconfig
openrisc simple_smp_defconfig
mips maltasmvp_defconfig
powerpc ppa8548_defconfig
sh apsh4a3a_defconfig
arc vdk_hs38_smp_defconfig
powerpc ppc64e_defconfig
sh sh7770_generic_defconfig
mips nlm_xlp_defconfig
um x86_64_defconfig
powerpc acadia_defconfig
powerpc64 alldefconfig
sh sh7757lcr_defconfig
powerpc mpc836x_rdk_defconfig
sh sdk7780_defconfig
m68k amiga_defconfig
arm pcm027_defconfig
mips jmr3927_defconfig
arc nsimosci_hs_defconfig
powerpc mpc8560_ads_defconfig
arm xcep_defconfig
m68k m5275evb_defconfig
h8300 alldefconfig
sh rts7751r2dplus_defconfig
powerpc adder875_defconfig
arm omap1_defconfig
arm pxa910_defconfig
sh sh03_defconfig
arm aspeed_g5_defconfig
sh r7785rp_defconfig
powerpc holly_defconfig
sparc sparc64_defconfig
mips pistachio_defconfig
x86_64 allnoconfig
ia64 allmodconfig
ia64 defconfig
ia64 allyesconfig
m68k allmodconfig
m68k defconfig
m68k allyesconfig
nios2 defconfig
arc allyesconfig
nds32 allnoconfig
nds32 defconfig
nios2 allyesconfig
csky defconfig
alpha defconfig
alpha allyesconfig
xtensa allyesconfig
h8300 allyesconfig
arc defconfig
sh allmodconfig
parisc defconfig
s390 allyesconfig
s390 allmodconfig
parisc allyesconfig
s390 defconfig
i386 allyesconfig
sparc allyesconfig
sparc defconfig
i386 defconfig
mips allyesconfig
mips allmodconfig
powerpc allyesconfig
powerpc allmodconfig
powerpc allnoconfig
x86_64 randconfig-a004-20210516
x86_64 randconfig-a003-20210516
x86_64 randconfig-a001-20210516
x86_64 randconfig-a005-20210516
x86_64 randconfig-a002-20210516
x86_64 randconfig-a006-20210516
i386 randconfig-a003-20210516
i386 randconfig-a001-20210516
i386 randconfig-a004-20210516
i386 randconfig-a005-20210516
i386 randconfig-a002-20210516
i386 randconfig-a006-20210516
i386 randconfig-a016-20210516
i386 randconfig-a014-20210516
i386 randconfig-a011-20210516
i386 randconfig-a012-20210516
i386 randconfig-a015-20210516
i386 randconfig-a013-20210516
riscv nommu_k210_defconfig
riscv allyesconfig
riscv nommu_virt_defconfig
riscv allnoconfig
riscv defconfig
riscv rv32_defconfig
riscv allmodconfig
um allmodconfig
um allnoconfig
um allyesconfig
um defconfig
x86_64 allyesconfig
x86_64 rhel-8.3-kselftests
x86_64 defconfig
x86_64 rhel-8.3
x86_64 rhel-8.3-kbuiltin
x86_64 kexec
clang tested configs:
x86_64 randconfig-a015-20210516
x86_64 randconfig-a012-20210516
x86_64 randconfig-a011-20210516
x86_64 randconfig-a013-20210516
x86_64 randconfig-a016-20210516
x86_64 randconfig-a014-20210516
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
^ permalink raw reply
* Re: [PATCH v13 6/8] powerpc: Set ARCH_HAS_STRICT_MODULE_RWX
From: Jordan Niethe @ 2021-05-17 1:28 UTC (permalink / raw)
To: Christophe Leroy
Cc: ajd, Nicholas Piggin, cmr, Aneesh Kumar K.V, naveen.n.rao,
linuxppc-dev, Daniel Axtens
In-Reply-To: <3678a605-d2bb-5417-ff2d-9155c95835e0@csgroup.eu>
On Fri, May 14, 2021 at 3:50 PM Christophe Leroy
<christophe.leroy@csgroup.eu> wrote:
>
>
>
> Le 10/05/2021 à 03:18, Jordan Niethe a écrit :
> > From: Russell Currey <ruscur@russell.cc>
> >
> > To enable strict module RWX on powerpc, set:
> >
> > CONFIG_STRICT_MODULE_RWX=y
> >
> > You should also have CONFIG_STRICT_KERNEL_RWX=y set to have any real
> > security benefit.
> >
> > ARCH_HAS_STRICT_MODULE_RWX is set to require ARCH_HAS_STRICT_KERNEL_RWX.
> > This is due to a quirk in arch/Kconfig and arch/powerpc/Kconfig that
> > makes STRICT_MODULE_RWX *on by default* in configurations where
> > STRICT_KERNEL_RWX is *unavailable*.
> >
> > Since this doesn't make much sense, and module RWX without kernel RWX
> > doesn't make much sense, having the same dependencies as kernel RWX
> > works around this problem.
> >
> > With STRICT_MODULE_RWX, now make module_alloc() allocate pages with
> > KERNEL_PAGE protection rather than KERNEL_PAGE_EXEC.
> >
> > Book32s/32 processors with a hash mmu (i.e. 604 core) can not set memory
> > protection on a page by page basis so do not enable.
> >
> > Signed-off-by: Russell Currey <ruscur@russell.cc>
> > [jpn: - predicate on !PPC_BOOK3S_604
> > - make module_alloc() use PAGE_KERNEL protection]
> > Signed-off-by: Jordan Niethe <jniethe5@gmail.com>
> > ---
> > v10: - Predicate on !PPC_BOOK3S_604
> > - Make module_alloc() use PAGE_KERNEL protection
> > v11: - Neaten up
> > v13: Use strict_kernel_rwx_enabled()
> > ---
> > arch/powerpc/Kconfig | 1 +
> > arch/powerpc/kernel/module.c | 4 +++-
> > 2 files changed, 4 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
> > index cce0a137b046..cb5d9d862c35 100644
> > --- a/arch/powerpc/Kconfig
> > +++ b/arch/powerpc/Kconfig
> > @@ -140,6 +140,7 @@ config PPC
> > select ARCH_HAS_SCALED_CPUTIME if VIRT_CPU_ACCOUNTING_NATIVE && PPC_BOOK3S_64
> > select ARCH_HAS_SET_MEMORY
> > select ARCH_HAS_STRICT_KERNEL_RWX if ((PPC_BOOK3S_64 || PPC32) && !HIBERNATION)
> > + select ARCH_HAS_STRICT_MODULE_RWX if ARCH_HAS_STRICT_KERNEL_RWX && !PPC_BOOK3S_604
> > select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
> > select ARCH_HAS_UACCESS_FLUSHCACHE
> > select ARCH_HAS_COPY_MC if PPC64
> > diff --git a/arch/powerpc/kernel/module.c b/arch/powerpc/kernel/module.c
> > index 3f35c8d20be7..f24004635ed5 100644
> > --- a/arch/powerpc/kernel/module.c
> > +++ b/arch/powerpc/kernel/module.c
> > @@ -92,12 +92,14 @@ int module_finalize(const Elf_Ehdr *hdr,
> > static __always_inline void *
> > __module_alloc(unsigned long size, unsigned long start, unsigned long end)
> > {
> > + pgprot_t prot = strict_kernel_rwx_enabled() ? PAGE_KERNEL : PAGE_KERNEL_EXEC;
> > +
>
> I'm not sure this is OK.
>
> I think we need to make a new helper strict_module_rwx_enabled() because I don't think we want
> PAGE_KERNEL here when CONFIG_STRICT_MODULE_RWX is not selected.
Yeah that seems like the right thing to do. I'll send a new version.
>
>
> > /*
> > * Don't do huge page allocations for modules yet until more testing
> > * is done. STRICT_MODULE_RWX may require extra work to support this
> > * too.
> > */
> > - return __vmalloc_node_range(size, 1, start, end, GFP_KERNEL, PAGE_KERNEL_EXEC,
> > + return __vmalloc_node_range(size, 1, start, end, GFP_KERNEL, prot,
> > VM_FLUSH_RESET_PERMS | VM_NO_HUGE_VMAP,
> > NUMA_NO_NODE, __builtin_return_address(0));
> > }
> >
^ permalink raw reply
* Re: [PATCH V2 1/1] powerpc/perf: Fix PMU callbacks to clear pending PMI before resetting an overflown PMC
From: Nicholas Piggin @ 2021-05-17 3:20 UTC (permalink / raw)
To: Athira Rajeev, mpe; +Cc: nasastry, maddy, linuxppc-dev
In-Reply-To: <1618887697-1556-2-git-send-email-atrajeev@linux.vnet.ibm.com>
Sorry I missed this :(
Excerpts from Athira Rajeev's message of April 20, 2021 1:01 pm:
> Running perf fuzzer showed below in dmesg logs:
> "Can't find PMC that caused IRQ"
>
> This means a PMU exception happened, but none of the PMC's (Performance
> Monitor Counter) were found to be overflown. There are some corner cases
> that clears the PMCs after PMI gets masked. In such cases, the perf
> interrupt handler will not find the active PMC values that had caused
> the overflow and thus leads to this message while replaying.
>
> Case 1: PMU Interrupt happens during replay of other interrupts and
> counter values gets cleared by PMU callbacks before replay:
>
> During replay of interrupts like timer, __do_irq and doorbell exception, we
> conditionally enable interrupts via may_hard_irq_enable(). This could
> potentially create a window to generate a PMI. Since irq soft mask is set
> to ALL_DISABLED, the PMI will get masked here. We could get IPIs run before
> perf interrupt is replayed and the PMU events could deleted or stopped.
> This will change the PMU SPR values and resets the counters. Snippet of
> ftrace log showing PMU callbacks invoked in "__do_irq":
>
> <idle>-0 [051] dns. 132025441306354: __do_irq <-call_do_irq
> <idle>-0 [051] dns. 132025441306430: irq_enter <-__do_irq
> <idle>-0 [051] dns. 132025441306503: irq_enter_rcu <-__do_irq
> <idle>-0 [051] dnH. 132025441306599: xive_get_irq <-__do_irq
> <<>>
> <idle>-0 [051] dnH. 132025441307770: generic_smp_call_function_single_interrupt <-smp_ipi_demux_relaxed
> <idle>-0 [051] dnH. 132025441307839: flush_smp_call_function_queue <-smp_ipi_demux_relaxed
> <idle>-0 [051] dnH. 132025441308057: _raw_spin_lock <-event_function
> <idle>-0 [051] dnH. 132025441308206: power_pmu_disable <-perf_pmu_disable
> <idle>-0 [051] dnH. 132025441308337: power_pmu_del <-event_sched_out
> <idle>-0 [051] dnH. 132025441308407: power_pmu_read <-power_pmu_del
> <idle>-0 [051] dnH. 132025441308477: read_pmc <-power_pmu_read
> <idle>-0 [051] dnH. 132025441308590: isa207_disable_pmc <-power_pmu_del
> <idle>-0 [051] dnH. 132025441308663: write_pmc <-power_pmu_del
> <idle>-0 [051] dnH. 132025441308787: power_pmu_event_idx <-perf_event_update_userpage
> <idle>-0 [051] dnH. 132025441308859: rcu_read_unlock_strict <-perf_event_update_userpage
> <idle>-0 [051] dnH. 132025441308975: power_pmu_enable <-perf_pmu_enable
> <<>>
> <idle>-0 [051] dnH. 132025441311108: irq_exit <-__do_irq
> <idle>-0 [051] dns. 132025441311319: performance_monitor_exception <-replay_soft_interrupts
>
> Case 2: PMI's masked during local_* operations, example local_add.
> If the local_add operation happens within a local_irq_save, replay of
> PMI will be during local_irq_restore. Similar to case 1, this could
> also create a window before replay where PMU events gets deleted or
> stopped.
>
> Patch adds a fix to update the PMU callback functions (del,stop,enable) to
> check for pending perf interrupt. If there is an overflown PMC and pending
> perf interrupt indicated in Paca or by PMAO bit set in MMCR0, clear the PMI
> bit in paca to drop that sample. Also clear the MMCR0 PMAO bit which
> otherwise could lead to spurious interrupts in some corner cases. Example,
> a timer after power_pmu_del which will re-enable interrupts since PMI is
> cleared and triggers a PMI again since PMAO bit is still set. Another
> condition occures if had disabled MSR[EE] right before perf interrupt
> came in. Re-enabling interrupt will trigger PMI since PMAO is still set.
> But fails to find valid overflow if PMC get cleared before enabling EE.
>
> We can't just replay PMI any time. Hence this approach is preferred rather
> than replaying PMI before resetting overflown PMC. Patch also documents
> core-book3s on a race condition which can trigger these PMC messages during
> idle path in PowerNV.
>
> Fixes: f442d004806e ("powerpc/64s: Add support to mask perf interrupts and replay them")
> Reported-by: Nageswara R Sastry <nasastry@in.ibm.com>
> Suggested-by: Nicholas Piggin <npiggin@gmail.com>
I would say you can leave ^ this line out. You and Maddy did the hard
work of coming up with the fix, I just suggested a few minor changes.
> Suggested-by: Madhavan Srinivasan <maddy@linux.ibm.com>
> Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
> ---
> arch/powerpc/include/asm/hw_irq.h | 19 ++++++++
> arch/powerpc/perf/core-book3s.c | 77 +++++++++++++++++++++++++++++++
> 2 files changed, 96 insertions(+)
>
> diff --git a/arch/powerpc/include/asm/hw_irq.h b/arch/powerpc/include/asm/hw_irq.h
> index 56a98936a6a9..7e192bd8253b 100644
> --- a/arch/powerpc/include/asm/hw_irq.h
> +++ b/arch/powerpc/include/asm/hw_irq.h
> @@ -215,6 +215,23 @@ static inline bool arch_irqs_disabled(void)
> return arch_irqs_disabled_flags(arch_local_save_flags());
> }
>
> +static inline int get_clear_pmi_irq_pending(void)
> +{
> + /*
> + * Some corner cases could clear the PMU counter overflow
> + * while a masked PMI is pending. One of such case is
> + * when a PMI happens during interrupt replay and perf
> + * counter values gets cleared by PMU callbacks before
> + * replay. So the pending PMI must be cleared here.
> + */
> + if (get_paca()->irq_happened & PACA_IRQ_PMI) {
> + WARN_ON_ONCE(mfmsr() & MSR_EE);
> + get_paca()->irq_happened &= ~PACA_IRQ_PMI;
> + return 1;
> + }
> + return 0;
> +}
This is fine, if you respin it, you could make it return bool, and put
the warning under if (IS_ENABLED(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG)).
> +
> #ifdef CONFIG_PPC_BOOK3S
> /*
> * To support disabling and enabling of irq with PMI, set of
> @@ -391,6 +408,8 @@ static inline bool arch_irq_disabled_regs(struct pt_regs *regs)
>
> static inline void may_hard_irq_enable(void) { }
>
> +static inline int get_clear_pmi_irq_pending(void) { return 0; }
> +
> static inline void irq_soft_mask_regs_set_state(struct pt_regs *regs, unsigned long val)
> {
> }
> diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
> index 766f064f00fb..6ddac1b913fa 100644
> --- a/arch/powerpc/perf/core-book3s.c
> +++ b/arch/powerpc/perf/core-book3s.c
> @@ -847,6 +847,20 @@ static void write_pmc(int idx, unsigned long val)
> }
> }
>
> +static int pmc_overflown(int idx)
> +{
> + unsigned long val[8];
> + int i;
> +
> + for (i = 0; i < ppmu->n_counter; i++)
> + val[i] = read_pmc(i + 1);
> +
> + if ((int)val[idx-1] < 0)
> + return 1;
> +
> + return 0;
I don't know the PMU very well -- do you have to read all counters, or
can you just read_pmc(idx)?
> +}
> +
> /* Called from sysrq_handle_showregs() */
> void perf_event_print_debug(void)
> {
> @@ -1438,6 +1452,17 @@ static void power_pmu_enable(struct pmu *pmu)
> event = cpuhw->event[i];
> if (event->hw.idx && event->hw.idx != hwc_index[i] + 1) {
> power_pmu_read(event);
> + /*
> + * if the PMC corresponding to event->hw.idx is
> + * overflown, check if there is any pending perf
> + * interrupt set in paca. If so, disable the interrupt
> + * by clearing the paca bit for PMI since we are going
> + * to reset the PMC. power_pmu_enable will reset PMAO bit
> + * of MMCR0 while enabling the event. So PMAO check
> + * is not needed here (versus PMAO check done in del/stop).
> + */
> + if (pmc_overflown(event->hw.idx))
> + get_clear_pmi_irq_pending();
power_pmu_read(event) is already reading the PMC, so I wonder if you
could just take that value directly. It's in event->hw.prev_count, I
think?
> write_pmc(event->hw.idx, 0);
> event->hw.idx = 0;
> }
> @@ -1474,6 +1499,10 @@ static void power_pmu_enable(struct pmu *pmu)
> event->hw.idx = idx;
> if (event->hw.state & PERF_HES_STOPPED)
> val = 0;
> +
> + /* See above for get_clear_pmi_irq_pending */
> + if (pmc_overflown(event->hw.idx))
> + get_clear_pmi_irq_pending();
Sorry, not sure of why this is done here. Wouldn't the PMC have already
been observed to be overflown and pending PMI cleared by the previous
check?
> write_pmc(idx, val);
>
> perf_event_update_userpage(event);
> @@ -1619,6 +1648,7 @@ static void power_pmu_del(struct perf_event *event, int ef_flags)
> struct cpu_hw_events *cpuhw;
> long i;
> unsigned long flags;
> + unsigned long val_mmcr0;
>
> local_irq_save(flags);
> perf_pmu_disable(event->pmu);
> @@ -1636,6 +1666,23 @@ static void power_pmu_del(struct perf_event *event, int ef_flags)
> --cpuhw->n_events;
> ppmu->disable_pmc(event->hw.idx - 1, &cpuhw->mmcr);
> if (event->hw.idx) {
> + /*
> + * if the PMC corresponding to event->hw.idx is
> + * overflown, check if there is any pending perf
> + * interrupt set in paca or indicated by PMAO bit
> + * in MMCR0. If so, disable the interrupt and clear
> + * the MMCR0 PMAO bit since we are going to reset
> + * the PMC and delete the event.
> + */
> + if (pmc_overflown(event->hw.idx)) {
> + if ((get_clear_pmi_irq_pending() | (mfspr(SPRN_MMCR0) & MMCR0_PMAO))) {
> + val_mmcr0 = mfspr(SPRN_MMCR0);
> + val_mmcr0 &= ~MMCR0_PMAO;
> + write_mmcr0(cpuhw, val_mmcr0);
> + mb();
> + isync();
> + }
> + }
Again showing my ignorance of PMU and powerpc/perf, power_pmu_disable
will have already cleared PMAO? How is it possible for it to become
set again here?
I can see how a PMI can be marked pending after local_irq_save and
before perf_pmu_disable call... I wonder if clearing that pending bit
should be done in power_pmu_disable (which matches the same place where
we clear PMAO)?
> write_pmc(event->hw.idx, 0);
> event->hw.idx = 0;
> }
> @@ -1705,6 +1752,8 @@ static void power_pmu_start(struct perf_event *event, int ef_flags)
> static void power_pmu_stop(struct perf_event *event, int ef_flags)
> {
> unsigned long flags;
> + unsigned long val_mmcr0;
> + struct cpu_hw_events *cpuhw;
>
> if (!event->hw.idx || !event->hw.sample_period)
> return;
> @@ -1713,8 +1762,27 @@ static void power_pmu_stop(struct perf_event *event, int ef_flags)
> return;
>
> local_irq_save(flags);
> + cpuhw = this_cpu_ptr(&cpu_hw_events);
> perf_pmu_disable(event->pmu);
>
> + /*
> + * if the PMC corresponding to event->hw.idx is
> + * overflown, check if there is any pending perf
> + * interrupt set in paca or indicated by PMAO bit
> + * in MMCR0. If so, disable the interrupt and clear
> + * the MMCR0 PMAO bit since we are going to reset
> + * the PMC.
> + */
> + if (pmc_overflown(event->hw.idx)) {
> + if ((get_clear_pmi_irq_pending() | (mfspr(SPRN_MMCR0) & MMCR0_PMAO))) {
> + val_mmcr0 = mfspr(SPRN_MMCR0);
> + val_mmcr0 &= ~MMCR0_PMAO;
> + write_mmcr0(cpuhw, val_mmcr0);
> + mb();
> + isync();
> + }
> + }
> +
> power_pmu_read(event);
> event->hw.state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
> write_pmc(event->hw.idx, 0);
Same question for this one. Also would be good to put this pattern into
a helper function if it has to be duplicated.
Thanks,
Nick
> @@ -2343,6 +2411,15 @@ static void __perf_event_interrupt(struct pt_regs *regs)
> }
> }
> }
> +
> + /*
> + * During system wide profling or while specific CPU
> + * is monitored for an event, some corner cases could
> + * cause PMC to overflow in idle path. This will trigger
> + * a PMI after waking up from idle. Since counter values
> + * are _not_ saved/restored in idle path, can lead to
> + * below "Can't find PMC" message.
> + */
> if (unlikely(!found) && !arch_irq_disabled_regs(regs))
> printk_ratelimited(KERN_WARNING "Can't find PMC that caused IRQ\n");
>
> --
> 2.26.2
>
>
^ permalink raw reply
* Re: [PATCH kernel v3] powerpc/makefile: Do not redefine $(CPP) for preprocessor
From: Alexey Kardashevskiy @ 2021-05-17 3:23 UTC (permalink / raw)
To: Segher Boessenkool, Masahiro Yamada
Cc: Michal Marek, Linux Kbuild mailing list, Nick Desaulniers,
Linux Kernel Mailing List, Nathan Chancellor, clang-built-linux,
linuxppc-dev
In-Reply-To: <20210514084649.GI10366@gate.crashing.org>
On 5/14/21 18:46, Segher Boessenkool wrote:
> Hi!
>
> On Fri, May 14, 2021 at 11:42:32AM +0900, Masahiro Yamada wrote:
>> In my best guess, the reason why powerpc adding the endian flag to CPP
>> is this line in arch/powerpc/kernel/vdso64/vdso64.lds.S
>>
>> #ifdef __LITTLE_ENDIAN__
>> OUTPUT_FORMAT("elf64-powerpcle", "elf64-powerpcle", "elf64-powerpcle")
>> #else
>> OUTPUT_FORMAT("elf64-powerpc", "elf64-powerpc", "elf64-powerpc")
>> #endif
>
> Which is equivalent to
>
> #ifdef __LITTLE_ENDIAN__
> OUTPUT_FORMAT("elf64-powerpcle")
> #else
> OUTPUT_FORMAT("elf64-powerpc")
> #endif
>
> so please change that at the same time if you touch this :-)
"If you touch this" approach did not work well with this patch so sorry
but no ;)
and for a separate patch, I'll have to dig since when it is equal, do
you know?
>
>> __LITTLE_ENDIAN__ is defined by powerpc gcc and clang.
>
> This predefined macro is required by the newer ABIs, but all older
That's good so I'll stick to it.
> compilers have it as well. _LITTLE_ENDIAN is not supported on all
> platforms (but it is if your compiler targets Linux, which you cannot
> necessarily rely on). These macros are PowerPC-specific.
>
> For GCC, for all targets, you can say
> #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
> You do not need any of the other *ORDER__ macros in most cases.
> See "info cpp" for the sordid details.
>
>> [2] powerpc-linux-gnu-gcc + -mlittle-endian -> __LITTLE_ENDIAN__ is defined
>
> You can just write -mbig and -mlittle btw. Those aren't available on
> all targets, but neither are the long-winded -m{big,little}-endian
> option names. Pet peeve, I know :-)
I am looking the same guarantees across modern enough gcc and clang and
I am not sure all of the above is valid for clang 10.0.something (or
whatever we say we support) ;)
--
Alexey
^ permalink raw reply
* [PATCH v14 0/9] powerpc: Further Strict RWX support
From: Jordan Niethe @ 2021-05-17 3:28 UTC (permalink / raw)
To: linuxppc-dev
Cc: ajd, cmr, npiggin, aneesh.kumar, naveen.n.rao, Jordan Niethe, dja
Adding more Strict RWX support on powerpc, in particular Strict Module RWX.
Thanks for all of the feedback everyone.
It is now rebased on linux-next + powerpc/64s/radix: Enable huge vmalloc mappings
(https://lore.kernel.org/linuxppc-dev/20210503091755.613393-1-npiggin@gmail.com/)
For reference the previous revision is available here:
https://lore.kernel.org/linuxppc-dev/20210510011828.4006623-1-jniethe5@gmail.com/
The changes in v14 for each patch:
Christophe Leroy (2):
powerpc/mm: implement set_memory_attr()
powerpc/32: use set_memory_attr()
Jordan Niethe (4):
powerpc/lib/code-patching: Set up Strict RWX patching earlier
powerpc/modules: Make module_alloc() Strict Module RWX aware
v14: - Split out from powerpc: Set ARCH_HAS_STRICT_MODULE_RW
- Add and use strict_module_rwx_enabled() helper
powerpc/bpf: Remove bpf_jit_free()
powerpc/bpf: Write protect JIT code
Russell Currey (3):
powerpc/mm: Implement set_memory() routines
v14: - only check is_vm_area_hugepages() for virtual memory
powerpc/kprobes: Mark newly allocated probes as ROX
v14: - Use strict_module_rwx_enabled()
powerpc: Set ARCH_HAS_STRICT_MODULE_RWX
v14: - Make changes to module_alloc() its own commit
arch/powerpc/Kconfig | 2 +
arch/powerpc/include/asm/mmu.h | 5 +
arch/powerpc/include/asm/set_memory.h | 34 +++++++
arch/powerpc/kernel/kprobes.c | 17 ++++
arch/powerpc/kernel/module.c | 4 +-
arch/powerpc/lib/code-patching.c | 12 +--
arch/powerpc/mm/Makefile | 2 +-
arch/powerpc/mm/pageattr.c | 134 ++++++++++++++++++++++++++
arch/powerpc/mm/pgtable_32.c | 60 ++----------
arch/powerpc/net/bpf_jit_comp.c | 13 +--
10 files changed, 211 insertions(+), 72 deletions(-)
create mode 100644 arch/powerpc/include/asm/set_memory.h
create mode 100644 arch/powerpc/mm/pageattr.c
--
2.25.1
^ permalink raw reply
* [PATCH v14 1/9] powerpc/mm: Implement set_memory() routines
From: Jordan Niethe @ 2021-05-17 3:28 UTC (permalink / raw)
To: linuxppc-dev
Cc: ajd, cmr, npiggin, aneesh.kumar, naveen.n.rao, Jordan Niethe, dja
In-Reply-To: <20210517032810.129949-1-jniethe5@gmail.com>
From: Russell Currey <ruscur@russell.cc>
The set_memory_{ro/rw/nx/x}() functions are required for
STRICT_MODULE_RWX, and are generally useful primitives to have. This
implementation is designed to be generic across powerpc's many MMUs.
It's possible that this could be optimised to be faster for specific
MMUs.
This implementation does not handle cases where the caller is attempting
to change the mapping of the page it is executing from, or if another
CPU is concurrently using the page being altered. These cases likely
shouldn't happen, but a more complex implementation with MMU-specific code
could safely handle them.
On hash, the linear mapping is not kept in the linux pagetable, so this
will not change the protection if used on that range. Currently these
functions are not used on the linear map so just WARN for now.
apply_to_existing_page_range() does not work on huge pages so for now
disallow changing the protection of huge pages.
Reviewed-by: Daniel Axtens <dja@axtens.net>
Signed-off-by: Russell Currey <ruscur@russell.cc>
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
[jpn: - Allow set memory functions to be used without Strict RWX
- Hash: Disallow certain regions
- Have change_page_attr() take function pointers to manipulate ptes
- Radix: Add ptesync after set_pte_at()]
Signed-off-by: Jordan Niethe <jniethe5@gmail.com>
---
v10: WARN if trying to change the hash linear map
v11: - Update copywrite dates
- Allow set memory functions to be used without Strict RWX
- Hash: Disallow certain regions and add comment explaining why
- Have change_page_attr() take function pointers to manipulate ptes
- Clarify change_page_attr()'s comment
- Radix: Add ptesync after set_pte_at()
v12: - change_page_attr() back to taking an action value
- disallow operating on huge pages
v14: - only check is_vm_area_hugepages() for virtual memory
---
arch/powerpc/Kconfig | 1 +
arch/powerpc/include/asm/set_memory.h | 32 ++++++++
arch/powerpc/mm/Makefile | 2 +-
arch/powerpc/mm/pageattr.c | 101 ++++++++++++++++++++++++++
4 files changed, 135 insertions(+), 1 deletion(-)
create mode 100644 arch/powerpc/include/asm/set_memory.h
create mode 100644 arch/powerpc/mm/pageattr.c
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 3f863dd21374..cce0a137b046 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -138,6 +138,7 @@ config PPC
select ARCH_HAS_MEMBARRIER_CALLBACKS
select ARCH_HAS_MEMBARRIER_SYNC_CORE
select ARCH_HAS_SCALED_CPUTIME if VIRT_CPU_ACCOUNTING_NATIVE && PPC_BOOK3S_64
+ select ARCH_HAS_SET_MEMORY
select ARCH_HAS_STRICT_KERNEL_RWX if ((PPC_BOOK3S_64 || PPC32) && !HIBERNATION)
select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
select ARCH_HAS_UACCESS_FLUSHCACHE
diff --git a/arch/powerpc/include/asm/set_memory.h b/arch/powerpc/include/asm/set_memory.h
new file mode 100644
index 000000000000..64011ea444b4
--- /dev/null
+++ b/arch/powerpc/include/asm/set_memory.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_POWERPC_SET_MEMORY_H
+#define _ASM_POWERPC_SET_MEMORY_H
+
+#define SET_MEMORY_RO 0
+#define SET_MEMORY_RW 1
+#define SET_MEMORY_NX 2
+#define SET_MEMORY_X 3
+
+int change_memory_attr(unsigned long addr, int numpages, long action);
+
+static inline int set_memory_ro(unsigned long addr, int numpages)
+{
+ return change_memory_attr(addr, numpages, SET_MEMORY_RO);
+}
+
+static inline int set_memory_rw(unsigned long addr, int numpages)
+{
+ return change_memory_attr(addr, numpages, SET_MEMORY_RW);
+}
+
+static inline int set_memory_nx(unsigned long addr, int numpages)
+{
+ return change_memory_attr(addr, numpages, SET_MEMORY_NX);
+}
+
+static inline int set_memory_x(unsigned long addr, int numpages)
+{
+ return change_memory_attr(addr, numpages, SET_MEMORY_X);
+}
+
+#endif
diff --git a/arch/powerpc/mm/Makefile b/arch/powerpc/mm/Makefile
index c3df3a8501d4..9142cf1fb0d5 100644
--- a/arch/powerpc/mm/Makefile
+++ b/arch/powerpc/mm/Makefile
@@ -5,7 +5,7 @@
ccflags-$(CONFIG_PPC64) := $(NO_MINIMAL_TOC)
-obj-y := fault.o mem.o pgtable.o mmap.o maccess.o \
+obj-y := fault.o mem.o pgtable.o mmap.o maccess.o pageattr.o \
init_$(BITS).o pgtable_$(BITS).o \
pgtable-frag.o ioremap.o ioremap_$(BITS).o \
init-common.o mmu_context.o drmem.o \
diff --git a/arch/powerpc/mm/pageattr.c b/arch/powerpc/mm/pageattr.c
new file mode 100644
index 000000000000..5e5ae50a7f23
--- /dev/null
+++ b/arch/powerpc/mm/pageattr.c
@@ -0,0 +1,101 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+ * MMU-generic set_memory implementation for powerpc
+ *
+ * Copyright 2019-2021, IBM Corporation.
+ */
+
+#include <linux/mm.h>
+#include <linux/vmalloc.h>
+#include <linux/set_memory.h>
+
+#include <asm/mmu.h>
+#include <asm/page.h>
+#include <asm/pgtable.h>
+
+
+/*
+ * Updates the attributes of a page in three steps:
+ *
+ * 1. invalidate the page table entry
+ * 2. flush the TLB
+ * 3. install the new entry with the updated attributes
+ *
+ * Invalidating the pte means there are situations where this will not work
+ * when in theory it should.
+ * For example:
+ * - removing write from page whilst it is being executed
+ * - setting a page read-only whilst it is being read by another CPU
+ *
+ */
+static int change_page_attr(pte_t *ptep, unsigned long addr, void *data)
+{
+ long action = (long)data;
+ pte_t pte;
+
+ spin_lock(&init_mm.page_table_lock);
+
+ /* invalidate the PTE so it's safe to modify */
+ pte = ptep_get_and_clear(&init_mm, addr, ptep);
+ flush_tlb_kernel_range(addr, addr + PAGE_SIZE);
+
+ /* modify the PTE bits as desired, then apply */
+ switch (action) {
+ case SET_MEMORY_RO:
+ pte = pte_wrprotect(pte);
+ break;
+ case SET_MEMORY_RW:
+ pte = pte_mkwrite(pte_mkdirty(pte));
+ break;
+ case SET_MEMORY_NX:
+ pte = pte_exprotect(pte);
+ break;
+ case SET_MEMORY_X:
+ pte = pte_mkexec(pte);
+ break;
+ default:
+ WARN_ON_ONCE(1);
+ break;
+ }
+
+ set_pte_at(&init_mm, addr, ptep, pte);
+
+ /* See ptesync comment in radix__set_pte_at() */
+ if (radix_enabled())
+ asm volatile("ptesync": : :"memory");
+ spin_unlock(&init_mm.page_table_lock);
+
+ return 0;
+}
+
+int change_memory_attr(unsigned long addr, int numpages, long action)
+{
+ unsigned long start = ALIGN_DOWN(addr, PAGE_SIZE);
+ unsigned long size = numpages * PAGE_SIZE;
+
+ if (!numpages)
+ return 0;
+
+ if (WARN_ON_ONCE(is_vmalloc_or_module_addr((void *)addr) &&
+ is_vm_area_hugepages((void *)addr)))
+ return -EINVAL;
+
+#ifdef CONFIG_PPC_BOOK3S_64
+ /*
+ * On hash, the linear mapping is not in the Linux page table so
+ * apply_to_existing_page_range() will have no effect. If in the future
+ * the set_memory_* functions are used on the linear map this will need
+ * to be updated.
+ */
+ if (!radix_enabled()) {
+ int region = get_region_id(addr);
+
+ if (WARN_ON_ONCE(region != VMALLOC_REGION_ID && region != IO_REGION_ID))
+ return -EINVAL;
+ }
+#endif
+
+ return apply_to_existing_page_range(&init_mm, start, size,
+ change_page_attr, (void *)action);
+}
--
2.25.1
^ permalink raw reply related
* [PATCH v14 2/9] powerpc/lib/code-patching: Set up Strict RWX patching earlier
From: Jordan Niethe @ 2021-05-17 3:28 UTC (permalink / raw)
To: linuxppc-dev
Cc: ajd, cmr, npiggin, aneesh.kumar, naveen.n.rao, Jordan Niethe, dja
In-Reply-To: <20210517032810.129949-1-jniethe5@gmail.com>
setup_text_poke_area() is a late init call so it runs before
mark_rodata_ro() and after the init calls. This lets all the init code
patching simply write to their locations. In the future, kprobes is
going to allocate its instruction pages RO which means they will need
setup_text__poke_area() to have been already called for their code
patching. However, init_kprobes() (which allocates and patches some
instruction pages) is an early init call so it happens before
setup_text__poke_area().
start_kernel() calls poking_init() before any of the init calls. On
powerpc, poking_init() is currently a nop. setup_text_poke_area() relies
on kernel virtual memory, cpu hotplug and per_cpu_areas being setup.
setup_per_cpu_areas(), boot_cpu_hotplug_init() and mm_init() are called
before poking_init().
Turn setup_text_poke_area() into poking_init().
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Reviewed-by: Russell Currey <ruscur@russell.cc>
Signed-off-by: Jordan Niethe <jniethe5@gmail.com>
---
v9: New to series
---
arch/powerpc/lib/code-patching.c | 12 ++++--------
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/arch/powerpc/lib/code-patching.c b/arch/powerpc/lib/code-patching.c
index 870b30d9be2f..15296207e1ba 100644
--- a/arch/powerpc/lib/code-patching.c
+++ b/arch/powerpc/lib/code-patching.c
@@ -70,14 +70,11 @@ static int text_area_cpu_down(unsigned int cpu)
}
/*
- * Run as a late init call. This allows all the boot time patching to be done
- * simply by patching the code, and then we're called here prior to
- * mark_rodata_ro(), which happens after all init calls are run. Although
- * BUG_ON() is rude, in this case it should only happen if ENOMEM, and we judge
- * it as being preferable to a kernel that will crash later when someone tries
- * to use patch_instruction().
+ * Although BUG_ON() is rude, in this case it should only happen if ENOMEM, and
+ * we judge it as being preferable to a kernel that will crash later when
+ * someone tries to use patch_instruction().
*/
-static int __init setup_text_poke_area(void)
+int __init poking_init(void)
{
BUG_ON(!cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
"powerpc/text_poke:online", text_area_cpu_up,
@@ -85,7 +82,6 @@ static int __init setup_text_poke_area(void)
return 0;
}
-late_initcall(setup_text_poke_area);
/*
* This can be called for kernel text or a module.
--
2.25.1
^ permalink raw reply related
* [PATCH v14 3/9] powerpc/modules: Make module_alloc() Strict Module RWX aware
From: Jordan Niethe @ 2021-05-17 3:28 UTC (permalink / raw)
To: linuxppc-dev
Cc: ajd, cmr, npiggin, aneesh.kumar, naveen.n.rao, Jordan Niethe, dja
In-Reply-To: <20210517032810.129949-1-jniethe5@gmail.com>
Make module_alloc() use PAGE_KERNEL protections instead of
PAGE_KERNEL_EXEX if Strict Module RWX is enabled.
Signed-off-by: Jordan Niethe <jniethe5@gmail.com>
---
v14: - Split out from powerpc: Set ARCH_HAS_STRICT_MODULE_RWX
- Add and use strict_module_rwx_enabled() helper
---
arch/powerpc/include/asm/mmu.h | 5 +++++
arch/powerpc/kernel/module.c | 4 +++-
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index 607168b1aef4..7710bf0cbf8a 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -357,6 +357,11 @@ static inline bool strict_kernel_rwx_enabled(void)
return false;
}
#endif
+
+static inline bool strict_module_rwx_enabled(void)
+{
+ return IS_ENABLED(CONFIG_STRICT_MODULE_RWX) && strict_kernel_rwx_enabled();
+}
#endif /* !__ASSEMBLY__ */
/* The kernel use the constants below to index in the page sizes array.
diff --git a/arch/powerpc/kernel/module.c b/arch/powerpc/kernel/module.c
index 3f35c8d20be7..ed04a3ba66fe 100644
--- a/arch/powerpc/kernel/module.c
+++ b/arch/powerpc/kernel/module.c
@@ -92,12 +92,14 @@ int module_finalize(const Elf_Ehdr *hdr,
static __always_inline void *
__module_alloc(unsigned long size, unsigned long start, unsigned long end)
{
+ pgprot_t prot = strict_module_rwx_enabled() ? PAGE_KERNEL : PAGE_KERNEL_EXEC;
+
/*
* Don't do huge page allocations for modules yet until more testing
* is done. STRICT_MODULE_RWX may require extra work to support this
* too.
*/
- return __vmalloc_node_range(size, 1, start, end, GFP_KERNEL, PAGE_KERNEL_EXEC,
+ return __vmalloc_node_range(size, 1, start, end, GFP_KERNEL, prot,
VM_FLUSH_RESET_PERMS | VM_NO_HUGE_VMAP,
NUMA_NO_NODE, __builtin_return_address(0));
}
--
2.25.1
^ permalink raw reply related
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