* [PATCH] powerpc/syscalls: Simplify do_mmap2()
From: Christophe Leroy @ 2021-06-25 10:58 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman
Cc: linuxppc-dev, linux-kernel
When shift is nul, operations remain valid so no test needed.
And 'ret' is unnecessary.
And use IS_ALIGNED() to check alignment, that's more clear.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
---
arch/powerpc/kernel/syscalls.c | 15 ++++-----------
1 file changed, 4 insertions(+), 11 deletions(-)
diff --git a/arch/powerpc/kernel/syscalls.c b/arch/powerpc/kernel/syscalls.c
index bf4ae0f0e36c..825931e400df 100644
--- a/arch/powerpc/kernel/syscalls.c
+++ b/arch/powerpc/kernel/syscalls.c
@@ -41,20 +41,13 @@ static inline long do_mmap2(unsigned long addr, size_t len,
unsigned long prot, unsigned long flags,
unsigned long fd, unsigned long off, int shift)
{
- long ret = -EINVAL;
-
if (!arch_validate_prot(prot, addr))
- goto out;
+ return -EINVAL;
- if (shift) {
- if (off & ((1 << shift) - 1))
- goto out;
- off >>= shift;
- }
+ if (!IS_ALIGNED(off, 1 << shift))
+ return -EINVAL;
- ret = ksys_mmap_pgoff(addr, len, prot, flags, fd, off);
-out:
- return ret;
+ return ksys_mmap_pgoff(addr, len, prot, flags, fd, off >> shift);
}
SYSCALL_DEFINE6(mmap2, unsigned long, addr, size_t, len,
--
2.25.0
^ permalink raw reply related
* [PATCH 1/2] powerpc/ptrace: Move set_return_regs_changed() before regs_set_return_{msr/ip}
From: Christophe Leroy @ 2021-06-25 11:13 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman
Cc: linuxppc-dev, linux-kernel
regs_set_return_msr() and regs_set_return_ip() have a copy
of the code of set_return_regs_changed().
Move up set_return_regs_changed() so it can be reused by
regs_set_return_{msr/ip}
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
---
arch/powerpc/include/asm/ptrace.h | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/include/asm/ptrace.h b/arch/powerpc/include/asm/ptrace.h
index fcf63f559344..14b8105a1e27 100644
--- a/arch/powerpc/include/asm/ptrace.h
+++ b/arch/powerpc/include/asm/ptrace.h
@@ -135,26 +135,26 @@ extern unsigned long profile_pc(struct pt_regs *regs);
long do_syscall_trace_enter(struct pt_regs *regs);
void do_syscall_trace_leave(struct pt_regs *regs);
-static inline void regs_set_return_ip(struct pt_regs *regs, unsigned long ip)
+static inline void set_return_regs_changed(void)
{
- regs->nip = ip;
#ifdef CONFIG_PPC_BOOK3S_64
local_paca->hsrr_valid = 0;
local_paca->srr_valid = 0;
#endif
}
-static inline void regs_set_return_msr(struct pt_regs *regs, unsigned long msr)
+static inline void regs_set_return_ip(struct pt_regs *regs, unsigned long ip)
{
- regs->msr = msr;
+ regs->nip = ip;
#ifdef CONFIG_PPC_BOOK3S_64
local_paca->hsrr_valid = 0;
local_paca->srr_valid = 0;
#endif
}
-static inline void set_return_regs_changed(void)
+static inline void regs_set_return_msr(struct pt_regs *regs, unsigned long msr)
{
+ regs->msr = msr;
#ifdef CONFIG_PPC_BOOK3S_64
local_paca->hsrr_valid = 0;
local_paca->srr_valid = 0;
--
2.25.0
^ permalink raw reply related
* [PATCH 2/2] powerpc/ptrace: Refactor regs_set_return_{msr/ip}
From: Christophe Leroy @ 2021-06-25 11:13 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman
Cc: linuxppc-dev, linux-kernel
In-Reply-To: <49f4fb051a3e1cb69f7305d5b6768aec14727c32.1624619582.git.christophe.leroy@csgroup.eu>
regs_set_return_msr() and regs_set_return_ip() have a copy
of the code of set_return_regs_changed().
Call the later instead.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
---
arch/powerpc/include/asm/ptrace.h | 10 ++--------
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/arch/powerpc/include/asm/ptrace.h b/arch/powerpc/include/asm/ptrace.h
index 14b8105a1e27..3e5d470a6155 100644
--- a/arch/powerpc/include/asm/ptrace.h
+++ b/arch/powerpc/include/asm/ptrace.h
@@ -146,19 +146,13 @@ static inline void set_return_regs_changed(void)
static inline void regs_set_return_ip(struct pt_regs *regs, unsigned long ip)
{
regs->nip = ip;
-#ifdef CONFIG_PPC_BOOK3S_64
- local_paca->hsrr_valid = 0;
- local_paca->srr_valid = 0;
-#endif
+ set_return_regs_changed();
}
static inline void regs_set_return_msr(struct pt_regs *regs, unsigned long msr)
{
regs->msr = msr;
-#ifdef CONFIG_PPC_BOOK3S_64
- local_paca->hsrr_valid = 0;
- local_paca->srr_valid = 0;
-#endif
+ set_return_regs_changed();
}
static inline void regs_add_return_ip(struct pt_regs *regs, long offset)
--
2.25.0
^ permalink raw reply related
* [PATCH] ASoC: fsl: fsl_easrc: remove unnecessary print function dev_err()
From: 13145886936 @ 2021-06-25 11:58 UTC (permalink / raw)
To: timur, nicoleotsuka, Xiubo.Lee, perex, tiwai, alsa-devel
Cc: linuxppc-dev, linux-kernel, gushengxian
From: gushengxian <gushengxian@yulong.com>
The print function dev_err() is redundant because
platform_get_irq() already prints an error.
Signed-off-by: gushengxian <gushengxian@yulong.com>
---
sound/soc/fsl/fsl_easrc.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/sound/soc/fsl/fsl_easrc.c b/sound/soc/fsl/fsl_easrc.c
index b1765c7d3bcd..25747433916e 100644
--- a/sound/soc/fsl/fsl_easrc.c
+++ b/sound/soc/fsl/fsl_easrc.c
@@ -1901,10 +1901,8 @@ static int fsl_easrc_probe(struct platform_device *pdev)
}
irq = platform_get_irq(pdev, 0);
- if (irq < 0) {
- dev_err(dev, "no irq for node %pOF\n", np);
+ if (irq < 0)
return irq;
- }
ret = devm_request_irq(&pdev->dev, irq, fsl_easrc_isr, 0,
dev_name(dev), easrc);
--
2.25.1
^ permalink raw reply related
* [PATCH] perf vendor events power10: Adds 24x7 nest metric events for power10 platform
From: Kajol Jain @ 2021-06-25 11:59 UTC (permalink / raw)
To: acme
Cc: ravi.bangoria, atrajeev, rnsastry, kjain, linuxppc-dev,
linux-kernel, linux-perf-users, maddy, pc, jolsa
Patch adds 24x7 nest metric events for POWER10.
Signed-off-by: Kajol Jain <kjain@linux.ibm.com>
---
.../arch/powerpc/power10/nest_metrics.json | 491 ++++++++++++++++++
1 file changed, 491 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/powerpc/power10/nest_metrics.json
diff --git a/tools/perf/pmu-events/arch/powerpc/power10/nest_metrics.json b/tools/perf/pmu-events/arch/powerpc/power10/nest_metrics.json
new file mode 100644
index 000000000000..b79046cd8b09
--- /dev/null
+++ b/tools/perf/pmu-events/arch/powerpc/power10/nest_metrics.json
@@ -0,0 +1,491 @@
+[
+ {
+ "MetricName": "VEC_GROUP_PUMP_RETRY_RATIO_P01",
+ "BriefDescription": "VEC_GROUP_PUMP_RETRY_RATIO_P01",
+ "MetricExpr": "(hv_24x7@PM_PB_RTY_VG_PUMP01\\,chip\\=?@ / hv_24x7@PM_PB_VG_PUMP01\\,chip\\=?@) * 100",
+ "ScaleUnit": "1%",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "VEC_GROUP_PUMP_RETRY_RATIO_P23",
+ "BriefDescription": "VEC_GROUP_PUMP_RETRY_RATIO_P23",
+ "MetricExpr": "(hv_24x7@PM_PB_RTY_VG_PUMP23\\,chip\\=?@ / hv_24x7@PM_PB_VG_PUMP23\\,chip\\=?@) * 100",
+ "ScaleUnit": "1%",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "LOCAL_NODE_PUMP_RETRY_RATIO_P01",
+ "BriefDescription": "LOCAL_NODE_PUMP_RETRY_RATIO_P01",
+ "MetricExpr": "(hv_24x7@PM_PB_RTY_LNS_PUMP01\\,chip\\=?@ / hv_24x7@PM_PB_LNS_PUMP01\\,chip\\=?@) * 100",
+ "ScaleUnit": "1%",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "LOCAL_NODE_PUMP_RETRY_RATIO_P23",
+ "BriefDescription": "LOCAL_NODE_PUMP_RETRY_RATIO_P23",
+ "MetricExpr": "(hv_24x7@PM_PB_RTY_LNS_PUMP23\\,chip\\=?@ / hv_24x7@PM_PB_LNS_PUMP23\\,chip\\=?@) * 100",
+ "ScaleUnit": "1%",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "GROUP_PUMP_RETRY_RATIO_P01",
+ "BriefDescription": "GROUP_PUMP_RETRY_RATIO_P01",
+ "MetricExpr": "(hv_24x7@PM_PB_RTY_GROUP_PUMP01\\,chip\\=?@ / hv_24x7@PM_PB_GROUP_PUMP01\\,chip\\=?@) * 100",
+ "ScaleUnit": "1%",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "GROUP_PUMP_RETRY_RATIO_P23",
+ "BriefDescription": "GROUP_PUMP_RETRY_RATIO_P23",
+ "MetricExpr": "(hv_24x7@PM_PB_RTY_GROUP_PUMP23\\,chip\\=?@ / hv_24x7@PM_PB_GROUP_PUMP23\\,chip\\=?@) * 100",
+ "ScaleUnit": "1%",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "TOTAL_GROUP_PUMPS_P01",
+ "BriefDescription": "TOTAL_GROUP_PUMPS_P01(PER-CYC)",
+ "MetricExpr": "(hv_24x7@PM_PB_GROUP_PUMP01\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
+ "ScaleUnit": "4",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "TOTAL_GROUP_PUMPS_P23",
+ "BriefDescription": "TOTAL_GROUP_PUMPS_P23(PER-CYC)",
+ "MetricExpr": "(hv_24x7@PM_PB_GROUP_PUMP23\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
+ "ScaleUnit": "4",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "TOTAL_GROUP_PUMPS_RETRIES_P01",
+ "BriefDescription": "TOTAL_GROUP_PUMPS_RETRIES_P01(PER-CYC)",
+ "MetricExpr": "(hv_24x7@PM_PB_RTY_GROUP_PUMP01\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
+ "ScaleUnit": "4",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "TOTAL_GROUP_PUMPS_RETRIES_P23",
+ "BriefDescription": "TOTAL_GROUP_PUMPS_RETRIES_P23(PER-CYC)",
+ "MetricExpr": "(hv_24x7@PM_PB_RTY_GROUP_PUMP23\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
+ "ScaleUnit": "4",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "REMOTE_NODE_PUMPS_RETRIES_RATIO_P01",
+ "BriefDescription": "REMOTE_NODE_PUMPS_RETRIES_RATIO_P01",
+ "MetricExpr": "(hv_24x7@PM_PB_RTY_RNS_PUMP01\\,chip\\=?@ / hv_24x7@PM_PB_RNS_PUMP01\\,chip\\=?@) * 100",
+ "ScaleUnit": "1%",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "REMOTE_NODE_PUMPS_RETRIES_RATIO_P23",
+ "BriefDescription": "REMOTE_NODE_PUMPS_RETRIES_RATIO_P23",
+ "MetricExpr": "(hv_24x7@PM_PB_RTY_RNS_PUMP23\\,chip\\=?@ / hv_24x7@PM_PB_RNS_PUMP23\\,chip\\=?@) * 100",
+ "ScaleUnit": "1%",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "TOTAL_VECTOR_GROUP_PUMPS_P01",
+ "BriefDescription": "TOTAL_VECTOR_GROUP_PUMPS_P01(PER-CYC)",
+ "MetricExpr": "(hv_24x7@PM_PB_VG_PUMP01\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
+ "ScaleUnit": "4",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "TOTAL_VECTOR_GROUP_PUMPS_P23",
+ "BriefDescription": "TOTAL_VECTOR_GROUP_PUMPS_P23(PER-CYC)",
+ "MetricExpr": "(hv_24x7@PM_PB_VG_PUMP23\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
+ "ScaleUnit": "4",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "TOTAL_LOCAL_NODE_PUMPS_P01",
+ "BriefDescription": "TOTAL_LOCAL_NODE_PUMPS_P01(PER-CYC)",
+ "MetricExpr": "(hv_24x7@PM_PB_LNS_PUMP01\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
+ "ScaleUnit": "4",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "TOTAL_LOCAL_NODE_PUMPS_P23",
+ "BriefDescription": "TOTAL_LOCAL_NODE_PUMPS_P23(PER-CYC)",
+ "MetricExpr": "(hv_24x7@PM_PB_LNS_PUMP23\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
+ "ScaleUnit": "4",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "TOTAL_VECTOR_GROUP_PUMPS_RETRIES_P01",
+ "BriefDescription": "TOTAL_VECTOR_GROUP_PUMPS_RETRIES_P01(PER-CYC)",
+ "MetricExpr": "(hv_24x7@PM_PB_RTY_VG_PUMP01\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
+ "ScaleUnit": "4",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "TOTAL_VECTOR_GROUP_PUMPS_RETRIES_P23",
+ "BriefDescription": "TOTAL_VECTOR_GROUP_PUMPS_RETRIES_P23(PER-CYC)",
+ "MetricExpr": "(hv_24x7@PM_PB_RTY_VG_PUMP23\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
+ "ScaleUnit": "4",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "TOTAL_LOCAL_NODE_PUMPS_RETRIES_P01",
+ "BriefDescription": "TOTAL_LOCAL_NODE_PUMPS_RETRIES_P01(PER-CYC)",
+ "MetricExpr": "(hv_24x7@PM_PB_RTY_LNS_PUMP01\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
+ "ScaleUnit": "4",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "TOTAL_LOCAL_NODE_PUMPS_RETRIES_P23",
+ "BriefDescription": "TOTAL_LOCAL_NODE_PUMPS_RETRIES_P23(PER-CYC)",
+ "MetricExpr": "(hv_24x7@PM_PB_RTY_LNS_PUMP23\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
+ "ScaleUnit": "4",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "TOTAL_REMOTE_NODE_PUMPS_P01",
+ "BriefDescription": "TOTAL_REMOTE_NODE_PUMPS_P01",
+ "MetricExpr": "(hv_24x7@PM_PB_RNS_PUMP01\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
+ "ScaleUnit": "4",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "TOTAL_REMOTE_NODE_PUMPS_P23",
+ "BriefDescription": "TOTAL_REMOTE_NODE_PUMPS_P23",
+ "MetricExpr": "(hv_24x7@PM_PB_RNS_PUMP23\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
+ "ScaleUnit": "4",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "TOTAL_NEAR_NODE_PUMPS_P01",
+ "BriefDescription": "TOTAL_NEAR_NODE_PUMPS_P01",
+ "MetricExpr": "(hv_24x7@PM_PB_NNS_PUMP01\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
+ "ScaleUnit": "4",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "TOTAL_NEAR_NODE_PUMPS_P23",
+ "BriefDescription": "TOTAL_NEAR_NODE_PUMPS_P23",
+ "MetricExpr": "(hv_24x7@PM_PB_NNS_PUMP23\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
+ "ScaleUnit": "4",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "TOTAL_INT_PB_BW",
+ "BriefDescription": "TOTAL_INT_PB_BW",
+ "MetricExpr": "(hv_24x7@PM_PB_INT_DATA_XFER\\,chip\\=?@)",
+ "ScaleUnit": "2.09MB",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "XLINK0_OUT_TOTAL_UTILIZATION",
+ "BriefDescription": "XLINK0_OUT_TOTAL_UTILIZATION",
+ "MetricExpr": "((hv_24x7@PM_XLINK0_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_XLINK0_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_XLINK0_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK0_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
+ "ScaleUnit": "1%",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "XLINK1_OUT_TOTAL_UTILIZATION",
+ "BriefDescription": "XLINK1_OUT_TOTAL_UTILIZATION",
+ "MetricExpr": "((hv_24x7@PM_XLINK1_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_XLINK1_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_XLINK1_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK1_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
+ "ScaleUnit": "1%",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "XLINK2_OUT_TOTAL_UTILIZATION",
+ "BriefDescription": "XLINK2_OUT_TOTAL_UTILIZATION",
+ "MetricExpr": "((hv_24x7@PM_XLINK2_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_XLINK2_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_XLINK2_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK2_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
+ "ScaleUnit": "1%",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "XLINK3_OUT_TOTAL_UTILIZATION",
+ "BriefDescription": "XLINK3_OUT_TOTAL_UTILIZATION",
+ "MetricExpr": "((hv_24x7@PM_XLINK3_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_XLINK3_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_XLINK3_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK3_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
+ "ScaleUnit": "1%",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "XLINK4_OUT_TOTAL_UTILIZATION",
+ "BriefDescription": "XLINK4_OUT_TOTAL_UTILIZATION",
+ "MetricExpr": "((hv_24x7@PM_XLINK4_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_XLINK4_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_XLINK4_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK4_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
+ "ScaleUnit": "1%",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "XLINK5_OUT_TOTAL_UTILIZATION",
+ "BriefDescription": "XLINK5_OUT_TOTAL_UTILIZATION",
+ "MetricExpr": "((hv_24x7@PM_XLINK5_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_XLINK5_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_XLINK5_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK5_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
+ "ScaleUnit": "1%",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "XLINK6_OUT_TOTAL_UTILIZATION",
+ "BriefDescription": "XLINK6_OUT_TOTAL_UTILIZATION",
+ "MetricExpr": "((hv_24x7@PM_XLINK6_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_XLINK6_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_XLINK6_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK6_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
+ "ScaleUnit": "1%",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "XLINK7_OUT_TOTAL_UTILIZATION",
+ "BriefDescription": "XLINK7_OUT_TOTAL_UTILIZATION",
+ "MetricExpr": "((hv_24x7@PM_XLINK7_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_XLINK7_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_XLINK7_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK7_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
+ "ScaleUnit": "1%",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "XLINK0_OUT_DATA_UTILIZATION",
+ "BriefDescription": "XLINK0_OUT_DATA_UTILIZATION",
+ "MetricExpr": "((hv_24x7@PM_XLINK0_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_XLINK0_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_XLINK0_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK0_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
+ "ScaleUnit": "1.063%",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "XLINK1_OUT_DATA_UTILIZATION",
+ "BriefDescription": "XLINK1_OUT_DATA_UTILIZATION",
+ "MetricExpr": "((hv_24x7@PM_XLINK1_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_XLINK1_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_XLINK1_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK1_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
+ "ScaleUnit": "1.063%",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "XLINK2_OUT_DATA_UTILIZATION",
+ "BriefDescription": "XLINK2_OUT_DATA_UTILIZATION",
+ "MetricExpr": "((hv_24x7@PM_XLINK2_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_XLINK2_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_XLINK2_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK2_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
+ "ScaleUnit": "1.063%",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "XLINK3_OUT_DATA_UTILIZATION",
+ "BriefDescription": "XLINK3_OUT_DATA_UTILIZATION",
+ "MetricExpr": "((hv_24x7@PM_XLINK3_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_XLINK3_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_XLINK3_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK3_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
+ "ScaleUnit": "1.063%",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "XLINK4_OUT_DATA_UTILIZATION",
+ "BriefDescription": "XLINK4_OUT_DATA_UTILIZATION",
+ "MetricExpr": "((hv_24x7@PM_XLINK4_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_XLINK4_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_XLINK4_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK4_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
+ "ScaleUnit": "1.063%",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "XLINK5_OUT_DATA_UTILIZATION",
+ "BriefDescription": "XLINK5_OUT_DATA_UTILIZATION",
+ "MetricExpr": "((hv_24x7@PM_XLINK5_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_XLINK5_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_XLINK5_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK5_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
+ "ScaleUnit": "1.063%",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "XLINK6_OUT_DATA_UTILIZATION",
+ "BriefDescription": "XLINK6_OUT_DATA_UTILIZATION",
+ "MetricExpr": "((hv_24x7@PM_XLINK6_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_XLINK6_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_XLINK6_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK6_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
+ "ScaleUnit": "1.063%",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "XLINK7_OUT_DATA_UTILIZATION",
+ "BriefDescription": "XLINK7_OUT_DATA_UTILIZATION",
+ "MetricExpr": "((hv_24x7@PM_XLINK7_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_XLINK7_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_XLINK7_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK7_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
+ "ScaleUnit": "1.063%",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "ALINK0_OUT_TOTAL_UTILIZATION",
+ "BriefDescription": "ALINK0_OUT_TOTAL_UTILIZATION",
+ "MetricExpr": "((hv_24x7@PM_ALINK0_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_ALINK0_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_ALINK0_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK0_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
+ "ScaleUnit": "1%",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "ALINK1_OUT_TOTAL_UTILIZATION",
+ "BriefDescription": "ALINK1_OUT_TOTAL_UTILIZATION",
+ "MetricExpr": "((hv_24x7@PM_ALINK1_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_ALINK1_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_ALINK1_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK1_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
+ "ScaleUnit": "1%",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "ALINK2_OUT_TOTAL_UTILIZATION",
+ "BriefDescription": "ALINK2_OUT_TOTAL_UTILIZATION",
+ "MetricExpr": "((hv_24x7@PM_ALINK2_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_ALINK2_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_ALINK2_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK2_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
+ "ScaleUnit": "1%",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "ALINK3_OUT_TOTAL_UTILIZATION",
+ "BriefDescription": "ALINK3_OUT_TOTAL_UTILIZATION",
+ "MetricExpr": "((hv_24x7@PM_ALINK3_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_ALINK3_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_ALINK3_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK3_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
+ "ScaleUnit": "1%",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "ALINK4_OUT_TOTAL_UTILIZATION",
+ "BriefDescription": "ALINK4_OUT_TOTAL_UTILIZATION",
+ "MetricExpr": "((hv_24x7@PM_ALINK4_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_ALINK4_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_ALINK4_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK4_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
+ "ScaleUnit": "1%",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "ALINK5_OUT_TOTAL_UTILIZATION",
+ "BriefDescription": "ALINK5_OUT_TOTAL_UTILIZATION",
+ "MetricExpr": "((hv_24x7@PM_ALINK5_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_ALINK5_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_ALINK5_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK5_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
+ "ScaleUnit": "1%",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "ALINK6_OUT_TOTAL_UTILIZATION",
+ "BriefDescription": "ALINK6_OUT_TOTAL_UTILIZATION",
+ "MetricExpr": "((hv_24x7@PM_ALINK6_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_ALINK6_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_ALINK6_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK6_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
+ "ScaleUnit": "1%",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "ALINK7_OUT_TOTAL_UTILIZATION",
+ "BriefDescription": "ALINK7_OUT_TOTAL_UTILIZATION",
+ "MetricExpr": "((hv_24x7@PM_ALINK7_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_ALINK7_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_ALINK7_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK7_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
+ "ScaleUnit": "1%",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "ALINK0_OUT_DATA_UTILIZATION",
+ "BriefDescription": "ALINK0_OUT_DATA_UTILIZATION",
+ "MetricExpr": "((hv_24x7@PM_ALINK0_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_ALINK0_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_ALINK0_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK0_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
+ "ScaleUnit": "1.063%",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "ALINK1_OUT_DATA_UTILIZATION",
+ "BriefDescription": "ALINK1_OUT_DATA_UTILIZATION",
+ "MetricExpr": "((hv_24x7@PM_ALINK1_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_ALINK1_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_ALINK1_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK1_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
+ "ScaleUnit": "1.063%",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "ALINK2_OUT_DATA_UTILIZATION",
+ "BriefDescription": "ALINK2_OUT_DATA_UTILIZATION",
+ "MetricExpr": "((hv_24x7@PM_ALINK2_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_ALINK2_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_ALINK2_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK2_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
+ "ScaleUnit": "1.063%",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "ALINK3_OUT_DATA_UTILIZATION",
+ "BriefDescription": "ALINK3_OUT_DATA_UTILIZATION",
+ "MetricExpr": "((hv_24x7@PM_ALINK3_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_ALINK3_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_ALINK3_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK3_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
+ "ScaleUnit": "1.063%",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "ALINK4_OUT_DATA_UTILIZATION",
+ "BriefDescription": "ALINK4_OUT_DATA_UTILIZATION",
+ "MetricExpr": "((hv_24x7@PM_ALINK4_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_ALINK4_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_ALINK4_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK4_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
+ "ScaleUnit": "1.063%",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "ALINK5_OUT_DATA_UTILIZATION",
+ "BriefDescription": "ALINK5_OUT_DATA_UTILIZATION",
+ "MetricExpr": "((hv_24x7@PM_ALINK5_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_ALINK5_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_ALINK5_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK5_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
+ "ScaleUnit": "1.063%",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "ALINK6_OUT_DATA_UTILIZATION",
+ "BriefDescription": "ALINK6_OUT_DATA_UTILIZATION",
+ "MetricExpr": "((hv_24x7@PM_ALINK6_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_ALINK6_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_ALINK6_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK6_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
+ "ScaleUnit": "1.063%",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "ALINK7_OUT_DATA_UTILIZATION",
+ "BriefDescription": "ALINK7_OUT_DATA_UTILIZATION",
+ "MetricExpr": "((hv_24x7@PM_ALINK7_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_ALINK7_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_ALINK7_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK7_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
+ "ScaleUnit": "1.063%",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "TOTAL_DATA_BANDWIDTH_TRANSFERRED_OVER_PB_PCI1",
+ "BriefDescription": "TOTAL_DATA_BANDWIDTH_TRANSFERRED_OVER_PB_PCI1",
+ "MetricExpr": "(hv_24x7@PM_PCI1_32B_INOUT\\,chip\\=?@)",
+ "ScaleUnit": "3.28e-2MB",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "TOTAL_DATA_BANDWIDTH_TRANSFERRED_OVER_PB_PCI0",
+ "BriefDescription": "TOTAL_DATA_BANDWIDTH_TRANSFERRED_OVER_PB_PCI0",
+ "MetricExpr": "(hv_24x7@PM_PCI0_32B_INOUT\\,chip\\=?@)",
+ "ScaleUnit": "3.28e-2MB",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "TOTAL_MCS_READ_BW_MC0_CHAN01",
+ "BriefDescription": "TOTAL_MCS_READ_BW_MC0_CHAN01",
+ "MetricExpr": "(hv_24x7@PM_MCS_128B_RD_DATA_BLOCKS_MC0_CHAN01\\,chip\\=?@)",
+ "ScaleUnit": "5.24e-1MB",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "TOTAL_MCS_READ_BW_MC1_CHAN01",
+ "BriefDescription": "TOTAL_MCS_READ_BW_MC1_CHAN01",
+ "MetricExpr": "(hv_24x7@PM_MCS_128B_RD_DATA_BLOCKS_MC1_CHAN01\\,chip\\=?@)",
+ "ScaleUnit": "5.24e-1MB",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "TOTAL_MCS_READ_BW_MC2_CHAN01",
+ "BriefDescription": "TOTAL_MCS_READ_BW_MC2_CHAN01",
+ "MetricExpr": "(hv_24x7@PM_MCS_128B_RD_DATA_BLOCKS_MC2_CHAN01\\,chip\\=?@)",
+ "ScaleUnit": "5.24e-1MB",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "TOTAL_MCS_READ_BW_MC3_CHAN01",
+ "BriefDescription": "TOTAL_MCS_READ_BW_MC3_CHAN01",
+ "MetricExpr": "(hv_24x7@PM_MCS_128B_RD_DATA_BLOCKS_MC3_CHAN01\\,chip\\=?@)",
+ "ScaleUnit": "5.24e-1MB",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "TOTAL_MCS_WRITE_BW_MC0_CHAN01",
+ "BriefDescription": "TOTAL_MCS_WRITE_BW_MC0_CHAN01",
+ "MetricExpr": "(hv_24x7@PM_MCS_64B_WR_DATA_BLOCKS_MC0_CHAN01\\,chip\\=?@)",
+ "ScaleUnit": "2.6e-1MB",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "TOTAL_MCS_WRITE_BW_MC1_CHAN01",
+ "BriefDescription": "TOTAL_MCS_WRITE_BW_MC1_CHAN01",
+ "MetricExpr": "(hv_24x7@PM_MCS_64B_WR_DATA_BLOCKS_MC1_CHAN01\\,chip\\=?@)",
+ "ScaleUnit": "2.6e-1MB",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "TOTAL_MCS_WRITE_BW_MC2_CHAN01",
+ "BriefDescription": "TOTAL_MCS_WRITE_BW_MC2_CHAN01",
+ "MetricExpr": "(hv_24x7@PM_MCS_64B_WR_DATA_BLOCKS_MC2_CHAN01\\,chip\\=?@)",
+ "ScaleUnit": "2.6e-1MB",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricName": "TOTAL_MCS_WRITE_BW_MC3_CHAN01",
+ "BriefDescription": "TOTAL_MCS_WRITE_BW_MC3_CHAN01",
+ "MetricExpr": "(hv_24x7@PM_MCS_64B_WR_DATA_BLOCKS_MC3_CHAN01\\,chip\\=?@)",
+ "ScaleUnit": "2.6e-1MB",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricExpr": "(hv_24x7@PM_MCS_128B_RD_DATA_BLOCKS_MC0_CHAN01\\,chip\\=?@ + hv_24x7@PM_MCS_128B_RD_DATA_BLOCKS_MC1_CHAN01\\,chip\\=?@ + hv_24x7@PM_MCS_128B_RD_DATA_BLOCKS_MC2_CHAN01\\,chip\\=?@ + hv_24x7@PM_MCS_128B_RD_DATA_BLOCKS_MC3_CHAN01\\,chip\\=?@)",
+ "MetricName": "Memory_RD_BW_Chip",
+ "MetricGroup": "Memory_BW",
+ "ScaleUnit": "5.24e-1MB",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricExpr": "(hv_24x7@PM_MCS_64B_WR_DATA_BLOCKS_MC0_CHAN01\\,chip\\=?@ + hv_24x7@PM_MCS_64B_WR_DATA_BLOCKS_MC1_CHAN01\\,chip\\=?@ + hv_24x7@PM_MCS_64B_WR_DATA_BLOCKS_MC2_CHAN01\\,chip\\=?@ + hv_24x7@PM_MCS_64B_WR_DATA_BLOCKS_MC3_CHAN01\\,chip\\=?@ )",
+ "MetricName": "Memory_WR_BW_Chip",
+ "MetricGroup": "Memory_BW",
+ "ScaleUnit": "2.6e-1MB",
+ "AggregationMode": "PerChip"
+ },
+ {
+ "MetricExpr": "(hv_24x7@PM_PAU_CYC\\,chip\\=?@ )",
+ "MetricName": "PowerBUS_Frequency",
+ "ScaleUnit": "2.56e-7GHz",
+ "AggregationMode": "PerChip"
+ }
+]
--
2.27.0
^ permalink raw reply related
* [PATCH] ASoC: fsl_spdif: remove unnecessary print function dev_err()
From: 13145886936 @ 2021-06-25 12:12 UTC (permalink / raw)
To: timur, nicoleotsuka, Xiubo.Lee, perex, tiwai, alsa-devel
Cc: linuxppc-dev, linux-kernel, gushengxian
From: gushengxian <gushengxian@yulong.com>
The print function dev_err() is redundant because
platform_get_irq() already prints an error.
Signed-off-by: gushengxian <gushengxian@yulong.com>
---
sound/soc/fsl/fsl_spdif.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/sound/soc/fsl/fsl_spdif.c b/sound/soc/fsl/fsl_spdif.c
index c631de325a6e..02b750fc32d8 100644
--- a/sound/soc/fsl/fsl_spdif.c
+++ b/sound/soc/fsl/fsl_spdif.c
@@ -1302,10 +1302,8 @@ static int fsl_spdif_probe(struct platform_device *pdev)
for (i = 0; i < spdif_priv->soc->interrupts; i++) {
irq = platform_get_irq(pdev, i);
- if (irq < 0) {
- dev_err(&pdev->dev, "no irq for node %s\n", pdev->name);
+ if (irq < 0)
return irq;
- }
ret = devm_request_irq(&pdev->dev, irq, spdif_isr, 0,
dev_name(&pdev->dev), spdif_priv);
--
2.25.1
^ permalink raw reply related
* [PATCH] ASoC: fsl_xcvr: remove unnecessary print function dev_err()
From: 13145886936 @ 2021-06-25 12:16 UTC (permalink / raw)
To: timur, nicoleotsuka, Xiubo.Lee, perex, tiwai, alsa-devel
Cc: linuxppc-dev, linux-kernel, gushengxian
From: gushengxian <gushengxian@yulong.com>
The print function dev_err() is redundant because
platform_get_irq() already prints an error.
Signed-off-by: gushengxian <gushengxian@yulong.com>
---
sound/soc/fsl/fsl_xcvr.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/sound/soc/fsl/fsl_xcvr.c b/sound/soc/fsl/fsl_xcvr.c
index 6cb558165848..e34d57ad66fb 100644
--- a/sound/soc/fsl/fsl_xcvr.c
+++ b/sound/soc/fsl/fsl_xcvr.c
@@ -1189,10 +1189,8 @@ static int fsl_xcvr_probe(struct platform_device *pdev)
/* get IRQs */
irq = platform_get_irq(pdev, 0);
- if (irq < 0) {
- dev_err(dev, "no irq[0]: %d\n", irq);
+ if (irq < 0)
return irq;
- }
ret = devm_request_irq(dev, irq, irq0_isr, 0, pdev->name, xcvr);
if (ret) {
--
2.25.1
^ permalink raw reply related
* Re: [PATCH v15 00/12] Restricted DMA
From: Will Deacon @ 2021-06-25 12:30 UTC (permalink / raw)
To: Konrad Rzeszutek Wilk
Cc: heikki.krogerus, thomas.hellstrom, peterz, joonas.lahtinen,
dri-devel, chris, grant.likely, paulus, Frank Rowand, mingo,
Marek Szyprowski, sstabellini, Saravana Kannan, Joerg Roedel,
Rafael J . Wysocki, Christoph Hellwig, Bartosz Golaszewski,
bskeggs, linux-pci, xen-devel, Thierry Reding, intel-gfx,
matthew.auld, linux-devicetree, jxgao, daniel, maarten.lankhorst,
airlied, Dan Williams, linuxppc-dev, jani.nikula, Rob Herring,
rodrigo.vivi, bhelgaas, Claire Chang, boris.ostrovsky,
Andy Shevchenko, jgross, Nicolas Boichat, Greg KH, Randy Dunlap,
quic_qiancai, lkml, tfiga, list@263.net:IOMMU DRIVERS,
Jim Quinlan, xypron.glpk, thomas.lendacky, Robin Murphy, bauerman
In-Reply-To: <YNTa1C5uvz+qWryf@char.us.oracle.com>
On Thu, Jun 24, 2021 at 03:19:48PM -0400, Konrad Rzeszutek Wilk wrote:
> On Thu, Jun 24, 2021 at 11:55:14PM +0800, Claire Chang wrote:
> > This series implements mitigations for lack of DMA access control on
> > systems without an IOMMU, which could result in the DMA accessing the
> > system memory at unexpected times and/or unexpected addresses, possibly
> > leading to data leakage or corruption.
> >
> > For example, we plan to use the PCI-e bus for Wi-Fi and that PCI-e bus is
> > not behind an IOMMU. As PCI-e, by design, gives the device full access to
> > system memory, a vulnerability in the Wi-Fi firmware could easily escalate
> > to a full system exploit (remote wifi exploits: [1a], [1b] that shows a
> > full chain of exploits; [2], [3]).
> >
> > To mitigate the security concerns, we introduce restricted DMA. Restricted
> > DMA utilizes the existing swiotlb to bounce streaming DMA in and out of a
> > specially allocated region and does memory allocation from the same region.
> > The feature on its own provides a basic level of protection against the DMA
> > overwriting buffer contents at unexpected times. However, to protect
> > against general data leakage and system memory corruption, the system needs
> > to provide a way to restrict the DMA to a predefined memory region (this is
> > usually done at firmware level, e.g. MPU in ATF on some ARM platforms [4]).
> >
> > [1a] https://googleprojectzero.blogspot.com/2017/04/over-air-exploiting-broadcoms-wi-fi_4.html
> > [1b] https://googleprojectzero.blogspot.com/2017/04/over-air-exploiting-broadcoms-wi-fi_11.html
> > [2] https://blade.tencent.com/en/advisories/qualpwn/
> > [3] https://www.bleepingcomputer.com/news/security/vulnerabilities-found-in-highly-popular-firmware-for-wifi-chips/
> > [4] https://github.com/ARM-software/arm-trusted-firmware/blob/master/plat/mediatek/mt8183/drivers/emi_mpu/emi_mpu.c#L132
> >
> > v15:
> > - Apply Will's diff (https://lore.kernel.org/patchwork/patch/1448957/#1647521)
> > to fix the crash reported by Qian.
> > - Add Stefano's Acked-by tag for patch 01/12 from v14
>
> That all should be now be on
>
> https://git.kernel.org/pub/scm/linux/kernel/git/konrad/swiotlb.git/
> devel/for-linus-5.14 (and linux-next)
Thanks Konrad!
Will
^ permalink raw reply
* Re: PowerPC guest getting "BUG: scheduling while atomic" on linux-next-20210623 during secondary CPUs bringup
From: Bharata B Rao @ 2021-06-25 12:32 UTC (permalink / raw)
To: Peter Zijlstra
Cc: Srikar Dronamraju, LKML, Valentin Schneider, linux-next,
linuxppc-dev, Ingo Molnar
In-Reply-To: <YNWtFKdSuoYTfSon@hirez.programming.kicks-ass.net>
On Fri, Jun 25, 2021 at 12:16:52PM +0200, Peter Zijlstra wrote:
> You mean: CONFIG_PREEMPTION=n, what about CONFIG_PREEMPT_COUNT?
>
> Because if both are =n, then I don't see how that warning could trigger.
> in_atomic_preempt_off() would then result in prempt_count() == 0, and
> per the print above, it *is* 0.
CONFIG_PREEMPTION isn't set.
Also other PREEMPT related options are as under:
# CONFIG_PREEMPT_NONE is not set
CONFIG_PREEMPT_VOLUNTARY=y
# CONFIG_PREEMPT is not set
CONFIG_PREEMPT_COUNT=y
CONFIG_PREEMPT_NOTIFIERS=y
CONFIG_PREEMPTIRQ_TRACEPOINTS=y
# CONFIG_PREEMPTIRQ_DELAY_TEST is not set
Regards,
Bharata.
^ permalink raw reply
* Re: [PATCH printk v3 4/6] printk: remove NMI tracking
From: Petr Mladek @ 2021-06-25 12:36 UTC (permalink / raw)
To: John Ogness
Cc: Peter Zijlstra, Alexei Starovoitov, Chris Wilson,
Wolfram Sang (Renesas), Paul Mackerras, Marc Zyngier,
Masahiro Yamada, Russell King, Ingo Molnar, linux-arm-kernel,
Sami Tolvanen, Valentin Schneider, Kees Cook, Anshuman Khandual,
Frederic Weisbecker, Steven Rostedt, Nathan Chancellor,
Nick Terrell, Thomas Gleixner, Vlastimil Babka, linux-kernel,
Pekka Enberg, Sergey Senozhatsky, Andrew Morton, linuxppc-dev,
Mike Rapoport
In-Reply-To: <20210624111148.5190-5-john.ogness@linutronix.de>
On Thu 2021-06-24 13:17:46, John Ogness wrote:
> All NMI contexts are handled the same as the safe context: store the
> message and defer printing. There is no need to have special NMI
> context tracking for this. Using in_nmi() is enough.
>
> Signed-off-by: John Ogness <john.ogness@linutronix.de>
> Reviewed-by: Petr Mladek <pmladek@suse.com>
> ---
> arch/arm/kernel/smp.c | 2 --
> arch/powerpc/kexec/crash.c | 3 ---
> include/linux/hardirq.h | 2 --
> include/linux/printk.h | 12 ------------
> init/Kconfig | 5 -----
> kernel/printk/internal.h | 6 ------
> kernel/printk/printk_safe.c | 37 +------------------------------------
> kernel/trace/trace.c | 2 --
> 8 files changed, 1 insertion(+), 68 deletions(-)
>
> diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
> index 74679240a9d8..0dd2d733ad62 100644
> --- a/arch/arm/kernel/smp.c
> +++ b/arch/arm/kernel/smp.c
> @@ -668,9 +668,7 @@ static void do_handle_IPI(int ipinr)
> break;
>
> case IPI_CPU_BACKTRACE:
> - printk_nmi_enter();
> nmi_cpu_backtrace(get_irq_regs());
> - printk_nmi_exit();
It looks to me that in_nmi() returns false here. As a result,
nmi_cpu_backtrace() might newly call consoles immediately.
If I recall correctly, arm does not have a proper NMI.
And this is just some special case of a "normal" IRQ.
And indeed, nmi_enter() is called only from handle_fiq_as_nmi()
and it is just a boiler plate.
If I am right, we should replace printk_nmi_enter() with
printk_safe_enter_irqsave(flags) or so.
Even better solution might be to call this within
nmi_enter()/nmi_exit(). But I am not sure if this is what
the arm people want.
Best Regards,
Petr
PS: Sigh, I have skipped this patch yesterday because it already had
my Reviewed-by. And I missed it before...
^ permalink raw reply
* [PATCH] ASoC: fsl_xcvr: remove an unneeded semicolon
From: 13145886936 @ 2021-06-25 12:37 UTC (permalink / raw)
To: timur, nicoleotsuka, Xiubo.Lee, perex, tiwai, alsa-devel
Cc: linuxppc-dev, linux-kernel, gushengxian
From: gushengxian <gushengxian@yulong.com>
Remove an unneeded semicolon.
Signed-off-by: gushengxian <gushengxian@yulong.com>
---
sound/soc/fsl/fsl_xcvr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sound/soc/fsl/fsl_xcvr.c b/sound/soc/fsl/fsl_xcvr.c
index e34d57ad66fb..75fa8f1b5576 100644
--- a/sound/soc/fsl/fsl_xcvr.c
+++ b/sound/soc/fsl/fsl_xcvr.c
@@ -736,7 +736,7 @@ static int fsl_xcvr_load_firmware(struct fsl_xcvr *xcvr)
/* clean current page, including data memory */
memset_io(xcvr->ram_addr, 0, size);
}
- };
+ }
err_firmware:
release_firmware(fw);
--
2.25.1
^ permalink raw reply related
* Re: [PATCH printk v3 3/6] printk: remove safe buffers
From: Petr Mladek @ 2021-06-25 12:41 UTC (permalink / raw)
To: John Ogness
Cc: Kees Cook, Paul E. McKenney, Alexey Kardashevskiy,
Nicholas Piggin, linux-kernel, Steven Rostedt, kexec,
Sergey Senozhatsky, Yue Hu, Paul Mackerras, Eric Biederman,
Thomas Gleixner, linuxppc-dev, Andrew Morton, Tiezhu Yang,
Cédric Le Goater
In-Reply-To: <8735t7mg0z.fsf@jogness.linutronix.de>
On Thu 2021-06-24 17:41:56, John Ogness wrote:
> I would prefer a v4 with these fixes:
>
> - wrap @console_owner_lock with printk_safe usage
>
> - remove unnecessary printk_safe usage from printk_safe.c
>
> - update commit message to say that safe context tracking is left in
> place for both the console and console_owner locks
Sounds good to me.
Best Regards,
Petr
^ permalink raw reply
* Re: [PATCH] perf vendor events power10: Adds 24x7 nest metric events for power10 platform
From: Paul A. Clarke @ 2021-06-25 13:21 UTC (permalink / raw)
To: Kajol Jain
Cc: ravi.bangoria, atrajeev, rnsastry, jolsa, linux-kernel, acme,
linux-perf-users, maddy, linuxppc-dev
In-Reply-To: <20210625115948.99579-1-kjain@linux.ibm.com>
On Fri, Jun 25, 2021 at 05:29:48PM +0530, Kajol Jain wrote:
> Patch adds 24x7 nest metric events for POWER10.
>
> Signed-off-by: Kajol Jain <kjain@linux.ibm.com>
> ---
> .../arch/powerpc/power10/nest_metrics.json | 491 ++++++++++++++++++
> 1 file changed, 491 insertions(+)
> create mode 100644 tools/perf/pmu-events/arch/powerpc/power10/nest_metrics.json
>
> diff --git a/tools/perf/pmu-events/arch/powerpc/power10/nest_metrics.json b/tools/perf/pmu-events/arch/powerpc/power10/nest_metrics.json
> new file mode 100644
> index 000000000000..b79046cd8b09
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/powerpc/power10/nest_metrics.json
> @@ -0,0 +1,491 @@
> +[
> + {
> + "MetricName": "VEC_GROUP_PUMP_RETRY_RATIO_P01",
> + "BriefDescription": "VEC_GROUP_PUMP_RETRY_RATIO_P01",
Is it possible to get better descriptions than just a restatement of the
name, or no description at all?
This comment obviously applies to almost all of the metrics herein.
> + "MetricExpr": "(hv_24x7@PM_PB_RTY_VG_PUMP01\\,chip\\=?@ / hv_24x7@PM_PB_VG_PUMP01\\,chip\\=?@) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "VEC_GROUP_PUMP_RETRY_RATIO_P23",
> + "BriefDescription": "VEC_GROUP_PUMP_RETRY_RATIO_P23",
> + "MetricExpr": "(hv_24x7@PM_PB_RTY_VG_PUMP23\\,chip\\=?@ / hv_24x7@PM_PB_VG_PUMP23\\,chip\\=?@) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "LOCAL_NODE_PUMP_RETRY_RATIO_P01",
> + "BriefDescription": "LOCAL_NODE_PUMP_RETRY_RATIO_P01",
> + "MetricExpr": "(hv_24x7@PM_PB_RTY_LNS_PUMP01\\,chip\\=?@ / hv_24x7@PM_PB_LNS_PUMP01\\,chip\\=?@) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "LOCAL_NODE_PUMP_RETRY_RATIO_P23",
> + "BriefDescription": "LOCAL_NODE_PUMP_RETRY_RATIO_P23",
> + "MetricExpr": "(hv_24x7@PM_PB_RTY_LNS_PUMP23\\,chip\\=?@ / hv_24x7@PM_PB_LNS_PUMP23\\,chip\\=?@) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "GROUP_PUMP_RETRY_RATIO_P01",
> + "BriefDescription": "GROUP_PUMP_RETRY_RATIO_P01",
> + "MetricExpr": "(hv_24x7@PM_PB_RTY_GROUP_PUMP01\\,chip\\=?@ / hv_24x7@PM_PB_GROUP_PUMP01\\,chip\\=?@) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "GROUP_PUMP_RETRY_RATIO_P23",
> + "BriefDescription": "GROUP_PUMP_RETRY_RATIO_P23",
> + "MetricExpr": "(hv_24x7@PM_PB_RTY_GROUP_PUMP23\\,chip\\=?@ / hv_24x7@PM_PB_GROUP_PUMP23\\,chip\\=?@) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_GROUP_PUMPS_P01",
> + "BriefDescription": "TOTAL_GROUP_PUMPS_P01(PER-CYC)",
> + "MetricExpr": "(hv_24x7@PM_PB_GROUP_PUMP01\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
> + "ScaleUnit": "4",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_GROUP_PUMPS_P23",
> + "BriefDescription": "TOTAL_GROUP_PUMPS_P23(PER-CYC)",
> + "MetricExpr": "(hv_24x7@PM_PB_GROUP_PUMP23\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
> + "ScaleUnit": "4",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_GROUP_PUMPS_RETRIES_P01",
> + "BriefDescription": "TOTAL_GROUP_PUMPS_RETRIES_P01(PER-CYC)",
> + "MetricExpr": "(hv_24x7@PM_PB_RTY_GROUP_PUMP01\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
> + "ScaleUnit": "4",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_GROUP_PUMPS_RETRIES_P23",
> + "BriefDescription": "TOTAL_GROUP_PUMPS_RETRIES_P23(PER-CYC)",
> + "MetricExpr": "(hv_24x7@PM_PB_RTY_GROUP_PUMP23\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
> + "ScaleUnit": "4",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "REMOTE_NODE_PUMPS_RETRIES_RATIO_P01",
> + "BriefDescription": "REMOTE_NODE_PUMPS_RETRIES_RATIO_P01",
> + "MetricExpr": "(hv_24x7@PM_PB_RTY_RNS_PUMP01\\,chip\\=?@ / hv_24x7@PM_PB_RNS_PUMP01\\,chip\\=?@) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "REMOTE_NODE_PUMPS_RETRIES_RATIO_P23",
> + "BriefDescription": "REMOTE_NODE_PUMPS_RETRIES_RATIO_P23",
> + "MetricExpr": "(hv_24x7@PM_PB_RTY_RNS_PUMP23\\,chip\\=?@ / hv_24x7@PM_PB_RNS_PUMP23\\,chip\\=?@) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_VECTOR_GROUP_PUMPS_P01",
> + "BriefDescription": "TOTAL_VECTOR_GROUP_PUMPS_P01(PER-CYC)",
> + "MetricExpr": "(hv_24x7@PM_PB_VG_PUMP01\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
> + "ScaleUnit": "4",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_VECTOR_GROUP_PUMPS_P23",
> + "BriefDescription": "TOTAL_VECTOR_GROUP_PUMPS_P23(PER-CYC)",
> + "MetricExpr": "(hv_24x7@PM_PB_VG_PUMP23\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
> + "ScaleUnit": "4",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_LOCAL_NODE_PUMPS_P01",
> + "BriefDescription": "TOTAL_LOCAL_NODE_PUMPS_P01(PER-CYC)",
> + "MetricExpr": "(hv_24x7@PM_PB_LNS_PUMP01\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
> + "ScaleUnit": "4",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_LOCAL_NODE_PUMPS_P23",
> + "BriefDescription": "TOTAL_LOCAL_NODE_PUMPS_P23(PER-CYC)",
> + "MetricExpr": "(hv_24x7@PM_PB_LNS_PUMP23\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
> + "ScaleUnit": "4",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_VECTOR_GROUP_PUMPS_RETRIES_P01",
> + "BriefDescription": "TOTAL_VECTOR_GROUP_PUMPS_RETRIES_P01(PER-CYC)",
> + "MetricExpr": "(hv_24x7@PM_PB_RTY_VG_PUMP01\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
> + "ScaleUnit": "4",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_VECTOR_GROUP_PUMPS_RETRIES_P23",
> + "BriefDescription": "TOTAL_VECTOR_GROUP_PUMPS_RETRIES_P23(PER-CYC)",
> + "MetricExpr": "(hv_24x7@PM_PB_RTY_VG_PUMP23\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
> + "ScaleUnit": "4",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_LOCAL_NODE_PUMPS_RETRIES_P01",
> + "BriefDescription": "TOTAL_LOCAL_NODE_PUMPS_RETRIES_P01(PER-CYC)",
> + "MetricExpr": "(hv_24x7@PM_PB_RTY_LNS_PUMP01\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
> + "ScaleUnit": "4",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_LOCAL_NODE_PUMPS_RETRIES_P23",
> + "BriefDescription": "TOTAL_LOCAL_NODE_PUMPS_RETRIES_P23(PER-CYC)",
> + "MetricExpr": "(hv_24x7@PM_PB_RTY_LNS_PUMP23\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
> + "ScaleUnit": "4",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_REMOTE_NODE_PUMPS_P01",
> + "BriefDescription": "TOTAL_REMOTE_NODE_PUMPS_P01",
> + "MetricExpr": "(hv_24x7@PM_PB_RNS_PUMP01\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
> + "ScaleUnit": "4",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_REMOTE_NODE_PUMPS_P23",
> + "BriefDescription": "TOTAL_REMOTE_NODE_PUMPS_P23",
> + "MetricExpr": "(hv_24x7@PM_PB_RNS_PUMP23\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
> + "ScaleUnit": "4",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_NEAR_NODE_PUMPS_P01",
> + "BriefDescription": "TOTAL_NEAR_NODE_PUMPS_P01",
> + "MetricExpr": "(hv_24x7@PM_PB_NNS_PUMP01\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
> + "ScaleUnit": "4",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_NEAR_NODE_PUMPS_P23",
> + "BriefDescription": "TOTAL_NEAR_NODE_PUMPS_P23",
> + "MetricExpr": "(hv_24x7@PM_PB_NNS_PUMP23\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
> + "ScaleUnit": "4",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_INT_PB_BW",
> + "BriefDescription": "TOTAL_INT_PB_BW",
> + "MetricExpr": "(hv_24x7@PM_PB_INT_DATA_XFER\\,chip\\=?@)",
> + "ScaleUnit": "2.09MB",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "XLINK0_OUT_TOTAL_UTILIZATION",
> + "BriefDescription": "XLINK0_OUT_TOTAL_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_XLINK0_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_XLINK0_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_XLINK0_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK0_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "XLINK1_OUT_TOTAL_UTILIZATION",
> + "BriefDescription": "XLINK1_OUT_TOTAL_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_XLINK1_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_XLINK1_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_XLINK1_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK1_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "XLINK2_OUT_TOTAL_UTILIZATION",
> + "BriefDescription": "XLINK2_OUT_TOTAL_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_XLINK2_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_XLINK2_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_XLINK2_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK2_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "XLINK3_OUT_TOTAL_UTILIZATION",
> + "BriefDescription": "XLINK3_OUT_TOTAL_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_XLINK3_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_XLINK3_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_XLINK3_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK3_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "XLINK4_OUT_TOTAL_UTILIZATION",
> + "BriefDescription": "XLINK4_OUT_TOTAL_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_XLINK4_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_XLINK4_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_XLINK4_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK4_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "XLINK5_OUT_TOTAL_UTILIZATION",
> + "BriefDescription": "XLINK5_OUT_TOTAL_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_XLINK5_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_XLINK5_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_XLINK5_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK5_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "XLINK6_OUT_TOTAL_UTILIZATION",
> + "BriefDescription": "XLINK6_OUT_TOTAL_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_XLINK6_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_XLINK6_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_XLINK6_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK6_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "XLINK7_OUT_TOTAL_UTILIZATION",
> + "BriefDescription": "XLINK7_OUT_TOTAL_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_XLINK7_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_XLINK7_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_XLINK7_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK7_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "XLINK0_OUT_DATA_UTILIZATION",
> + "BriefDescription": "XLINK0_OUT_DATA_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_XLINK0_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_XLINK0_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_XLINK0_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK0_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1.063%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "XLINK1_OUT_DATA_UTILIZATION",
> + "BriefDescription": "XLINK1_OUT_DATA_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_XLINK1_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_XLINK1_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_XLINK1_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK1_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1.063%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "XLINK2_OUT_DATA_UTILIZATION",
> + "BriefDescription": "XLINK2_OUT_DATA_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_XLINK2_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_XLINK2_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_XLINK2_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK2_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1.063%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "XLINK3_OUT_DATA_UTILIZATION",
> + "BriefDescription": "XLINK3_OUT_DATA_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_XLINK3_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_XLINK3_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_XLINK3_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK3_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1.063%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "XLINK4_OUT_DATA_UTILIZATION",
> + "BriefDescription": "XLINK4_OUT_DATA_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_XLINK4_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_XLINK4_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_XLINK4_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK4_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1.063%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "XLINK5_OUT_DATA_UTILIZATION",
> + "BriefDescription": "XLINK5_OUT_DATA_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_XLINK5_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_XLINK5_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_XLINK5_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK5_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1.063%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "XLINK6_OUT_DATA_UTILIZATION",
> + "BriefDescription": "XLINK6_OUT_DATA_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_XLINK6_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_XLINK6_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_XLINK6_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK6_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1.063%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "XLINK7_OUT_DATA_UTILIZATION",
> + "BriefDescription": "XLINK7_OUT_DATA_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_XLINK7_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_XLINK7_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_XLINK7_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK7_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1.063%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "ALINK0_OUT_TOTAL_UTILIZATION",
> + "BriefDescription": "ALINK0_OUT_TOTAL_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_ALINK0_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_ALINK0_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_ALINK0_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK0_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "ALINK1_OUT_TOTAL_UTILIZATION",
> + "BriefDescription": "ALINK1_OUT_TOTAL_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_ALINK1_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_ALINK1_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_ALINK1_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK1_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "ALINK2_OUT_TOTAL_UTILIZATION",
> + "BriefDescription": "ALINK2_OUT_TOTAL_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_ALINK2_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_ALINK2_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_ALINK2_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK2_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "ALINK3_OUT_TOTAL_UTILIZATION",
> + "BriefDescription": "ALINK3_OUT_TOTAL_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_ALINK3_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_ALINK3_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_ALINK3_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK3_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "ALINK4_OUT_TOTAL_UTILIZATION",
> + "BriefDescription": "ALINK4_OUT_TOTAL_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_ALINK4_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_ALINK4_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_ALINK4_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK4_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "ALINK5_OUT_TOTAL_UTILIZATION",
> + "BriefDescription": "ALINK5_OUT_TOTAL_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_ALINK5_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_ALINK5_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_ALINK5_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK5_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "ALINK6_OUT_TOTAL_UTILIZATION",
> + "BriefDescription": "ALINK6_OUT_TOTAL_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_ALINK6_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_ALINK6_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_ALINK6_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK6_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "ALINK7_OUT_TOTAL_UTILIZATION",
> + "BriefDescription": "ALINK7_OUT_TOTAL_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_ALINK7_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_ALINK7_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_ALINK7_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK7_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "ALINK0_OUT_DATA_UTILIZATION",
> + "BriefDescription": "ALINK0_OUT_DATA_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_ALINK0_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_ALINK0_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_ALINK0_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK0_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1.063%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "ALINK1_OUT_DATA_UTILIZATION",
> + "BriefDescription": "ALINK1_OUT_DATA_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_ALINK1_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_ALINK1_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_ALINK1_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK1_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1.063%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "ALINK2_OUT_DATA_UTILIZATION",
> + "BriefDescription": "ALINK2_OUT_DATA_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_ALINK2_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_ALINK2_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_ALINK2_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK2_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1.063%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "ALINK3_OUT_DATA_UTILIZATION",
> + "BriefDescription": "ALINK3_OUT_DATA_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_ALINK3_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_ALINK3_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_ALINK3_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK3_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1.063%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "ALINK4_OUT_DATA_UTILIZATION",
> + "BriefDescription": "ALINK4_OUT_DATA_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_ALINK4_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_ALINK4_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_ALINK4_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK4_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1.063%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "ALINK5_OUT_DATA_UTILIZATION",
> + "BriefDescription": "ALINK5_OUT_DATA_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_ALINK5_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_ALINK5_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_ALINK5_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK5_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1.063%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "ALINK6_OUT_DATA_UTILIZATION",
> + "BriefDescription": "ALINK6_OUT_DATA_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_ALINK6_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_ALINK6_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_ALINK6_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK6_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1.063%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "ALINK7_OUT_DATA_UTILIZATION",
> + "BriefDescription": "ALINK7_OUT_DATA_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_ALINK7_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_ALINK7_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_ALINK7_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK7_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1.063%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_DATA_BANDWIDTH_TRANSFERRED_OVER_PB_PCI1",
> + "BriefDescription": "TOTAL_DATA_BANDWIDTH_TRANSFERRED_OVER_PB_PCI1",
> + "MetricExpr": "(hv_24x7@PM_PCI1_32B_INOUT\\,chip\\=?@)",
> + "ScaleUnit": "3.28e-2MB",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_DATA_BANDWIDTH_TRANSFERRED_OVER_PB_PCI0",
> + "BriefDescription": "TOTAL_DATA_BANDWIDTH_TRANSFERRED_OVER_PB_PCI0",
> + "MetricExpr": "(hv_24x7@PM_PCI0_32B_INOUT\\,chip\\=?@)",
> + "ScaleUnit": "3.28e-2MB",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_MCS_READ_BW_MC0_CHAN01",
> + "BriefDescription": "TOTAL_MCS_READ_BW_MC0_CHAN01",
> + "MetricExpr": "(hv_24x7@PM_MCS_128B_RD_DATA_BLOCKS_MC0_CHAN01\\,chip\\=?@)",
> + "ScaleUnit": "5.24e-1MB",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_MCS_READ_BW_MC1_CHAN01",
> + "BriefDescription": "TOTAL_MCS_READ_BW_MC1_CHAN01",
> + "MetricExpr": "(hv_24x7@PM_MCS_128B_RD_DATA_BLOCKS_MC1_CHAN01\\,chip\\=?@)",
> + "ScaleUnit": "5.24e-1MB",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_MCS_READ_BW_MC2_CHAN01",
> + "BriefDescription": "TOTAL_MCS_READ_BW_MC2_CHAN01",
> + "MetricExpr": "(hv_24x7@PM_MCS_128B_RD_DATA_BLOCKS_MC2_CHAN01\\,chip\\=?@)",
> + "ScaleUnit": "5.24e-1MB",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_MCS_READ_BW_MC3_CHAN01",
> + "BriefDescription": "TOTAL_MCS_READ_BW_MC3_CHAN01",
> + "MetricExpr": "(hv_24x7@PM_MCS_128B_RD_DATA_BLOCKS_MC3_CHAN01\\,chip\\=?@)",
> + "ScaleUnit": "5.24e-1MB",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_MCS_WRITE_BW_MC0_CHAN01",
> + "BriefDescription": "TOTAL_MCS_WRITE_BW_MC0_CHAN01",
> + "MetricExpr": "(hv_24x7@PM_MCS_64B_WR_DATA_BLOCKS_MC0_CHAN01\\,chip\\=?@)",
> + "ScaleUnit": "2.6e-1MB",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_MCS_WRITE_BW_MC1_CHAN01",
> + "BriefDescription": "TOTAL_MCS_WRITE_BW_MC1_CHAN01",
> + "MetricExpr": "(hv_24x7@PM_MCS_64B_WR_DATA_BLOCKS_MC1_CHAN01\\,chip\\=?@)",
> + "ScaleUnit": "2.6e-1MB",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_MCS_WRITE_BW_MC2_CHAN01",
> + "BriefDescription": "TOTAL_MCS_WRITE_BW_MC2_CHAN01",
> + "MetricExpr": "(hv_24x7@PM_MCS_64B_WR_DATA_BLOCKS_MC2_CHAN01\\,chip\\=?@)",
> + "ScaleUnit": "2.6e-1MB",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_MCS_WRITE_BW_MC3_CHAN01",
> + "BriefDescription": "TOTAL_MCS_WRITE_BW_MC3_CHAN01",
> + "MetricExpr": "(hv_24x7@PM_MCS_64B_WR_DATA_BLOCKS_MC3_CHAN01\\,chip\\=?@)",
> + "ScaleUnit": "2.6e-1MB",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricExpr": "(hv_24x7@PM_MCS_128B_RD_DATA_BLOCKS_MC0_CHAN01\\,chip\\=?@ + hv_24x7@PM_MCS_128B_RD_DATA_BLOCKS_MC1_CHAN01\\,chip\\=?@ + hv_24x7@PM_MCS_128B_RD_DATA_BLOCKS_MC2_CHAN01\\,chip\\=?@ + hv_24x7@PM_MCS_128B_RD_DATA_BLOCKS_MC3_CHAN01\\,chip\\=?@)",
> + "MetricName": "Memory_RD_BW_Chip",
The pattern up until this point was "MetricName", then "BriefDescription",
then "MetricExpr". I think it would be helpful to continue that here,
and for the next two as well. That should include _having_ a description,
obviously. :-)
> + "MetricGroup": "Memory_BW",
> + "ScaleUnit": "5.24e-1MB",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricExpr": "(hv_24x7@PM_MCS_64B_WR_DATA_BLOCKS_MC0_CHAN01\\,chip\\=?@ + hv_24x7@PM_MCS_64B_WR_DATA_BLOCKS_MC1_CHAN01\\,chip\\=?@ + hv_24x7@PM_MCS_64B_WR_DATA_BLOCKS_MC2_CHAN01\\,chip\\=?@ + hv_24x7@PM_MCS_64B_WR_DATA_BLOCKS_MC3_CHAN01\\,chip\\=?@ )",
> + "MetricName": "Memory_WR_BW_Chip",
> + "MetricGroup": "Memory_BW",
> + "ScaleUnit": "2.6e-1MB",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricExpr": "(hv_24x7@PM_PAU_CYC\\,chip\\=?@ )",
> + "MetricName": "PowerBUS_Frequency",
> + "ScaleUnit": "2.56e-7GHz",
> + "AggregationMode": "PerChip"
> + }
> +]
> --
PC
^ permalink raw reply
* Re: [PATCH printk v3 4/6] printk: remove NMI tracking
From: Russell King (Oracle) @ 2021-06-25 13:34 UTC (permalink / raw)
To: Petr Mladek
Cc: Peter Zijlstra, Alexei Starovoitov, Chris Wilson,
Wolfram Sang (Renesas), Paul Mackerras, Marc Zyngier,
Masahiro Yamada, Ingo Molnar, linux-arm-kernel, Sami Tolvanen,
Valentin Schneider, Kees Cook, John Ogness, Anshuman Khandual,
Frederic Weisbecker, Steven Rostedt, Nathan Chancellor,
Nick Terrell, Thomas Gleixner, Vlastimil Babka, linux-kernel,
Pekka Enberg, Sergey Senozhatsky, Andrew Morton, linuxppc-dev,
Mike Rapoport
In-Reply-To: <YNXNx68CXrI9QpHD@alley>
On Fri, Jun 25, 2021 at 02:36:23PM +0200, Petr Mladek wrote:
> On Thu 2021-06-24 13:17:46, John Ogness wrote:
> > All NMI contexts are handled the same as the safe context: store the
> > message and defer printing. There is no need to have special NMI
> > context tracking for this. Using in_nmi() is enough.
> >
> > Signed-off-by: John Ogness <john.ogness@linutronix.de>
> > Reviewed-by: Petr Mladek <pmladek@suse.com>
> > ---
> > arch/arm/kernel/smp.c | 2 --
> > arch/powerpc/kexec/crash.c | 3 ---
> > include/linux/hardirq.h | 2 --
> > include/linux/printk.h | 12 ------------
> > init/Kconfig | 5 -----
> > kernel/printk/internal.h | 6 ------
> > kernel/printk/printk_safe.c | 37 +------------------------------------
> > kernel/trace/trace.c | 2 --
> > 8 files changed, 1 insertion(+), 68 deletions(-)
> >
> > diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
> > index 74679240a9d8..0dd2d733ad62 100644
> > --- a/arch/arm/kernel/smp.c
> > +++ b/arch/arm/kernel/smp.c
> > @@ -668,9 +668,7 @@ static void do_handle_IPI(int ipinr)
> > break;
> >
> > case IPI_CPU_BACKTRACE:
> > - printk_nmi_enter();
> > nmi_cpu_backtrace(get_irq_regs());
> > - printk_nmi_exit();
>
> It looks to me that in_nmi() returns false here. As a result,
> nmi_cpu_backtrace() might newly call consoles immediately.
>
> If I recall correctly, arm does not have a proper NMI.
> And this is just some special case of a "normal" IRQ.
>
> And indeed, nmi_enter() is called only from handle_fiq_as_nmi()
> and it is just a boiler plate.
>
> If I am right, we should replace printk_nmi_enter() with
> printk_safe_enter_irqsave(flags) or so.
>
> Even better solution might be to call this within
> nmi_enter()/nmi_exit(). But I am not sure if this is what
> the arm people want.
As I seem to recall, the guy in ARM Ltd who was working on this seemed
to drift away and it never got finished - however, I've always carried
platform specific hacks in my tree to make this work from FIQ on the
platforms I cared about:
http://git.armlinux.org.uk/cgit/linux-arm.git/commit/?h=fiq
Not suitable for mainline like that. I'm not aware of anyone working on
it now.
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!
^ permalink raw reply
* Re: [PATCH v16 1/4] kasan: allow an architecture to disable inline instrumentation
From: Andrey Konovalov @ 2021-06-25 13:45 UTC (permalink / raw)
To: Daniel Axtens
Cc: Marco Elver, aneesh.kumar, LKML, kasan-dev,
Linux Memory Management List, Andrew Morton, linuxppc-dev
In-Reply-To: <20210624034050.511391-2-dja@axtens.net>
On Thu, Jun 24, 2021 at 6:41 AM Daniel Axtens <dja@axtens.net> wrote:
>
> For annoying architectural reasons, it's very difficult to support inline
> instrumentation on powerpc64.*
>
> Add a Kconfig flag to allow an arch to disable inline. (It's a bit
> annoying to be 'backwards', but I'm not aware of any way to have
> an arch force a symbol to be 'n', rather than 'y'.)
>
> We also disable stack instrumentation in this case as it does things that
> are functionally equivalent to inline instrumentation, namely adding
> code that touches the shadow directly without going through a C helper.
>
> * on ppc64 atm, the shadow lives in virtual memory and isn't accessible in
> real mode. However, before we turn on virtual memory, we parse the device
> tree to determine which platform and MMU we're running under. That calls
> generic DT code, which is instrumented. Inline instrumentation in DT would
> unconditionally attempt to touch the shadow region, which we won't have
> set up yet, and would crash. We can make outline mode wait for the arch to
> be ready, but we can't change what the compiler inserts for inline mode.
>
> Reviewed-by: Marco Elver <elver@google.com>
> Signed-off-by: Daniel Axtens <dja@axtens.net>
> ---
> lib/Kconfig.kasan | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/lib/Kconfig.kasan b/lib/Kconfig.kasan
> index cffc2ebbf185..c3b228828a80 100644
> --- a/lib/Kconfig.kasan
> +++ b/lib/Kconfig.kasan
> @@ -12,6 +12,13 @@ config HAVE_ARCH_KASAN_HW_TAGS
> config HAVE_ARCH_KASAN_VMALLOC
> bool
>
> +config ARCH_DISABLE_KASAN_INLINE
> + bool
> + help
> + An architecture might not support inline instrumentation.
> + When this option is selected, inline and stack instrumentation are
> + disabled.
> +
> config CC_HAS_KASAN_GENERIC
> def_bool $(cc-option, -fsanitize=kernel-address)
>
> @@ -130,6 +137,7 @@ config KASAN_OUTLINE
>
> config KASAN_INLINE
> bool "Inline instrumentation"
> + depends on !ARCH_DISABLE_KASAN_INLINE
> help
> Compiler directly inserts code checking shadow memory before
> memory accesses. This is faster than outline (in some workloads
> @@ -141,6 +149,7 @@ endchoice
> config KASAN_STACK
> bool "Enable stack instrumentation (unsafe)" if CC_IS_CLANG && !COMPILE_TEST
> depends on KASAN_GENERIC || KASAN_SW_TAGS
> + depends on !ARCH_DISABLE_KASAN_INLINE
> default y if CC_IS_GCC
> help
> The LLVM stack address sanitizer has a know problem that
> @@ -154,6 +163,9 @@ config KASAN_STACK
> but clang users can still enable it for builds without
> CONFIG_COMPILE_TEST. On gcc it is assumed to always be safe
> to use and enabled by default.
> + If the architecture disables inline instrumentation, stack
> + instrumentation is also disabled as it adds inline-style
> + instrumentation that is run unconditionally.
>
> config KASAN_SW_TAGS_IDENTIFY
> bool "Enable memory corruption identification"
> --
> 2.30.2
>
Reviewed-by: Andrey Konovalov <andreyknvl@gmail.com>
Thanks, Daniel!
^ permalink raw reply
* Re: [PATCH v16 2/4] kasan: allow architectures to provide an outline readiness check
From: Andrey Konovalov @ 2021-06-25 13:45 UTC (permalink / raw)
To: Daniel Axtens
Cc: Marco Elver, aneesh.kumar, LKML, kasan-dev,
Linux Memory Management List, Andrew Morton, linuxppc-dev
In-Reply-To: <20210624034050.511391-3-dja@axtens.net>
On Thu, Jun 24, 2021 at 6:41 AM Daniel Axtens <dja@axtens.net> wrote:
>
> Allow architectures to define a kasan_arch_is_ready() hook that bails
> out of any function that's about to touch the shadow unless the arch
> says that it is ready for the memory to be accessed. This is fairly
> uninvasive and should have a negligible performance penalty.
>
> This will only work in outline mode, so an arch must specify
> ARCH_DISABLE_KASAN_INLINE if it requires this.
>
> Cc: Balbir Singh <bsingharora@gmail.com>
> Cc: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
> Suggested-by: Christophe Leroy <christophe.leroy@csgroup.eu>
> Reviewed-by: Marco Elver <elver@google.com>
> Signed-off-by: Daniel Axtens <dja@axtens.net>
>
> --
>
> Both previous RFCs for ppc64 - by 2 different people - have
> needed this trick! See:
> - https://lore.kernel.org/patchwork/patch/592820/ # ppc64 hash series
> - https://patchwork.ozlabs.org/patch/795211/ # ppc radix series
>
> Build tested on arm64 with SW_TAGS and x86 with INLINE: the error fires
> if I add a kasan_arch_is_ready define.
> ---
> mm/kasan/common.c | 3 +++
> mm/kasan/generic.c | 3 +++
> mm/kasan/kasan.h | 6 ++++++
> mm/kasan/shadow.c | 6 ++++++
> 4 files changed, 18 insertions(+)
>
> diff --git a/mm/kasan/common.c b/mm/kasan/common.c
> index 10177cc26d06..2baf121fb8c5 100644
> --- a/mm/kasan/common.c
> +++ b/mm/kasan/common.c
> @@ -331,6 +331,9 @@ static inline bool ____kasan_slab_free(struct kmem_cache *cache, void *object,
> u8 tag;
> void *tagged_object;
>
> + if (!kasan_arch_is_ready())
> + return false;
> +
> tag = get_tag(object);
> tagged_object = object;
> object = kasan_reset_tag(object);
> diff --git a/mm/kasan/generic.c b/mm/kasan/generic.c
> index 53cbf28859b5..c3f5ba7a294a 100644
> --- a/mm/kasan/generic.c
> +++ b/mm/kasan/generic.c
> @@ -163,6 +163,9 @@ static __always_inline bool check_region_inline(unsigned long addr,
> size_t size, bool write,
> unsigned long ret_ip)
> {
> + if (!kasan_arch_is_ready())
> + return true;
> +
> if (unlikely(size == 0))
> return true;
>
> diff --git a/mm/kasan/kasan.h b/mm/kasan/kasan.h
> index 8f450bc28045..4dbc8def64f4 100644
> --- a/mm/kasan/kasan.h
> +++ b/mm/kasan/kasan.h
> @@ -449,6 +449,12 @@ static inline void kasan_poison_last_granule(const void *address, size_t size) {
>
> #endif /* CONFIG_KASAN_GENERIC */
>
> +#ifndef kasan_arch_is_ready
> +static inline bool kasan_arch_is_ready(void) { return true; }
> +#elif !defined(CONFIG_KASAN_GENERIC) || !defined(CONFIG_KASAN_OUTLINE)
> +#error kasan_arch_is_ready only works in KASAN generic outline mode!
> +#endif
> +
> /*
> * Exported functions for interfaces called from assembly or from generated
> * code. Declarations here to avoid warning about missing declarations.
> diff --git a/mm/kasan/shadow.c b/mm/kasan/shadow.c
> index 082ee5b6d9a1..8d95ee52d019 100644
> --- a/mm/kasan/shadow.c
> +++ b/mm/kasan/shadow.c
> @@ -73,6 +73,9 @@ void kasan_poison(const void *addr, size_t size, u8 value, bool init)
> {
> void *shadow_start, *shadow_end;
>
> + if (!kasan_arch_is_ready())
> + return;
> +
> /*
> * Perform shadow offset calculation based on untagged address, as
> * some of the callers (e.g. kasan_poison_object_data) pass tagged
> @@ -99,6 +102,9 @@ EXPORT_SYMBOL(kasan_poison);
> #ifdef CONFIG_KASAN_GENERIC
> void kasan_poison_last_granule(const void *addr, size_t size)
> {
> + if (!kasan_arch_is_ready())
> + return;
> +
> if (size & KASAN_GRANULE_MASK) {
> u8 *shadow = (u8 *)kasan_mem_to_shadow(addr + size);
> *shadow = size & KASAN_GRANULE_MASK;
> --
> 2.30.2
>
Reviewed-by: Andrey Konovalov <andreyknvl@gmail.com>
^ permalink raw reply
* [PATCH] powerpc/stacktrace: Fix spurious "stale" traces in raise_backtrace_ipi()
From: Michael Ellerman @ 2021-06-25 14:04 UTC (permalink / raw)
To: linuxppc-dev; +Cc: nathanl
In raise_backtrace_ipi() we iterate through the cpumask of CPUs, sending
each an IPI asking them to do a backtrace, but we don't wait for the
backtrace to happen.
We then iterate through the CPU mask again, and if any CPU hasn't done
the backtrace and cleared itself from the mask, we print a trace on its
behalf, noting that the trace may be "stale".
This works well enough when a CPU is not responding, because in that
case it doesn't receive the IPI and the sending CPU is left to print the
trace. But when all CPUs are responding we are left with a race between
the sending and receiving CPUs, if the sending CPU wins the race then it
will erroneously print a trace.
This leads to spurious "stale" traces from the sending CPU, which can
then be interleaved messily with the receiving CPU, note the CPU
numbers, eg:
[ 1658.929157][ C7] rcu: Stack dump where RCU GP kthread last ran:
[ 1658.929223][ C7] Sending NMI from CPU 7 to CPUs 1:
[ 1658.929303][ C1] NMI backtrace for cpu 1
[ 1658.929303][ C7] CPU 1 didn't respond to backtrace IPI, inspecting paca.
[ 1658.929362][ C1] CPU: 1 PID: 325 Comm: kworker/1:1H Tainted: G W E 5.13.0-rc2+ #46
[ 1658.929405][ C7] irq_soft_mask: 0x01 in_mce: 0 in_nmi: 0 current: 325 (kworker/1:1H)
[ 1658.929465][ C1] Workqueue: events_highpri test_work_fn [test_lockup]
[ 1658.929549][ C7] Back trace of paca->saved_r1 (0xc0000000057fb400) (possibly stale):
[ 1658.929592][ C1] NIP: c00000000002cf50 LR: c008000000820178 CTR: c00000000002cfa0
To fix it, change the logic so that the sending CPU waits 5s for the
receiving CPU to print its trace. If the receiving CPU prints its trace
successfully then the sending CPU just continues, avoiding any spurious
"stale" trace.
This has the added benefit of allowing all CPUs to print their traces in
order and avoids any interleaving of their output.
Fixes: 5cc05910f26e ("powerpc/64s: Wire up arch_trigger_cpumask_backtrace()")
Cc: stable@vger.kernel.org # v4.18+
Reported-by: Nathan Lynch <nathanl@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
---
arch/powerpc/kernel/stacktrace.c | 26 ++++++++++++++++++++------
1 file changed, 20 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/kernel/stacktrace.c b/arch/powerpc/kernel/stacktrace.c
index 1961e6d5e33b..2b0d04a1b7d2 100644
--- a/arch/powerpc/kernel/stacktrace.c
+++ b/arch/powerpc/kernel/stacktrace.c
@@ -172,17 +172,31 @@ static void handle_backtrace_ipi(struct pt_regs *regs)
static void raise_backtrace_ipi(cpumask_t *mask)
{
+ struct paca_struct *p;
unsigned int cpu;
+ u64 delay_us;
for_each_cpu(cpu, mask) {
- if (cpu == smp_processor_id())
+ if (cpu == smp_processor_id()) {
handle_backtrace_ipi(NULL);
- else
- smp_send_safe_nmi_ipi(cpu, handle_backtrace_ipi, 5 * USEC_PER_SEC);
- }
+ continue;
+ }
- for_each_cpu(cpu, mask) {
- struct paca_struct *p = paca_ptrs[cpu];
+ delay_us = 5 * USEC_PER_SEC;
+
+ if (smp_send_safe_nmi_ipi(cpu, handle_backtrace_ipi, delay_us)) {
+ // Now wait up to 5s for the other CPU to do its backtrace
+ while (cpumask_test_cpu(cpu, mask) && delay_us) {
+ udelay(1);
+ delay_us--;
+ }
+
+ // Other CPU cleared itself from the mask
+ if (delay_us)
+ continue;
+ }
+
+ p = paca_ptrs[cpu];
cpumask_clear_cpu(cpu, mask);
--
2.25.1
^ permalink raw reply related
* [PATCH] powerpc/interrupt: Also use exit_must_hard_disable() on PPC32
From: Christophe Leroy @ 2021-06-25 14:31 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman, npiggin
Cc: linuxppc-dev, linux-kernel
Reduce #ifdefs a bit by making exit_must_hard_disable() return
true on PPC32.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
---
arch/powerpc/kernel/interrupt.c | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/kernel/interrupt.c b/arch/powerpc/kernel/interrupt.c
index cee12f2fd459..1b4a99ecb7e5 100644
--- a/arch/powerpc/kernel/interrupt.c
+++ b/arch/powerpc/kernel/interrupt.c
@@ -33,10 +33,10 @@ static inline bool exit_must_hard_disable(void)
{
return static_branch_unlikely(&interrupt_exit_not_reentrant);
}
-#elif defined(CONFIG_PPC64)
+#else
static inline bool exit_must_hard_disable(void)
{
- return false;
+ return IS_ENABLED(CONFIG_PPC32);
}
#endif
@@ -56,12 +56,10 @@ static notrace __always_inline bool prep_irq_for_enabled_exit(bool restartable)
/* This must be done with RI=1 because tracing may touch vmaps */
trace_hardirqs_on();
-#ifdef CONFIG_PPC32
- __hard_EE_RI_disable();
-#else
if (exit_must_hard_disable() || !restartable)
__hard_EE_RI_disable();
+#ifdef CONFIG_PPC64
/* This pattern matches prep_irq_for_idle */
if (unlikely(lazy_irq_pending_nocheck())) {
if (exit_must_hard_disable() || !restartable) {
--
2.25.0
^ permalink raw reply related
* Re: [PATCH 1/2] powerpc/bug: Remove specific powerpc BUG_ON() and WARN_ON() on PPC32
From: Christophe Leroy @ 2021-06-25 14:41 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman
Cc: linuxppc-dev, linux-kernel
In-Reply-To: <b286e07fb771a664b631cd07a40b09c06f26e64b.1618244758.git.christophe.leroy@csgroup.eu>
Hi Michael,
What happened to this series ? It has been flagged 'under review' in Patchwork since mid April but I
never saw it in next-test.
Thanks
Christophe
Le 12/04/2021 à 18:26, Christophe Leroy a écrit :
> powerpc BUG_ON() and WARN_ON() are based on using twnei instruction.
>
> For catching simple conditions like a variable having value 0, this
> is efficient because it does the test and the trap at the same time.
> But most conditions used with BUG_ON or WARN_ON are more complex and
> forces GCC to format the condition into a 0 or 1 value in a register.
> This will usually require 2 to 3 instructions.
>
> The most efficient solution would be to use __builtin_trap() because
> GCC is able to optimise the use of the different trap instructions
> based on the requested condition, but this is complex if not
> impossible for the following reasons:
> - __builtin_trap() is a non-recoverable instruction, so it can't be
> used for WARN_ON
> - Knowing which line of code generated the trap would require the
> analysis of DWARF information. This is not a feature we have today.
>
> As mentioned in commit 8d4fbcfbe0a4 ("Fix WARN_ON() on bitfield ops")
> the way WARN_ON() is implemented is suboptimal. That commit also
> mentions an issue with 'long long' condition. It fixed it for
> WARN_ON() but the same problem still exists today with BUG_ON() on
> PPC32. It will be fixed by using the generic implementation.
>
> By using the generic implementation, gcc will naturally generate a
> branch to the unconditional trap generated by BUG().
>
> As modern powerpc implement zero-cycle branch,
> that's even more efficient.
>
> And for the functions using WARN_ON() and its return, the test
> on return from WARN_ON() is now also used for the WARN_ON() itself.
>
> On PPC64 we don't want it because we want to be able to use CFAR
> register to track how we entered the code that trapped. The CFAR
> register would be clobbered by the branch.
>
> A simple test function:
>
> unsigned long test9w(unsigned long a, unsigned long b)
> {
> if (WARN_ON(!b))
> return 0;
> return a / b;
> }
>
> Before the patch:
>
> 0000046c <test9w>:
> 46c: 7c 89 00 34 cntlzw r9,r4
> 470: 55 29 d9 7e rlwinm r9,r9,27,5,31
> 474: 0f 09 00 00 twnei r9,0
> 478: 2c 04 00 00 cmpwi r4,0
> 47c: 41 82 00 0c beq 488 <test9w+0x1c>
> 480: 7c 63 23 96 divwu r3,r3,r4
> 484: 4e 80 00 20 blr
>
> 488: 38 60 00 00 li r3,0
> 48c: 4e 80 00 20 blr
>
> After the patch:
>
> 00000468 <test9w>:
> 468: 2c 04 00 00 cmpwi r4,0
> 46c: 41 82 00 0c beq 478 <test9w+0x10>
> 470: 7c 63 23 96 divwu r3,r3,r4
> 474: 4e 80 00 20 blr
>
> 478: 0f e0 00 00 twui r0,0
> 47c: 38 60 00 00 li r3,0
> 480: 4e 80 00 20 blr
>
> So we see before the patch we need 3 instructions on the likely path
> to handle the WARN_ON(). With the patch the trap goes on the unlikely
> path.
>
> See below the difference at the entry of system_call_exception where
> we have several BUG_ON(), allthough less impressing.
>
> With the patch:
>
> 00000000 <system_call_exception>:
> 0: 81 6a 00 84 lwz r11,132(r10)
> 4: 90 6a 00 88 stw r3,136(r10)
> 8: 71 60 00 02 andi. r0,r11,2
> c: 41 82 00 70 beq 7c <system_call_exception+0x7c>
> 10: 71 60 40 00 andi. r0,r11,16384
> 14: 41 82 00 6c beq 80 <system_call_exception+0x80>
> 18: 71 6b 80 00 andi. r11,r11,32768
> 1c: 41 82 00 68 beq 84 <system_call_exception+0x84>
> 20: 94 21 ff e0 stwu r1,-32(r1)
> 24: 93 e1 00 1c stw r31,28(r1)
> 28: 7d 8c 42 e6 mftb r12
> ...
> 7c: 0f e0 00 00 twui r0,0
> 80: 0f e0 00 00 twui r0,0
> 84: 0f e0 00 00 twui r0,0
>
> Without the patch:
>
> 00000000 <system_call_exception>:
> 0: 94 21 ff e0 stwu r1,-32(r1)
> 4: 93 e1 00 1c stw r31,28(r1)
> 8: 90 6a 00 88 stw r3,136(r10)
> c: 81 6a 00 84 lwz r11,132(r10)
> 10: 69 60 00 02 xori r0,r11,2
> 14: 54 00 ff fe rlwinm r0,r0,31,31,31
> 18: 0f 00 00 00 twnei r0,0
> 1c: 69 60 40 00 xori r0,r11,16384
> 20: 54 00 97 fe rlwinm r0,r0,18,31,31
> 24: 0f 00 00 00 twnei r0,0
> 28: 69 6b 80 00 xori r11,r11,32768
> 2c: 55 6b 8f fe rlwinm r11,r11,17,31,31
> 30: 0f 0b 00 00 twnei r11,0
> 34: 7d 8c 42 e6 mftb r12
>
> Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
> ---
> arch/powerpc/include/asm/bug.h | 9 ++++++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/bug.h b/arch/powerpc/include/asm/bug.h
> index d1635ffbb179..101dea4eec8d 100644
> --- a/arch/powerpc/include/asm/bug.h
> +++ b/arch/powerpc/include/asm/bug.h
> @@ -68,7 +68,11 @@
> BUG_ENTRY("twi 31, 0, 0", 0); \
> unreachable(); \
> } while (0)
> +#define HAVE_ARCH_BUG
> +
> +#define __WARN_FLAGS(flags) BUG_ENTRY("twi 31, 0, 0", BUGFLAG_WARNING | (flags))
>
> +#ifdef CONFIG_PPC64
> #define BUG_ON(x) do { \
> if (__builtin_constant_p(x)) { \
> if (x) \
> @@ -78,8 +82,6 @@
> } \
> } while (0)
>
> -#define __WARN_FLAGS(flags) BUG_ENTRY("twi 31, 0, 0", BUGFLAG_WARNING | (flags))
> -
> #define WARN_ON(x) ({ \
> int __ret_warn_on = !!(x); \
> if (__builtin_constant_p(__ret_warn_on)) { \
> @@ -93,9 +95,10 @@
> unlikely(__ret_warn_on); \
> })
>
> -#define HAVE_ARCH_BUG
> #define HAVE_ARCH_BUG_ON
> #define HAVE_ARCH_WARN_ON
> +#endif
> +
> #endif /* __ASSEMBLY __ */
> #else
> #ifdef __ASSEMBLY__
>
^ permalink raw reply
* [PATCH] powerpc/interrupt: Use names in check_return_regs_valid()
From: Christophe Leroy @ 2021-06-25 14:49 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman, npiggin
Cc: linuxppc-dev, linux-kernel
trap->regs == 0x3000 is trap_is_scv()
trap 0x500 is INTERRUPT_EXTERNAL
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
---
arch/powerpc/kernel/interrupt.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/kernel/interrupt.c b/arch/powerpc/kernel/interrupt.c
index 1b4a99ecb7e5..0052702ee5ac 100644
--- a/arch/powerpc/kernel/interrupt.c
+++ b/arch/powerpc/kernel/interrupt.c
@@ -222,12 +222,12 @@ static void check_return_regs_valid(struct pt_regs *regs)
u8 *validp;
char *h;
- if (regs->trap == 0x3000)
+ if (trap_is_scv(regs))
return;
trap = regs->trap;
// EE in HV mode sets HSRRs like 0xea0
- if (cpu_has_feature(CPU_FTR_HVMODE) && trap == 0x500)
+ if (cpu_has_feature(CPU_FTR_HVMODE) && trap == INTERRUPT_EXTERNAL)
trap = 0xea0;
switch (trap) {
--
2.25.0
^ permalink raw reply related
* Re: [PATCH] perf vendor events power10: Adds 24x7 nest metric events for power10 platform
From: Nageswara Sastry @ 2021-06-25 15:42 UTC (permalink / raw)
To: Kajol Jain, acme
Cc: ravi.bangoria, atrajeev, linuxppc-dev, linux-kernel,
linux-perf-users, maddy, pc, jolsa
In-Reply-To: <20210625115948.99579-1-kjain@linux.ibm.com>
Test scenarios:
1. With 'perf list metric' and 'perf list metricgroup' - can see metrics
2. Run all the metrics with perf stat with -M option and --metric-only
-M option
The above test scenarios automated with avocado framework, pull request
title: perf_metric.py: Add perf metric test case
Output from automated test script run:
(1/2) perf_metric.py:perf_metric.test_all_metric_events_with_M: PASS
(89.83 s)
(2/2) perf_metric.py:perf_metric.test_all_metric_events_with_metric:
PASS (89.34 s)
Tested-by: Nageswara R Sastry <rnsastry@linux.ibm.com>
On 25/06/21 5:29 pm, Kajol Jain wrote:
> Patch adds 24x7 nest metric events for POWER10.
>
> Signed-off-by: Kajol Jain <kjain@linux.ibm.com>
> ---
> .../arch/powerpc/power10/nest_metrics.json | 491 ++++++++++++++++++
> 1 file changed, 491 insertions(+)
> create mode 100644 tools/perf/pmu-events/arch/powerpc/power10/nest_metrics.json
>
> diff --git a/tools/perf/pmu-events/arch/powerpc/power10/nest_metrics.json b/tools/perf/pmu-events/arch/powerpc/power10/nest_metrics.json
> new file mode 100644
> index 000000000000..b79046cd8b09
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/powerpc/power10/nest_metrics.json
> @@ -0,0 +1,491 @@
> +[
> + {
> + "MetricName": "VEC_GROUP_PUMP_RETRY_RATIO_P01",
> + "BriefDescription": "VEC_GROUP_PUMP_RETRY_RATIO_P01",
> + "MetricExpr": "(hv_24x7@PM_PB_RTY_VG_PUMP01\\,chip\\=?@ / hv_24x7@PM_PB_VG_PUMP01\\,chip\\=?@) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "VEC_GROUP_PUMP_RETRY_RATIO_P23",
> + "BriefDescription": "VEC_GROUP_PUMP_RETRY_RATIO_P23",
> + "MetricExpr": "(hv_24x7@PM_PB_RTY_VG_PUMP23\\,chip\\=?@ / hv_24x7@PM_PB_VG_PUMP23\\,chip\\=?@) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "LOCAL_NODE_PUMP_RETRY_RATIO_P01",
> + "BriefDescription": "LOCAL_NODE_PUMP_RETRY_RATIO_P01",
> + "MetricExpr": "(hv_24x7@PM_PB_RTY_LNS_PUMP01\\,chip\\=?@ / hv_24x7@PM_PB_LNS_PUMP01\\,chip\\=?@) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "LOCAL_NODE_PUMP_RETRY_RATIO_P23",
> + "BriefDescription": "LOCAL_NODE_PUMP_RETRY_RATIO_P23",
> + "MetricExpr": "(hv_24x7@PM_PB_RTY_LNS_PUMP23\\,chip\\=?@ / hv_24x7@PM_PB_LNS_PUMP23\\,chip\\=?@) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "GROUP_PUMP_RETRY_RATIO_P01",
> + "BriefDescription": "GROUP_PUMP_RETRY_RATIO_P01",
> + "MetricExpr": "(hv_24x7@PM_PB_RTY_GROUP_PUMP01\\,chip\\=?@ / hv_24x7@PM_PB_GROUP_PUMP01\\,chip\\=?@) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "GROUP_PUMP_RETRY_RATIO_P23",
> + "BriefDescription": "GROUP_PUMP_RETRY_RATIO_P23",
> + "MetricExpr": "(hv_24x7@PM_PB_RTY_GROUP_PUMP23\\,chip\\=?@ / hv_24x7@PM_PB_GROUP_PUMP23\\,chip\\=?@) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_GROUP_PUMPS_P01",
> + "BriefDescription": "TOTAL_GROUP_PUMPS_P01(PER-CYC)",
> + "MetricExpr": "(hv_24x7@PM_PB_GROUP_PUMP01\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
> + "ScaleUnit": "4",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_GROUP_PUMPS_P23",
> + "BriefDescription": "TOTAL_GROUP_PUMPS_P23(PER-CYC)",
> + "MetricExpr": "(hv_24x7@PM_PB_GROUP_PUMP23\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
> + "ScaleUnit": "4",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_GROUP_PUMPS_RETRIES_P01",
> + "BriefDescription": "TOTAL_GROUP_PUMPS_RETRIES_P01(PER-CYC)",
> + "MetricExpr": "(hv_24x7@PM_PB_RTY_GROUP_PUMP01\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
> + "ScaleUnit": "4",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_GROUP_PUMPS_RETRIES_P23",
> + "BriefDescription": "TOTAL_GROUP_PUMPS_RETRIES_P23(PER-CYC)",
> + "MetricExpr": "(hv_24x7@PM_PB_RTY_GROUP_PUMP23\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
> + "ScaleUnit": "4",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "REMOTE_NODE_PUMPS_RETRIES_RATIO_P01",
> + "BriefDescription": "REMOTE_NODE_PUMPS_RETRIES_RATIO_P01",
> + "MetricExpr": "(hv_24x7@PM_PB_RTY_RNS_PUMP01\\,chip\\=?@ / hv_24x7@PM_PB_RNS_PUMP01\\,chip\\=?@) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "REMOTE_NODE_PUMPS_RETRIES_RATIO_P23",
> + "BriefDescription": "REMOTE_NODE_PUMPS_RETRIES_RATIO_P23",
> + "MetricExpr": "(hv_24x7@PM_PB_RTY_RNS_PUMP23\\,chip\\=?@ / hv_24x7@PM_PB_RNS_PUMP23\\,chip\\=?@) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_VECTOR_GROUP_PUMPS_P01",
> + "BriefDescription": "TOTAL_VECTOR_GROUP_PUMPS_P01(PER-CYC)",
> + "MetricExpr": "(hv_24x7@PM_PB_VG_PUMP01\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
> + "ScaleUnit": "4",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_VECTOR_GROUP_PUMPS_P23",
> + "BriefDescription": "TOTAL_VECTOR_GROUP_PUMPS_P23(PER-CYC)",
> + "MetricExpr": "(hv_24x7@PM_PB_VG_PUMP23\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
> + "ScaleUnit": "4",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_LOCAL_NODE_PUMPS_P01",
> + "BriefDescription": "TOTAL_LOCAL_NODE_PUMPS_P01(PER-CYC)",
> + "MetricExpr": "(hv_24x7@PM_PB_LNS_PUMP01\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
> + "ScaleUnit": "4",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_LOCAL_NODE_PUMPS_P23",
> + "BriefDescription": "TOTAL_LOCAL_NODE_PUMPS_P23(PER-CYC)",
> + "MetricExpr": "(hv_24x7@PM_PB_LNS_PUMP23\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
> + "ScaleUnit": "4",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_VECTOR_GROUP_PUMPS_RETRIES_P01",
> + "BriefDescription": "TOTAL_VECTOR_GROUP_PUMPS_RETRIES_P01(PER-CYC)",
> + "MetricExpr": "(hv_24x7@PM_PB_RTY_VG_PUMP01\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
> + "ScaleUnit": "4",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_VECTOR_GROUP_PUMPS_RETRIES_P23",
> + "BriefDescription": "TOTAL_VECTOR_GROUP_PUMPS_RETRIES_P23(PER-CYC)",
> + "MetricExpr": "(hv_24x7@PM_PB_RTY_VG_PUMP23\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
> + "ScaleUnit": "4",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_LOCAL_NODE_PUMPS_RETRIES_P01",
> + "BriefDescription": "TOTAL_LOCAL_NODE_PUMPS_RETRIES_P01(PER-CYC)",
> + "MetricExpr": "(hv_24x7@PM_PB_RTY_LNS_PUMP01\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
> + "ScaleUnit": "4",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_LOCAL_NODE_PUMPS_RETRIES_P23",
> + "BriefDescription": "TOTAL_LOCAL_NODE_PUMPS_RETRIES_P23(PER-CYC)",
> + "MetricExpr": "(hv_24x7@PM_PB_RTY_LNS_PUMP23\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
> + "ScaleUnit": "4",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_REMOTE_NODE_PUMPS_P01",
> + "BriefDescription": "TOTAL_REMOTE_NODE_PUMPS_P01",
> + "MetricExpr": "(hv_24x7@PM_PB_RNS_PUMP01\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
> + "ScaleUnit": "4",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_REMOTE_NODE_PUMPS_P23",
> + "BriefDescription": "TOTAL_REMOTE_NODE_PUMPS_P23",
> + "MetricExpr": "(hv_24x7@PM_PB_RNS_PUMP23\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
> + "ScaleUnit": "4",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_NEAR_NODE_PUMPS_P01",
> + "BriefDescription": "TOTAL_NEAR_NODE_PUMPS_P01",
> + "MetricExpr": "(hv_24x7@PM_PB_NNS_PUMP01\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
> + "ScaleUnit": "4",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_NEAR_NODE_PUMPS_P23",
> + "BriefDescription": "TOTAL_NEAR_NODE_PUMPS_P23",
> + "MetricExpr": "(hv_24x7@PM_PB_NNS_PUMP23\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
> + "ScaleUnit": "4",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_INT_PB_BW",
> + "BriefDescription": "TOTAL_INT_PB_BW",
> + "MetricExpr": "(hv_24x7@PM_PB_INT_DATA_XFER\\,chip\\=?@)",
> + "ScaleUnit": "2.09MB",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "XLINK0_OUT_TOTAL_UTILIZATION",
> + "BriefDescription": "XLINK0_OUT_TOTAL_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_XLINK0_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_XLINK0_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_XLINK0_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK0_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "XLINK1_OUT_TOTAL_UTILIZATION",
> + "BriefDescription": "XLINK1_OUT_TOTAL_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_XLINK1_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_XLINK1_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_XLINK1_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK1_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "XLINK2_OUT_TOTAL_UTILIZATION",
> + "BriefDescription": "XLINK2_OUT_TOTAL_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_XLINK2_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_XLINK2_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_XLINK2_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK2_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "XLINK3_OUT_TOTAL_UTILIZATION",
> + "BriefDescription": "XLINK3_OUT_TOTAL_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_XLINK3_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_XLINK3_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_XLINK3_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK3_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "XLINK4_OUT_TOTAL_UTILIZATION",
> + "BriefDescription": "XLINK4_OUT_TOTAL_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_XLINK4_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_XLINK4_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_XLINK4_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK4_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "XLINK5_OUT_TOTAL_UTILIZATION",
> + "BriefDescription": "XLINK5_OUT_TOTAL_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_XLINK5_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_XLINK5_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_XLINK5_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK5_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "XLINK6_OUT_TOTAL_UTILIZATION",
> + "BriefDescription": "XLINK6_OUT_TOTAL_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_XLINK6_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_XLINK6_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_XLINK6_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK6_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "XLINK7_OUT_TOTAL_UTILIZATION",
> + "BriefDescription": "XLINK7_OUT_TOTAL_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_XLINK7_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_XLINK7_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_XLINK7_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK7_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "XLINK0_OUT_DATA_UTILIZATION",
> + "BriefDescription": "XLINK0_OUT_DATA_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_XLINK0_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_XLINK0_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_XLINK0_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK0_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1.063%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "XLINK1_OUT_DATA_UTILIZATION",
> + "BriefDescription": "XLINK1_OUT_DATA_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_XLINK1_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_XLINK1_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_XLINK1_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK1_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1.063%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "XLINK2_OUT_DATA_UTILIZATION",
> + "BriefDescription": "XLINK2_OUT_DATA_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_XLINK2_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_XLINK2_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_XLINK2_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK2_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1.063%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "XLINK3_OUT_DATA_UTILIZATION",
> + "BriefDescription": "XLINK3_OUT_DATA_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_XLINK3_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_XLINK3_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_XLINK3_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK3_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1.063%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "XLINK4_OUT_DATA_UTILIZATION",
> + "BriefDescription": "XLINK4_OUT_DATA_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_XLINK4_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_XLINK4_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_XLINK4_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK4_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1.063%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "XLINK5_OUT_DATA_UTILIZATION",
> + "BriefDescription": "XLINK5_OUT_DATA_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_XLINK5_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_XLINK5_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_XLINK5_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK5_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1.063%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "XLINK6_OUT_DATA_UTILIZATION",
> + "BriefDescription": "XLINK6_OUT_DATA_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_XLINK6_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_XLINK6_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_XLINK6_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK6_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1.063%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "XLINK7_OUT_DATA_UTILIZATION",
> + "BriefDescription": "XLINK7_OUT_DATA_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_XLINK7_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_XLINK7_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_XLINK7_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK7_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1.063%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "ALINK0_OUT_TOTAL_UTILIZATION",
> + "BriefDescription": "ALINK0_OUT_TOTAL_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_ALINK0_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_ALINK0_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_ALINK0_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK0_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "ALINK1_OUT_TOTAL_UTILIZATION",
> + "BriefDescription": "ALINK1_OUT_TOTAL_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_ALINK1_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_ALINK1_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_ALINK1_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK1_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "ALINK2_OUT_TOTAL_UTILIZATION",
> + "BriefDescription": "ALINK2_OUT_TOTAL_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_ALINK2_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_ALINK2_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_ALINK2_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK2_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "ALINK3_OUT_TOTAL_UTILIZATION",
> + "BriefDescription": "ALINK3_OUT_TOTAL_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_ALINK3_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_ALINK3_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_ALINK3_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK3_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "ALINK4_OUT_TOTAL_UTILIZATION",
> + "BriefDescription": "ALINK4_OUT_TOTAL_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_ALINK4_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_ALINK4_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_ALINK4_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK4_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "ALINK5_OUT_TOTAL_UTILIZATION",
> + "BriefDescription": "ALINK5_OUT_TOTAL_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_ALINK5_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_ALINK5_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_ALINK5_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK5_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "ALINK6_OUT_TOTAL_UTILIZATION",
> + "BriefDescription": "ALINK6_OUT_TOTAL_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_ALINK6_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_ALINK6_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_ALINK6_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK6_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "ALINK7_OUT_TOTAL_UTILIZATION",
> + "BriefDescription": "ALINK7_OUT_TOTAL_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_ALINK7_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_ALINK7_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_ALINK7_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK7_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "ALINK0_OUT_DATA_UTILIZATION",
> + "BriefDescription": "ALINK0_OUT_DATA_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_ALINK0_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_ALINK0_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_ALINK0_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK0_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1.063%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "ALINK1_OUT_DATA_UTILIZATION",
> + "BriefDescription": "ALINK1_OUT_DATA_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_ALINK1_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_ALINK1_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_ALINK1_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK1_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1.063%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "ALINK2_OUT_DATA_UTILIZATION",
> + "BriefDescription": "ALINK2_OUT_DATA_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_ALINK2_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_ALINK2_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_ALINK2_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK2_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1.063%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "ALINK3_OUT_DATA_UTILIZATION",
> + "BriefDescription": "ALINK3_OUT_DATA_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_ALINK3_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_ALINK3_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_ALINK3_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK3_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1.063%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "ALINK4_OUT_DATA_UTILIZATION",
> + "BriefDescription": "ALINK4_OUT_DATA_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_ALINK4_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_ALINK4_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_ALINK4_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK4_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1.063%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "ALINK5_OUT_DATA_UTILIZATION",
> + "BriefDescription": "ALINK5_OUT_DATA_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_ALINK5_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_ALINK5_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_ALINK5_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK5_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1.063%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "ALINK6_OUT_DATA_UTILIZATION",
> + "BriefDescription": "ALINK6_OUT_DATA_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_ALINK6_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_ALINK6_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_ALINK6_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK6_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1.063%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "ALINK7_OUT_DATA_UTILIZATION",
> + "BriefDescription": "ALINK7_OUT_DATA_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_ALINK7_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_ALINK7_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_ALINK7_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK7_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1.063%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_DATA_BANDWIDTH_TRANSFERRED_OVER_PB_PCI1",
> + "BriefDescription": "TOTAL_DATA_BANDWIDTH_TRANSFERRED_OVER_PB_PCI1",
> + "MetricExpr": "(hv_24x7@PM_PCI1_32B_INOUT\\,chip\\=?@)",
> + "ScaleUnit": "3.28e-2MB",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_DATA_BANDWIDTH_TRANSFERRED_OVER_PB_PCI0",
> + "BriefDescription": "TOTAL_DATA_BANDWIDTH_TRANSFERRED_OVER_PB_PCI0",
> + "MetricExpr": "(hv_24x7@PM_PCI0_32B_INOUT\\,chip\\=?@)",
> + "ScaleUnit": "3.28e-2MB",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_MCS_READ_BW_MC0_CHAN01",
> + "BriefDescription": "TOTAL_MCS_READ_BW_MC0_CHAN01",
> + "MetricExpr": "(hv_24x7@PM_MCS_128B_RD_DATA_BLOCKS_MC0_CHAN01\\,chip\\=?@)",
> + "ScaleUnit": "5.24e-1MB",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_MCS_READ_BW_MC1_CHAN01",
> + "BriefDescription": "TOTAL_MCS_READ_BW_MC1_CHAN01",
> + "MetricExpr": "(hv_24x7@PM_MCS_128B_RD_DATA_BLOCKS_MC1_CHAN01\\,chip\\=?@)",
> + "ScaleUnit": "5.24e-1MB",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_MCS_READ_BW_MC2_CHAN01",
> + "BriefDescription": "TOTAL_MCS_READ_BW_MC2_CHAN01",
> + "MetricExpr": "(hv_24x7@PM_MCS_128B_RD_DATA_BLOCKS_MC2_CHAN01\\,chip\\=?@)",
> + "ScaleUnit": "5.24e-1MB",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_MCS_READ_BW_MC3_CHAN01",
> + "BriefDescription": "TOTAL_MCS_READ_BW_MC3_CHAN01",
> + "MetricExpr": "(hv_24x7@PM_MCS_128B_RD_DATA_BLOCKS_MC3_CHAN01\\,chip\\=?@)",
> + "ScaleUnit": "5.24e-1MB",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_MCS_WRITE_BW_MC0_CHAN01",
> + "BriefDescription": "TOTAL_MCS_WRITE_BW_MC0_CHAN01",
> + "MetricExpr": "(hv_24x7@PM_MCS_64B_WR_DATA_BLOCKS_MC0_CHAN01\\,chip\\=?@)",
> + "ScaleUnit": "2.6e-1MB",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_MCS_WRITE_BW_MC1_CHAN01",
> + "BriefDescription": "TOTAL_MCS_WRITE_BW_MC1_CHAN01",
> + "MetricExpr": "(hv_24x7@PM_MCS_64B_WR_DATA_BLOCKS_MC1_CHAN01\\,chip\\=?@)",
> + "ScaleUnit": "2.6e-1MB",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_MCS_WRITE_BW_MC2_CHAN01",
> + "BriefDescription": "TOTAL_MCS_WRITE_BW_MC2_CHAN01",
> + "MetricExpr": "(hv_24x7@PM_MCS_64B_WR_DATA_BLOCKS_MC2_CHAN01\\,chip\\=?@)",
> + "ScaleUnit": "2.6e-1MB",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_MCS_WRITE_BW_MC3_CHAN01",
> + "BriefDescription": "TOTAL_MCS_WRITE_BW_MC3_CHAN01",
> + "MetricExpr": "(hv_24x7@PM_MCS_64B_WR_DATA_BLOCKS_MC3_CHAN01\\,chip\\=?@)",
> + "ScaleUnit": "2.6e-1MB",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricExpr": "(hv_24x7@PM_MCS_128B_RD_DATA_BLOCKS_MC0_CHAN01\\,chip\\=?@ + hv_24x7@PM_MCS_128B_RD_DATA_BLOCKS_MC1_CHAN01\\,chip\\=?@ + hv_24x7@PM_MCS_128B_RD_DATA_BLOCKS_MC2_CHAN01\\,chip\\=?@ + hv_24x7@PM_MCS_128B_RD_DATA_BLOCKS_MC3_CHAN01\\,chip\\=?@)",
> + "MetricName": "Memory_RD_BW_Chip",
> + "MetricGroup": "Memory_BW",
> + "ScaleUnit": "5.24e-1MB",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricExpr": "(hv_24x7@PM_MCS_64B_WR_DATA_BLOCKS_MC0_CHAN01\\,chip\\=?@ + hv_24x7@PM_MCS_64B_WR_DATA_BLOCKS_MC1_CHAN01\\,chip\\=?@ + hv_24x7@PM_MCS_64B_WR_DATA_BLOCKS_MC2_CHAN01\\,chip\\=?@ + hv_24x7@PM_MCS_64B_WR_DATA_BLOCKS_MC3_CHAN01\\,chip\\=?@ )",
> + "MetricName": "Memory_WR_BW_Chip",
> + "MetricGroup": "Memory_BW",
> + "ScaleUnit": "2.6e-1MB",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricExpr": "(hv_24x7@PM_PAU_CYC\\,chip\\=?@ )",
> + "MetricName": "PowerBUS_Frequency",
> + "ScaleUnit": "2.56e-7GHz",
> + "AggregationMode": "PerChip"
> + }
> +]
>
--
Thanks and Regards
R.Nageswara Sastry
^ permalink raw reply
* Re: [PATCH v2 1/4] mm: pagewalk: Fix walk for hugepage tables
From: Michael Ellerman @ 2021-06-25 23:46 UTC (permalink / raw)
To: Christophe Leroy, akpm
Cc: linux-arch, linux-kernel, Steven Price, linux-mm,
Oliver O'Halloran, Paul Mackerras, linuxppc-dev, dja
In-Reply-To: <217a6b38-a6ac-84d5-e3dc-257331431bb2@csgroup.eu>
Christophe Leroy <christophe.leroy@csgroup.eu> writes:
> Le 25/06/2021 à 06:45, Michael Ellerman a écrit :
>> Christophe Leroy <christophe.leroy@csgroup.eu> writes:
>>> Hi Michael,
>>>
>>> Le 19/04/2021 à 12:47, Christophe Leroy a écrit :
>>>> Pagewalk ignores hugepd entries and walk down the tables
>>>> as if it was traditionnal entries, leading to crazy result.
>>>>
>>>> Add walk_hugepd_range() and use it to walk hugepage tables.
>>>
>>> I see you took patch 2 and 3 of the series.
>>
>> Yeah I decided those were bug fixes so could be taken separately.
>>
>>> Do you expect Andrew to take patch 1 via mm tree, and then you'll take
>>> patch 4 once mm tree is merged ?
>>
>> I didn't feel I could take patch 1 via the powerpc tree without risking
>> conflicts.
>>
>> Andrew could take patch 1 and 4 via mm, though he might not want to pick
>> them up this late.
>
> Patch 4 needs patches 2 and 3 and doesn't apply without them so it is not that easy.
Ah duh, sorry.
> Maybe Andrew you can take patch 1 now and then Michael you can take patch 4 at anytime during 5.15
> preparation without any conflict risk ?
Yeah that would work.
>> I guess step one would be to repost 1 and 4 as a new series. Either they
>> can go via mm, or for 5.15 I could probably take them both as long as I
>> pick them up early enough.
>>
>
> I'll first repost patch 1 as standalone and see what happens.
Thanks.
cheers
^ permalink raw reply
* [PATCH 0/9] sections: Unify kernel sections range check and use
From: Kefeng Wang @ 2021-06-26 7:34 UTC (permalink / raw)
To: Arnd Bergmann, linux-arch, linux-kernel
Cc: linux-s390, Kefeng Wang, bpf, linuxppc-dev, iommu
There are three head files(kallsyms.h, kernel.h and sections.h) which
include the kernel sections range check, let's make some cleanup and
unify them.
1. cleanup arch specific text/data check and fix address boundary check in kallsyms.h
2. make all the basic kernel range check function into sections.h
3. update all the callers, and use the helper in sections.h to simplify the code
4. use memory_intersects() in sections.h instead of private overlap for dma-debug
Cc: linuxppc-dev@lists.ozlabs.org
Cc: linux-s390@vger.kernel.org
Cc: linux-arch@vger.kernel.org
Cc: iommu@lists.linux-foundation.org
Cc: bpf@vger.kernel.org
Kefeng Wang (9):
kallsyms: Remove arch specific text and data check
kallsyms: Fix address-checks for kernel related range
sections: Move and rename core_kernel_data() to is_kernel_data()
sections: Move is_kernel_inittext() into sections.h
kallsyms: Rename is_kernel() and is_kernel_text()
sections: Add new is_kernel() and is_kernel_text()
s390: kprobes: Use is_kernel() helper
powerpc/mm: Use is_kernel_text() and is_kernel_inittext() helper
dma-debug: Use memory_intersects() directly
arch/powerpc/mm/pgtable_32.c | 7 +---
arch/s390/kernel/kprobes.c | 9 +----
arch/x86/kernel/unwind_orc.c | 2 +-
arch/x86/net/bpf_jit_comp.c | 2 +-
include/asm-generic/sections.h | 71 ++++++++++++++++++++++++++--------
include/linux/kallsyms.h | 21 +++-------
include/linux/kernel.h | 2 -
kernel/cfi.c | 2 +-
kernel/dma/debug.c | 14 +------
kernel/extable.c | 33 ++--------------
kernel/locking/lockdep.c | 3 --
kernel/trace/ftrace.c | 2 +-
mm/kasan/report.c | 2 +-
net/sysctl_net.c | 2 +-
14 files changed, 76 insertions(+), 96 deletions(-)
--
2.26.2
^ permalink raw reply
* [PATCH 8/9] powerpc/mm: Use is_kernel_text() and is_kernel_inittext() helper
From: Kefeng Wang @ 2021-06-26 7:34 UTC (permalink / raw)
To: Arnd Bergmann, linux-arch, linux-kernel
Cc: Kefeng Wang, Paul Mackerras, linuxppc-dev
In-Reply-To: <20210626073439.150586-1-wangkefeng.wang@huawei.com>
Use is_kernel_text() and is_kernel_inittext() helper to simplify code,
also drop etext, _stext, _sinittext, _einittext declaration which
already declared in section.h.
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: linuxppc-dev@lists.ozlabs.org
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
arch/powerpc/mm/pgtable_32.c | 7 ++-----
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/mm/pgtable_32.c b/arch/powerpc/mm/pgtable_32.c
index dcf5ecca19d9..13c798308c2e 100644
--- a/arch/powerpc/mm/pgtable_32.c
+++ b/arch/powerpc/mm/pgtable_32.c
@@ -33,8 +33,6 @@
#include <mm/mmu_decl.h>
-extern char etext[], _stext[], _sinittext[], _einittext[];
-
static u8 early_fixmap_pagetable[FIXMAP_PTE_SIZE] __page_aligned_data;
notrace void __init early_ioremap_init(void)
@@ -104,14 +102,13 @@ static void __init __mapin_ram_chunk(unsigned long offset, unsigned long top)
{
unsigned long v, s;
phys_addr_t p;
- int ktext;
+ bool ktext;
s = offset;
v = PAGE_OFFSET + s;
p = memstart_addr + s;
for (; s < top; s += PAGE_SIZE) {
- ktext = ((char *)v >= _stext && (char *)v < etext) ||
- ((char *)v >= _sinittext && (char *)v < _einittext);
+ ktext = (is_kernel_text(v) || is_kernel_inittext(v));
map_kernel_page(v, p, ktext ? PAGE_KERNEL_TEXT : PAGE_KERNEL);
v += PAGE_SIZE;
p += PAGE_SIZE;
--
2.26.2
^ permalink raw reply related
* Re: [PATCH] powerpc: mark local variables around longjmp as volatile
From: Michael Ellerman @ 2021-06-26 10:37 UTC (permalink / raw)
To: Michael Ellerman, Arnd Bergmann
Cc: Ravi Bangoria, Arnd Bergmann, linux-kernel, Paul Mackerras,
Nicholas Piggin, linuxppc-dev
In-Reply-To: <20210429080708.1520360-1-arnd@kernel.org>
On Thu, 29 Apr 2021 10:06:38 +0200, Arnd Bergmann wrote:
> gcc-11 points out that modifying local variables next to a
> longjmp/setjmp may cause undefined behavior:
>
> arch/powerpc/kexec/crash.c: In function 'crash_kexec_prepare_cpus.constprop':
> arch/powerpc/kexec/crash.c:108:22: error: variable 'ncpus' might be clobbered by 'longjmp' or 'vfork' [-Werror=clobbere
> d]
> arch/powerpc/kexec/crash.c:109:13: error: variable 'tries' might be clobbered by 'longjmp' or 'vfork' [-Werror=clobbere
> d]
> arch/powerpc/xmon/xmon.c: In function 'xmon_print_symbol':
> arch/powerpc/xmon/xmon.c:3625:21: error: variable 'name' might be clobbered by 'longjmp' or 'vfork' [-Werror=clobbered]
> arch/powerpc/xmon/xmon.c: In function 'stop_spus':
> arch/powerpc/xmon/xmon.c:4057:13: error: variable 'i' might be clobbered by 'longjmp' or 'vfork' [-Werror=clobbered]
> arch/powerpc/xmon/xmon.c: In function 'restart_spus':
> arch/powerpc/xmon/xmon.c:4098:13: error: variable 'i' might be clobbered by 'longjmp' or 'vfork' [-Werror=clobbered]
> arch/powerpc/xmon/xmon.c: In function 'dump_opal_msglog':
> arch/powerpc/xmon/xmon.c:3008:16: error: variable 'pos' might be clobbered by 'longjmp' or 'vfork' [-Werror=clobbered]
> arch/powerpc/xmon/xmon.c: In function 'show_pte':
> arch/powerpc/xmon/xmon.c:3207:29: error: variable 'tsk' might be clobbered by 'longjmp' or 'vfork' [-Werror=clobbered]
> arch/powerpc/xmon/xmon.c: In function 'show_tasks':
> arch/powerpc/xmon/xmon.c:3302:29: error: variable 'tsk' might be clobbered by 'longjmp' or 'vfork' [-Werror=clobbered]
> arch/powerpc/xmon/xmon.c: In function 'xmon_core':
> arch/powerpc/xmon/xmon.c:494:13: error: variable 'cmd' might be clobbered by 'longjmp' or 'vfork' [-Werror=clobbered]
> arch/powerpc/xmon/xmon.c:860:21: error: variable 'bp' might be clobbered by 'longjmp' or 'vfork' [-Werror=clobbered]
> arch/powerpc/xmon/xmon.c:860:21: error: variable 'bp' might be clobbered by 'longjmp' or 'vfork' [-Werror=clobbered]
> arch/powerpc/xmon/xmon.c:492:48: error: argument 'fromipi' might be clobbered by 'longjmp' or 'vfork' [-Werror=clobbered]
>
> [...]
Applied to powerpc/next.
[1/1] powerpc: mark local variables around longjmp as volatile
https://git.kernel.org/powerpc/c/a2305e3de819394a7adf68078964a92d06f9db33
cheers
^ permalink raw reply
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