* [PATCH] powerpc/64s/hash: Fix SLB preload cache vs kthread_use_mm
From: Nicholas Piggin @ 2021-07-08 9:05 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Nicholas Piggin, Christopher M . Riedl
It's possible for kernel threads to pick up SLB preload entries if
they are accessing userspace with kthread_use_mm. If the kthread
later is context switched while using a different mm, when it is
switched back it could preload SLBs belonging to the previous mm.
This could lead to data corruption, leaks, SLB multi hits, etc.
In the absence of a usable hook to clear preloads when unusing an
mm, fix it by keeping track of the mm that the preloads belong to.
Adjust the isync() comment to be clear it can't be skipped if we
had no preloads.
Fixes: 5434ae74629a ("powerpc/64s/hash: Add a SLB preload cache")
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/include/asm/thread_info.h | 1 +
arch/powerpc/mm/book3s64/slb.c | 36 ++++++++++++++++++--------
2 files changed, 26 insertions(+), 11 deletions(-)
diff --git a/arch/powerpc/include/asm/thread_info.h b/arch/powerpc/include/asm/thread_info.h
index b4ec6c7dd72e..c3de13dde2af 100644
--- a/arch/powerpc/include/asm/thread_info.h
+++ b/arch/powerpc/include/asm/thread_info.h
@@ -54,6 +54,7 @@ struct thread_info {
#if defined(CONFIG_VIRT_CPU_ACCOUNTING_NATIVE) && defined(CONFIG_PPC32)
struct cpu_accounting_data accounting;
#endif
+ struct mm_struct *slb_preload_mm;
unsigned char slb_preload_nr;
unsigned char slb_preload_tail;
u32 slb_preload_esid[SLB_PRELOAD_NR];
diff --git a/arch/powerpc/mm/book3s64/slb.c b/arch/powerpc/mm/book3s64/slb.c
index c91bd85eb90e..4f9dbce0dd84 100644
--- a/arch/powerpc/mm/book3s64/slb.c
+++ b/arch/powerpc/mm/book3s64/slb.c
@@ -294,11 +294,20 @@ static bool preload_hit(struct thread_info *ti, unsigned long esid)
return false;
}
-static bool preload_add(struct thread_info *ti, unsigned long ea)
+static bool preload_add(struct thread_info *ti, struct mm_struct *mm, unsigned long ea)
{
unsigned char idx;
unsigned long esid;
+ if (unlikely(ti->slb_preload_mm != mm)) {
+ /*
+ * kthread_use_mm or other temporary mm switching can
+ * change the mm being used by a particular thread.
+ */
+ ti->slb_preload_nr = 0;
+ ti->slb_preload_mm = mm;
+ }
+
if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) {
/* EAs are stored >> 28 so 256MB segments don't need clearing */
if (ea & ESID_MASK_1T)
@@ -362,13 +371,13 @@ void slb_setup_new_exec(void)
* 0x10000000 so it makes sense to preload this segment.
*/
if (!is_kernel_addr(exec)) {
- if (preload_add(ti, exec))
+ if (preload_add(ti, mm, exec))
slb_allocate_user(mm, exec);
}
/* Libraries and mmaps. */
if (!is_kernel_addr(mm->mmap_base)) {
- if (preload_add(ti, mm->mmap_base))
+ if (preload_add(ti, mm, mm->mmap_base))
slb_allocate_user(mm, mm->mmap_base);
}
@@ -394,19 +403,19 @@ void preload_new_slb_context(unsigned long start, unsigned long sp)
/* Userspace entry address. */
if (!is_kernel_addr(start)) {
- if (preload_add(ti, start))
+ if (preload_add(ti, mm, start))
slb_allocate_user(mm, start);
}
/* Top of stack, grows down. */
if (!is_kernel_addr(sp)) {
- if (preload_add(ti, sp))
+ if (preload_add(ti, mm, sp))
slb_allocate_user(mm, sp);
}
/* Bottom of heap, grows up. */
if (heap && !is_kernel_addr(heap)) {
- if (preload_add(ti, heap))
+ if (preload_add(ti, mm, heap))
slb_allocate_user(mm, heap);
}
@@ -502,6 +511,11 @@ void switch_slb(struct task_struct *tsk, struct mm_struct *mm)
copy_mm_to_paca(mm);
+ if (unlikely(ti->slb_preload_mm != mm)) {
+ ti->slb_preload_nr = 0;
+ ti->slb_preload_mm = mm;
+ }
+
/*
* We gradually age out SLBs after a number of context switches to
* reduce reload overhead of unused entries (like we do with FP/VEC
@@ -513,7 +527,7 @@ void switch_slb(struct task_struct *tsk, struct mm_struct *mm)
unsigned long pc = KSTK_EIP(tsk);
preload_age(ti);
- preload_add(ti, pc);
+ preload_add(ti, mm, pc);
}
for (i = 0; i < ti->slb_preload_nr; i++) {
@@ -527,9 +541,9 @@ void switch_slb(struct task_struct *tsk, struct mm_struct *mm)
}
/*
- * Synchronize slbmte preloads with possible subsequent user memory
- * address accesses by the kernel (user mode won't happen until
- * rfid, which is safe).
+ * Synchronize slbias and slbmte preloads with possible subsequent user
+ * memory address accesses by the kernel (user mode won't happen until
+ * rfid, which is synchronizing).
*/
isync();
}
@@ -863,7 +877,7 @@ DEFINE_INTERRUPT_HANDLER_RAW(do_slb_fault)
err = slb_allocate_user(mm, ea);
if (!err)
- preload_add(current_thread_info(), ea);
+ preload_add(current_thread_info(), mm, ea);
return err;
}
--
2.23.0
^ permalink raw reply related
* Re: [PATCH v2 0/4] bus: Make remove callback return void
From: Uwe Kleine-König @ 2021-07-08 5:38 UTC (permalink / raw)
To: Sven Van Asbroeck
Cc: nvdimm, Alexey Kardashevskiy, Samuel Iglesias Gonsalvez,
Jens Taprogge, Alison Schofield, Jaroslav Kysela,
Benjamin Tissoires, Paul Mackerras, Srinivas Pandruvada,
K. Y. Srinivasan, Mike Christie, Wei Liu, Maxim Levitsky,
Samuel Holland, Takashi Iwai, linux-acpi, Tom Rix, xen-devel,
Tomas Winkler, Jason Wang, Ohad Ben-Cohen, Alex Williamson,
Alex Elder, Martin K. Petersen, Geoff Levand, Greg Kroah-Hartman,
linux-usb, linux-wireless, Linux Kernel Mailing List, linux-spi,
Kai-Heng Feng, Sascha Hauer, Jon Mason, linux-ntb, linux-media,
David Woodhouse, Krzysztof Wilczyński, Alexandre Belloni,
Manohar Vanga, Rafael J. Wysocki, Dominik Brodowski,
virtualization, James E.J. Bottomley, target-devel,
Srinivas Kandagatla, linux-i2c, Stefano Stabellini,
Stephen Hemminger, Jiri Slaby, Helge Deller,
Rafał Miłecki, industrypack-devel, Wu Hao, alsa-devel,
linux-arm-msm, Maxime Ripard, William Breathitt Gray, greybus-dev,
Bjorn Helgaas, Mark Gross, Boris Ostrovsky, Mika Westerberg,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
Johannes Thumshirn, Mathieu Poirier, Stephen Boyd, Cornelia Huck,
Wolfram Sang, Joey Pabalan, Yehezkel Bernat, Pali Rohár,
Len Brown, Bodo Stroesser, Ulf Hansson, Heikki Krogerus,
Tyrel Datwyler, Alexander Shishkin, linux-pci, Julien Grall,
SeongJae Park, linux-hyperv, platform-driver-x86, Frank Li,
Ira Weiny, Rob Herring, Lorenzo Pieralisi, Dave Jiang,
linux-staging, Dexuan Cui, Jernej Skrabec, Kishon Vijay Abraham I,
Chen-Yu Tsai, linux-input, Allen Hubbe, Alex Dubov, Haiyang Zhang,
Jiri Kosina, Vladimir Zapolskiy, Ben Widawsky, Moritz Fischer,
linux-cxl, Michael Buesch, Dan Williams, Mauro Carvalho Chehab,
Cristian Marussi, Thomas Bogendoerfer, linux-parisc, Martyn Welch,
Dmitry Torokhov, linux-mmc, linux-sunxi, Stefan Richter,
Sudeep Holla, David S. Miller, kvm, Michael S. Tsirkin,
linux-remoteproc, Maximilian Luz, Bjorn Andersson, Kirti Wankhede,
Andreas Noever, linux-i3c, linux1394-devel, Lee Jones,
Arnd Bergmann, linux-scsi, Vishal Verma, Russell King,
Thorsten Scherer, Andy Gross, linux-serial, Jakub Kicinski,
Michael Jamet, Johan Hovold, Hans de Goede, Hannes Reinecke,
Adrian Hunter, Johannes Berg, Juergen Gross, netdev, linux-mips,
Alexandre Bounine, Vinod Koul, Mark Brown, Marc Zyngier,
dmaengine, linux-fpga, linuxppc-dev
In-Reply-To: <CAGngYiWm4u27o-yy5L5tokMB5G1RUR5uYmKf2oXah2P3J=hK2A@mail.gmail.com>
[-- Attachment #1: Type: text/plain, Size: 560 bytes --]
On Wed, Jul 07, 2021 at 10:08:53PM -0400, Sven Van Asbroeck wrote:
> On Tue, Jul 6, 2021 at 11:50 AM Uwe Kleine-König
> <u.kleine-koenig@pengutronix.de> wrote:
> >
> > drivers/staging/fieldbus/anybuss/host.c | 4 +---
>
> Awesome !
>
> Acked-by: Sven Van Asbroeck <TheSven73@gmail.com>
I note that as an Ack for patch 4 only, as the others don't touch this
file.
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-König |
Industrial Linux Solutions | https://www.pengutronix.de/ |
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply
* Re: [RFC PATCH 27/43] KVM: PPC: Book3S HV P9: Move host OS save/restore functions to built-in
From: Athira Rajeev @ 2021-07-08 5:32 UTC (permalink / raw)
To: Nicholas Piggin; +Cc: linuxppc-dev, kvm-ppc
In-Reply-To: <20210622105736.633352-28-npiggin@gmail.com>
> On 22-Jun-2021, at 4:27 PM, Nicholas Piggin <npiggin@gmail.com> wrote:
>
> Move the P9 guest/host register switching functions to the built-in
> P9 entry code, and export it for nested to use as well.
>
> This allows more flexibility in scheduling these supervisor privileged
> SPR accesses with the HV privileged and PR SPR accesses in the low level
> entry code.
>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> ---
> arch/powerpc/kvm/book3s_hv.c | 351 +-------------------------
> arch/powerpc/kvm/book3s_hv.h | 39 +++
> arch/powerpc/kvm/book3s_hv_p9_entry.c | 332 ++++++++++++++++++++++++
> 3 files changed, 372 insertions(+), 350 deletions(-)
> create mode 100644 arch/powerpc/kvm/book3s_hv.h
>
> diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
> index 35749b0b663f..a7660af22161 100644
> --- a/arch/powerpc/kvm/book3s_hv.c
> +++ b/arch/powerpc/kvm/book3s_hv.c
> @@ -79,6 +79,7 @@
> #include <asm/dtl.h>
>
> #include "book3s.h"
> +#include "book3s_hv.h"
>
> #define CREATE_TRACE_POINTS
> #include "trace_hv.h"
> @@ -3675,356 +3676,6 @@ static noinline void kvmppc_run_core(struct kvmppc_vcore *vc)
> trace_kvmppc_run_core(vc, 1);
> }
>
> -/*
> - * Privileged (non-hypervisor) host registers to save.
> - */
> -struct p9_host_os_sprs {
> - unsigned long dscr;
> - unsigned long tidr;
> - unsigned long iamr;
> - unsigned long amr;
> - unsigned long fscr;
> -
> - unsigned int pmc1;
> - unsigned int pmc2;
> - unsigned int pmc3;
> - unsigned int pmc4;
> - unsigned int pmc5;
> - unsigned int pmc6;
> - unsigned long mmcr0;
> - unsigned long mmcr1;
> - unsigned long mmcr2;
> - unsigned long mmcr3;
> - unsigned long mmcra;
> - unsigned long siar;
> - unsigned long sier1;
> - unsigned long sier2;
> - unsigned long sier3;
> - unsigned long sdar;
> -};
> -
> -static void freeze_pmu(unsigned long mmcr0, unsigned long mmcra)
> -{
> - if (!(mmcr0 & MMCR0_FC))
> - goto do_freeze;
> - if (mmcra & MMCRA_SAMPLE_ENABLE)
> - goto do_freeze;
> - if (cpu_has_feature(CPU_FTR_ARCH_31)) {
> - if (!(mmcr0 & MMCR0_PMCCEXT))
> - goto do_freeze;
> - if (!(mmcra & MMCRA_BHRB_DISABLE))
> - goto do_freeze;
> - }
> - return;
> -
> -do_freeze:
> - mmcr0 = MMCR0_FC;
> - mmcra = 0;
> - if (cpu_has_feature(CPU_FTR_ARCH_31)) {
> - mmcr0 |= MMCR0_PMCCEXT;
> - mmcra = MMCRA_BHRB_DISABLE;
> - }
> -
> - mtspr(SPRN_MMCR0, mmcr0);
> - mtspr(SPRN_MMCRA, mmcra);
> - isync();
> -}
> -
> -static void switch_pmu_to_guest(struct kvm_vcpu *vcpu,
> - struct p9_host_os_sprs *host_os_sprs)
> -{
> - struct lppaca *lp;
> - int load_pmu = 1;
> -
> - lp = vcpu->arch.vpa.pinned_addr;
> - if (lp)
> - load_pmu = lp->pmcregs_in_use;
> -
> - if (load_pmu)
> - vcpu->arch.hfscr |= HFSCR_PM;
> -
> - /* Save host */
> - if (ppc_get_pmu_inuse()) {
> - /*
> - * It might be better to put PMU handling (at least for the
> - * host) in the perf subsystem because it knows more about what
> - * is being used.
> - */
> -
> - /* POWER9, POWER10 do not implement HPMC or SPMC */
> -
> - host_os_sprs->mmcr0 = mfspr(SPRN_MMCR0);
> - host_os_sprs->mmcra = mfspr(SPRN_MMCRA);
> -
> - freeze_pmu(host_os_sprs->mmcr0, host_os_sprs->mmcra);
> -
> - host_os_sprs->pmc1 = mfspr(SPRN_PMC1);
> - host_os_sprs->pmc2 = mfspr(SPRN_PMC2);
> - host_os_sprs->pmc3 = mfspr(SPRN_PMC3);
> - host_os_sprs->pmc4 = mfspr(SPRN_PMC4);
> - host_os_sprs->pmc5 = mfspr(SPRN_PMC5);
> - host_os_sprs->pmc6 = mfspr(SPRN_PMC6);
> - host_os_sprs->mmcr1 = mfspr(SPRN_MMCR1);
> - host_os_sprs->mmcr2 = mfspr(SPRN_MMCR2);
> - host_os_sprs->sdar = mfspr(SPRN_SDAR);
> - host_os_sprs->siar = mfspr(SPRN_SIAR);
> - host_os_sprs->sier1 = mfspr(SPRN_SIER);
> -
> - if (cpu_has_feature(CPU_FTR_ARCH_31)) {
> - host_os_sprs->mmcr3 = mfspr(SPRN_MMCR3);
> - host_os_sprs->sier2 = mfspr(SPRN_SIER2);
> - host_os_sprs->sier3 = mfspr(SPRN_SIER3);
> - }
> - }
> -
> -#ifdef CONFIG_PPC_PSERIES
> - if (kvmhv_on_pseries()) {
> - if (vcpu->arch.vpa.pinned_addr) {
> - struct lppaca *lp = vcpu->arch.vpa.pinned_addr;
> - get_lppaca()->pmcregs_in_use = lp->pmcregs_in_use;
> - } else {
> - get_lppaca()->pmcregs_in_use = 1;
> - }
> - }
> -#endif
> -
> - /* Load guest */
> - if (vcpu->arch.hfscr & HFSCR_PM) {
> - mtspr(SPRN_PMC1, vcpu->arch.pmc[0]);
> - mtspr(SPRN_PMC2, vcpu->arch.pmc[1]);
> - mtspr(SPRN_PMC3, vcpu->arch.pmc[2]);
> - mtspr(SPRN_PMC4, vcpu->arch.pmc[3]);
> - mtspr(SPRN_PMC5, vcpu->arch.pmc[4]);
> - mtspr(SPRN_PMC6, vcpu->arch.pmc[5]);
> - mtspr(SPRN_MMCR1, vcpu->arch.mmcr[1]);
> - mtspr(SPRN_MMCR2, vcpu->arch.mmcr[2]);
> - mtspr(SPRN_SDAR, vcpu->arch.sdar);
> - mtspr(SPRN_SIAR, vcpu->arch.siar);
> - mtspr(SPRN_SIER, vcpu->arch.sier[0]);
> -
> - if (cpu_has_feature(CPU_FTR_ARCH_31)) {
> - mtspr(SPRN_MMCR3, vcpu->arch.mmcr[4]);
Hi Nick,
Have a doubt here..
For MMCR3, it is vcpu->arch.mmcr[3) ?
Thanks
Athira
> - mtspr(SPRN_SIER2, vcpu->arch.sier[1]);
> - mtspr(SPRN_SIER3, vcpu->arch.sier[2]);
> - }
> -
> - /* Set MMCRA then MMCR0 last */
> - mtspr(SPRN_MMCRA, vcpu->arch.mmcra);
> - mtspr(SPRN_MMCR0, vcpu->arch.mmcr[0]);
> - /* No isync necessary because we're starting counters */
> - }
> -}
> -
> -static void switch_pmu_to_host(struct kvm_vcpu *vcpu,
> - struct p9_host_os_sprs *host_os_sprs)
> -{
> - struct lppaca *lp;
> - int save_pmu = 1;
> -
> - lp = vcpu->arch.vpa.pinned_addr;
> - if (lp)
> - save_pmu = lp->pmcregs_in_use;
> -
> - if (save_pmu) {
> - vcpu->arch.mmcr[0] = mfspr(SPRN_MMCR0);
> - vcpu->arch.mmcra = mfspr(SPRN_MMCRA);
> -
> - freeze_pmu(vcpu->arch.mmcr[0], vcpu->arch.mmcra);
> -
> - vcpu->arch.pmc[0] = mfspr(SPRN_PMC1);
> - vcpu->arch.pmc[1] = mfspr(SPRN_PMC2);
> - vcpu->arch.pmc[2] = mfspr(SPRN_PMC3);
> - vcpu->arch.pmc[3] = mfspr(SPRN_PMC4);
> - vcpu->arch.pmc[4] = mfspr(SPRN_PMC5);
> - vcpu->arch.pmc[5] = mfspr(SPRN_PMC6);
> - vcpu->arch.mmcr[1] = mfspr(SPRN_MMCR1);
> - vcpu->arch.mmcr[2] = mfspr(SPRN_MMCR2);
> - vcpu->arch.sdar = mfspr(SPRN_SDAR);
> - vcpu->arch.siar = mfspr(SPRN_SIAR);
> - vcpu->arch.sier[0] = mfspr(SPRN_SIER);
> -
> - if (cpu_has_feature(CPU_FTR_ARCH_31)) {
> - vcpu->arch.mmcr[3] = mfspr(SPRN_MMCR3);
> - vcpu->arch.sier[1] = mfspr(SPRN_SIER2);
> - vcpu->arch.sier[2] = mfspr(SPRN_SIER3);
> - }
> -
> - } else if (vcpu->arch.hfscr & HFSCR_PM) {
> - /*
> - * The guest accessed PMC SPRs without specifying they should
> - * be preserved. Stop them from counting if the guest had
> - * started anything.
> - */
> - freeze_pmu(mfspr(SPRN_MMCR0), mfspr(SPRN_MMCRA));
> -
> - /*
> - * Demand-fault PMU register access in the guest.
> - *
> - * This is used to grab the guest's VPA pmcregs_in_use value
> - * and reflect it into the host's VPA in the case of a nested
> - * hypervisor.
> - *
> - * It also avoids having to zero-out SPRs after each guest
> - * exit to avoid side-channels when.
> - *
> - * This is cleared here when we exit the guest, so later HFSCR
> - * interrupt handling can add it back to run the guest with
> - * PM enabled next time.
> - */
> - vcpu->arch.hfscr &= ~HFSCR_PM;
> - } /* otherwise the PMU should still be frozen from guest entry */
> -
> -#ifdef CONFIG_PPC_PSERIES
> - if (kvmhv_on_pseries())
> - get_lppaca()->pmcregs_in_use = ppc_get_pmu_inuse();
> -#endif
> -
> - if (ppc_get_pmu_inuse()) {
> - mtspr(SPRN_PMC1, host_os_sprs->pmc1);
> - mtspr(SPRN_PMC2, host_os_sprs->pmc2);
> - mtspr(SPRN_PMC3, host_os_sprs->pmc3);
> - mtspr(SPRN_PMC4, host_os_sprs->pmc4);
> - mtspr(SPRN_PMC5, host_os_sprs->pmc5);
> - mtspr(SPRN_PMC6, host_os_sprs->pmc6);
> - mtspr(SPRN_MMCR1, host_os_sprs->mmcr1);
> - mtspr(SPRN_MMCR2, host_os_sprs->mmcr2);
> - mtspr(SPRN_SDAR, host_os_sprs->sdar);
> - mtspr(SPRN_SIAR, host_os_sprs->siar);
> - mtspr(SPRN_SIER, host_os_sprs->sier1);
> -
> - if (cpu_has_feature(CPU_FTR_ARCH_31)) {
> - mtspr(SPRN_MMCR3, host_os_sprs->mmcr3);
> - mtspr(SPRN_SIER2, host_os_sprs->sier2);
> - mtspr(SPRN_SIER3, host_os_sprs->sier3);
> - }
> -
> - /* Set MMCRA then MMCR0 last */
> - mtspr(SPRN_MMCRA, host_os_sprs->mmcra);
> - mtspr(SPRN_MMCR0, host_os_sprs->mmcr0);
> - isync();
> - }
> -}
> -
> -static void load_spr_state(struct kvm_vcpu *vcpu,
> - struct p9_host_os_sprs *host_os_sprs)
> -{
> - mtspr(SPRN_TAR, vcpu->arch.tar);
> - mtspr(SPRN_EBBHR, vcpu->arch.ebbhr);
> - mtspr(SPRN_EBBRR, vcpu->arch.ebbrr);
> - mtspr(SPRN_BESCR, vcpu->arch.bescr);
> -
> - if (!cpu_has_feature(CPU_FTR_ARCH_31))
> - mtspr(SPRN_TIDR, vcpu->arch.tid);
> - if (host_os_sprs->iamr != vcpu->arch.iamr)
> - mtspr(SPRN_IAMR, vcpu->arch.iamr);
> - if (host_os_sprs->amr != vcpu->arch.amr)
> - mtspr(SPRN_AMR, vcpu->arch.amr);
> - if (vcpu->arch.uamor != 0)
> - mtspr(SPRN_UAMOR, vcpu->arch.uamor);
> - if (host_os_sprs->fscr != vcpu->arch.fscr)
> - mtspr(SPRN_FSCR, vcpu->arch.fscr);
> - if (host_os_sprs->dscr != vcpu->arch.dscr)
> - mtspr(SPRN_DSCR, vcpu->arch.dscr);
> - if (vcpu->arch.pspb != 0)
> - mtspr(SPRN_PSPB, vcpu->arch.pspb);
> -
> - /*
> - * DAR, DSISR, and for nested HV, SPRGs must be set with MSR[RI]
> - * clear (or hstate set appropriately to catch those registers
> - * being clobbered if we take a MCE or SRESET), so those are done
> - * later.
> - */
> -
> - if (!(vcpu->arch.ctrl & 1))
> - mtspr(SPRN_CTRLT, 0);
> -}
> -
> -static void store_spr_state(struct kvm_vcpu *vcpu)
> -{
> - vcpu->arch.tar = mfspr(SPRN_TAR);
> - vcpu->arch.ebbhr = mfspr(SPRN_EBBHR);
> - vcpu->arch.ebbrr = mfspr(SPRN_EBBRR);
> - vcpu->arch.bescr = mfspr(SPRN_BESCR);
> -
> - if (!cpu_has_feature(CPU_FTR_ARCH_31))
> - vcpu->arch.tid = mfspr(SPRN_TIDR);
> - vcpu->arch.iamr = mfspr(SPRN_IAMR);
> - vcpu->arch.amr = mfspr(SPRN_AMR);
> - vcpu->arch.uamor = mfspr(SPRN_UAMOR);
> - vcpu->arch.fscr = mfspr(SPRN_FSCR);
> - vcpu->arch.dscr = mfspr(SPRN_DSCR);
> - vcpu->arch.pspb = mfspr(SPRN_PSPB);
> -
> - vcpu->arch.ctrl = mfspr(SPRN_CTRLF);
> -}
> -
> -static void load_vcpu_state(struct kvm_vcpu *vcpu,
> - struct p9_host_os_sprs *host_os_sprs)
> -{
> - if (cpu_has_feature(CPU_FTR_TM) ||
> - cpu_has_feature(CPU_FTR_P9_TM_HV_ASSIST))
> - kvmppc_restore_tm_hv(vcpu, vcpu->arch.shregs.msr, true);
> -
> - load_spr_state(vcpu, host_os_sprs);
> -
> - load_fp_state(&vcpu->arch.fp);
> -#ifdef CONFIG_ALTIVEC
> - load_vr_state(&vcpu->arch.vr);
> -#endif
> - mtspr(SPRN_VRSAVE, vcpu->arch.vrsave);
> -}
> -
> -static void store_vcpu_state(struct kvm_vcpu *vcpu)
> -{
> - store_spr_state(vcpu);
> -
> - store_fp_state(&vcpu->arch.fp);
> -#ifdef CONFIG_ALTIVEC
> - store_vr_state(&vcpu->arch.vr);
> -#endif
> - vcpu->arch.vrsave = mfspr(SPRN_VRSAVE);
> -
> - if (cpu_has_feature(CPU_FTR_TM) ||
> - cpu_has_feature(CPU_FTR_P9_TM_HV_ASSIST))
> - kvmppc_save_tm_hv(vcpu, vcpu->arch.shregs.msr, true);
> -}
> -
> -static void save_p9_host_os_sprs(struct p9_host_os_sprs *host_os_sprs)
> -{
> - if (!cpu_has_feature(CPU_FTR_ARCH_31))
> - host_os_sprs->tidr = mfspr(SPRN_TIDR);
> - host_os_sprs->iamr = mfspr(SPRN_IAMR);
> - host_os_sprs->amr = mfspr(SPRN_AMR);
> - host_os_sprs->fscr = mfspr(SPRN_FSCR);
> - host_os_sprs->dscr = mfspr(SPRN_DSCR);
> -}
> -
> -/* vcpu guest regs must already be saved */
> -static void restore_p9_host_os_sprs(struct kvm_vcpu *vcpu,
> - struct p9_host_os_sprs *host_os_sprs)
> -{
> - mtspr(SPRN_SPRG_VDSO_WRITE, local_paca->sprg_vdso);
> -
> - if (!cpu_has_feature(CPU_FTR_ARCH_31))
> - mtspr(SPRN_TIDR, host_os_sprs->tidr);
> - if (host_os_sprs->iamr != vcpu->arch.iamr)
> - mtspr(SPRN_IAMR, host_os_sprs->iamr);
> - if (vcpu->arch.uamor != 0)
> - mtspr(SPRN_UAMOR, 0);
> - if (host_os_sprs->amr != vcpu->arch.amr)
> - mtspr(SPRN_AMR, host_os_sprs->amr);
> - if (host_os_sprs->fscr != vcpu->arch.fscr)
> - mtspr(SPRN_FSCR, host_os_sprs->fscr);
> - if (host_os_sprs->dscr != vcpu->arch.dscr)
> - mtspr(SPRN_DSCR, host_os_sprs->dscr);
> - if (vcpu->arch.pspb != 0)
> - mtspr(SPRN_PSPB, 0);
> -
> - /* Save guest CTRL register, set runlatch to 1 */
> - if (!(vcpu->arch.ctrl & 1))
> - mtspr(SPRN_CTRLT, 1);
> -}
> -
> static inline bool hcall_is_xics(unsigned long req)
> {
> return req == H_EOI || req == H_CPPR || req == H_IPI ||
> diff --git a/arch/powerpc/kvm/book3s_hv.h b/arch/powerpc/kvm/book3s_hv.h
> new file mode 100644
> index 000000000000..72e3a8f4c2cf
> --- /dev/null
> +++ b/arch/powerpc/kvm/book3s_hv.h
> @@ -0,0 +1,39 @@
> +
> +/*
> + * Privileged (non-hypervisor) host registers to save.
> + */
> +struct p9_host_os_sprs {
> + unsigned long dscr;
> + unsigned long tidr;
> + unsigned long iamr;
> + unsigned long amr;
> + unsigned long fscr;
> +
> + unsigned int pmc1;
> + unsigned int pmc2;
> + unsigned int pmc3;
> + unsigned int pmc4;
> + unsigned int pmc5;
> + unsigned int pmc6;
> + unsigned long mmcr0;
> + unsigned long mmcr1;
> + unsigned long mmcr2;
> + unsigned long mmcr3;
> + unsigned long mmcra;
> + unsigned long siar;
> + unsigned long sier1;
> + unsigned long sier2;
> + unsigned long sier3;
> + unsigned long sdar;
> +};
> +
> +void load_vcpu_state(struct kvm_vcpu *vcpu,
> + struct p9_host_os_sprs *host_os_sprs);
> +void store_vcpu_state(struct kvm_vcpu *vcpu);
> +void save_p9_host_os_sprs(struct p9_host_os_sprs *host_os_sprs);
> +void restore_p9_host_os_sprs(struct kvm_vcpu *vcpu,
> + struct p9_host_os_sprs *host_os_sprs);
> +void switch_pmu_to_guest(struct kvm_vcpu *vcpu,
> + struct p9_host_os_sprs *host_os_sprs);
> +void switch_pmu_to_host(struct kvm_vcpu *vcpu,
> + struct p9_host_os_sprs *host_os_sprs);
> diff --git a/arch/powerpc/kvm/book3s_hv_p9_entry.c b/arch/powerpc/kvm/book3s_hv_p9_entry.c
> index afdd7dfa1c08..cc74cd314fcf 100644
> --- a/arch/powerpc/kvm/book3s_hv_p9_entry.c
> +++ b/arch/powerpc/kvm/book3s_hv_p9_entry.c
> @@ -4,8 +4,340 @@
> #include <asm/asm-prototypes.h>
> #include <asm/dbell.h>
> #include <asm/kvm_ppc.h>
> +#include <asm/pmc.h>
> #include <asm/ppc-opcode.h>
>
> +#include "book3s_hv.h"
> +
> +static void freeze_pmu(unsigned long mmcr0, unsigned long mmcra)
> +{
> + if (!(mmcr0 & MMCR0_FC))
> + goto do_freeze;
> + if (mmcra & MMCRA_SAMPLE_ENABLE)
> + goto do_freeze;
> + if (cpu_has_feature(CPU_FTR_ARCH_31)) {
> + if (!(mmcr0 & MMCR0_PMCCEXT))
> + goto do_freeze;
> + if (!(mmcra & MMCRA_BHRB_DISABLE))
> + goto do_freeze;
> + }
> + return;
> +
> +do_freeze:
> + mmcr0 = MMCR0_FC;
> + mmcra = 0;
> + if (cpu_has_feature(CPU_FTR_ARCH_31)) {
> + mmcr0 |= MMCR0_PMCCEXT;
> + mmcra = MMCRA_BHRB_DISABLE;
> + }
> +
> + mtspr(SPRN_MMCR0, mmcr0);
> + mtspr(SPRN_MMCRA, mmcra);
> + isync();
> +}
> +
> +void switch_pmu_to_guest(struct kvm_vcpu *vcpu,
> + struct p9_host_os_sprs *host_os_sprs)
> +{
> + struct lppaca *lp;
> + int load_pmu = 1;
> +
> + lp = vcpu->arch.vpa.pinned_addr;
> + if (lp)
> + load_pmu = lp->pmcregs_in_use;
> +
> + if (load_pmu)
> + vcpu->arch.hfscr |= HFSCR_PM;
> +
> + /* Save host */
> + if (ppc_get_pmu_inuse()) {
> + /*
> + * It might be better to put PMU handling (at least for the
> + * host) in the perf subsystem because it knows more about what
> + * is being used.
> + */
> +
> + /* POWER9, POWER10 do not implement HPMC or SPMC */
> +
> + host_os_sprs->mmcr0 = mfspr(SPRN_MMCR0);
> + host_os_sprs->mmcra = mfspr(SPRN_MMCRA);
> +
> + freeze_pmu(host_os_sprs->mmcr0, host_os_sprs->mmcra);
> +
> + host_os_sprs->pmc1 = mfspr(SPRN_PMC1);
> + host_os_sprs->pmc2 = mfspr(SPRN_PMC2);
> + host_os_sprs->pmc3 = mfspr(SPRN_PMC3);
> + host_os_sprs->pmc4 = mfspr(SPRN_PMC4);
> + host_os_sprs->pmc5 = mfspr(SPRN_PMC5);
> + host_os_sprs->pmc6 = mfspr(SPRN_PMC6);
> + host_os_sprs->mmcr1 = mfspr(SPRN_MMCR1);
> + host_os_sprs->mmcr2 = mfspr(SPRN_MMCR2);
> + host_os_sprs->sdar = mfspr(SPRN_SDAR);
> + host_os_sprs->siar = mfspr(SPRN_SIAR);
> + host_os_sprs->sier1 = mfspr(SPRN_SIER);
> +
> + if (cpu_has_feature(CPU_FTR_ARCH_31)) {
> + host_os_sprs->mmcr3 = mfspr(SPRN_MMCR3);
> + host_os_sprs->sier2 = mfspr(SPRN_SIER2);
> + host_os_sprs->sier3 = mfspr(SPRN_SIER3);
> + }
> + }
> +
> +#ifdef CONFIG_PPC_PSERIES
> + if (kvmhv_on_pseries()) {
> + if (vcpu->arch.vpa.pinned_addr) {
> + struct lppaca *lp = vcpu->arch.vpa.pinned_addr;
> + get_lppaca()->pmcregs_in_use = lp->pmcregs_in_use;
> + } else {
> + get_lppaca()->pmcregs_in_use = 1;
> + }
> + }
> +#endif
> +
> + /* Load guest */
> + if (vcpu->arch.hfscr & HFSCR_PM) {
> + mtspr(SPRN_PMC1, vcpu->arch.pmc[0]);
> + mtspr(SPRN_PMC2, vcpu->arch.pmc[1]);
> + mtspr(SPRN_PMC3, vcpu->arch.pmc[2]);
> + mtspr(SPRN_PMC4, vcpu->arch.pmc[3]);
> + mtspr(SPRN_PMC5, vcpu->arch.pmc[4]);
> + mtspr(SPRN_PMC6, vcpu->arch.pmc[5]);
> + mtspr(SPRN_MMCR1, vcpu->arch.mmcr[1]);
> + mtspr(SPRN_MMCR2, vcpu->arch.mmcr[2]);
> + mtspr(SPRN_SDAR, vcpu->arch.sdar);
> + mtspr(SPRN_SIAR, vcpu->arch.siar);
> + mtspr(SPRN_SIER, vcpu->arch.sier[0]);
> +
> + if (cpu_has_feature(CPU_FTR_ARCH_31)) {
> + mtspr(SPRN_MMCR3, vcpu->arch.mmcr[4]);
> + mtspr(SPRN_SIER2, vcpu->arch.sier[1]);
> + mtspr(SPRN_SIER3, vcpu->arch.sier[2]);
> + }
> +
> + /* Set MMCRA then MMCR0 last */
> + mtspr(SPRN_MMCRA, vcpu->arch.mmcra);
> + mtspr(SPRN_MMCR0, vcpu->arch.mmcr[0]);
> + /* No isync necessary because we're starting counters */
> + }
> +}
> +EXPORT_SYMBOL_GPL(switch_pmu_to_guest);
> +
> +void switch_pmu_to_host(struct kvm_vcpu *vcpu,
> + struct p9_host_os_sprs *host_os_sprs)
> +{
> + struct lppaca *lp;
> + int save_pmu = 1;
> +
> + lp = vcpu->arch.vpa.pinned_addr;
> + if (lp)
> + save_pmu = lp->pmcregs_in_use;
> +
> + if (save_pmu) {
> + vcpu->arch.mmcr[0] = mfspr(SPRN_MMCR0);
> + vcpu->arch.mmcra = mfspr(SPRN_MMCRA);
> +
> + freeze_pmu(vcpu->arch.mmcr[0], vcpu->arch.mmcra);
> +
> + vcpu->arch.pmc[0] = mfspr(SPRN_PMC1);
> + vcpu->arch.pmc[1] = mfspr(SPRN_PMC2);
> + vcpu->arch.pmc[2] = mfspr(SPRN_PMC3);
> + vcpu->arch.pmc[3] = mfspr(SPRN_PMC4);
> + vcpu->arch.pmc[4] = mfspr(SPRN_PMC5);
> + vcpu->arch.pmc[5] = mfspr(SPRN_PMC6);
> + vcpu->arch.mmcr[1] = mfspr(SPRN_MMCR1);
> + vcpu->arch.mmcr[2] = mfspr(SPRN_MMCR2);
> + vcpu->arch.sdar = mfspr(SPRN_SDAR);
> + vcpu->arch.siar = mfspr(SPRN_SIAR);
> + vcpu->arch.sier[0] = mfspr(SPRN_SIER);
> +
> + if (cpu_has_feature(CPU_FTR_ARCH_31)) {
> + vcpu->arch.mmcr[3] = mfspr(SPRN_MMCR3);
> + vcpu->arch.sier[1] = mfspr(SPRN_SIER2);
> + vcpu->arch.sier[2] = mfspr(SPRN_SIER3);
> + }
> +
> + } else if (vcpu->arch.hfscr & HFSCR_PM) {
> + /*
> + * The guest accessed PMC SPRs without specifying they should
> + * be preserved. Stop them from counting if the guest had
> + * started anything.
> + */
> + freeze_pmu(mfspr(SPRN_MMCR0), mfspr(SPRN_MMCRA));
> +
> + /*
> + * Demand-fault PMU register access in the guest.
> + *
> + * This is used to grab the guest's VPA pmcregs_in_use value
> + * and reflect it into the host's VPA in the case of a nested
> + * hypervisor.
> + *
> + * It also avoids having to zero-out SPRs after each guest
> + * exit to avoid side-channels when.
> + *
> + * This is cleared here when we exit the guest, so later HFSCR
> + * interrupt handling can add it back to run the guest with
> + * PM enabled next time.
> + */
> + vcpu->arch.hfscr &= ~HFSCR_PM;
> + } /* otherwise the PMU should still be frozen from guest entry */
> +
> +
> +#ifdef CONFIG_PPC_PSERIES
> + if (kvmhv_on_pseries())
> + get_lppaca()->pmcregs_in_use = ppc_get_pmu_inuse();
> +#endif
> +
> + if (ppc_get_pmu_inuse()) {
> + mtspr(SPRN_PMC1, host_os_sprs->pmc1);
> + mtspr(SPRN_PMC2, host_os_sprs->pmc2);
> + mtspr(SPRN_PMC3, host_os_sprs->pmc3);
> + mtspr(SPRN_PMC4, host_os_sprs->pmc4);
> + mtspr(SPRN_PMC5, host_os_sprs->pmc5);
> + mtspr(SPRN_PMC6, host_os_sprs->pmc6);
> + mtspr(SPRN_MMCR1, host_os_sprs->mmcr1);
> + mtspr(SPRN_MMCR2, host_os_sprs->mmcr2);
> + mtspr(SPRN_SDAR, host_os_sprs->sdar);
> + mtspr(SPRN_SIAR, host_os_sprs->siar);
> + mtspr(SPRN_SIER, host_os_sprs->sier1);
> +
> + if (cpu_has_feature(CPU_FTR_ARCH_31)) {
> + mtspr(SPRN_MMCR3, host_os_sprs->mmcr3);
> + mtspr(SPRN_SIER2, host_os_sprs->sier2);
> + mtspr(SPRN_SIER3, host_os_sprs->sier3);
> + }
> +
> + /* Set MMCRA then MMCR0 last */
> + mtspr(SPRN_MMCRA, host_os_sprs->mmcra);
> + mtspr(SPRN_MMCR0, host_os_sprs->mmcr0);
> + isync();
> + }
> +}
> +EXPORT_SYMBOL_GPL(switch_pmu_to_host);
> +
> +static void load_spr_state(struct kvm_vcpu *vcpu,
> + struct p9_host_os_sprs *host_os_sprs)
> +{
> + mtspr(SPRN_TAR, vcpu->arch.tar);
> + mtspr(SPRN_EBBHR, vcpu->arch.ebbhr);
> + mtspr(SPRN_EBBRR, vcpu->arch.ebbrr);
> + mtspr(SPRN_BESCR, vcpu->arch.bescr);
> +
> + if (!cpu_has_feature(CPU_FTR_ARCH_31))
> + mtspr(SPRN_TIDR, vcpu->arch.tid);
> + if (host_os_sprs->iamr != vcpu->arch.iamr)
> + mtspr(SPRN_IAMR, vcpu->arch.iamr);
> + if (host_os_sprs->amr != vcpu->arch.amr)
> + mtspr(SPRN_AMR, vcpu->arch.amr);
> + if (vcpu->arch.uamor != 0)
> + mtspr(SPRN_UAMOR, vcpu->arch.uamor);
> + if (host_os_sprs->fscr != vcpu->arch.fscr)
> + mtspr(SPRN_FSCR, vcpu->arch.fscr);
> + if (host_os_sprs->dscr != vcpu->arch.dscr)
> + mtspr(SPRN_DSCR, vcpu->arch.dscr);
> + if (vcpu->arch.pspb != 0)
> + mtspr(SPRN_PSPB, vcpu->arch.pspb);
> +
> + /*
> + * DAR, DSISR, and for nested HV, SPRGs must be set with MSR[RI]
> + * clear (or hstate set appropriately to catch those registers
> + * being clobbered if we take a MCE or SRESET), so those are done
> + * later.
> + */
> +
> + if (!(vcpu->arch.ctrl & 1))
> + mtspr(SPRN_CTRLT, 0);
> +}
> +
> +static void store_spr_state(struct kvm_vcpu *vcpu)
> +{
> + vcpu->arch.tar = mfspr(SPRN_TAR);
> + vcpu->arch.ebbhr = mfspr(SPRN_EBBHR);
> + vcpu->arch.ebbrr = mfspr(SPRN_EBBRR);
> + vcpu->arch.bescr = mfspr(SPRN_BESCR);
> +
> + if (!cpu_has_feature(CPU_FTR_ARCH_31))
> + vcpu->arch.tid = mfspr(SPRN_TIDR);
> + vcpu->arch.iamr = mfspr(SPRN_IAMR);
> + vcpu->arch.amr = mfspr(SPRN_AMR);
> + vcpu->arch.uamor = mfspr(SPRN_UAMOR);
> + vcpu->arch.fscr = mfspr(SPRN_FSCR);
> + vcpu->arch.dscr = mfspr(SPRN_DSCR);
> + vcpu->arch.pspb = mfspr(SPRN_PSPB);
> +
> + vcpu->arch.ctrl = mfspr(SPRN_CTRLF);
> +}
> +
> +void load_vcpu_state(struct kvm_vcpu *vcpu,
> + struct p9_host_os_sprs *host_os_sprs)
> +{
> + if (cpu_has_feature(CPU_FTR_TM) ||
> + cpu_has_feature(CPU_FTR_P9_TM_HV_ASSIST))
> + kvmppc_restore_tm_hv(vcpu, vcpu->arch.shregs.msr, true);
> +
> + load_spr_state(vcpu, host_os_sprs);
> +
> + load_fp_state(&vcpu->arch.fp);
> +#ifdef CONFIG_ALTIVEC
> + load_vr_state(&vcpu->arch.vr);
> +#endif
> + mtspr(SPRN_VRSAVE, vcpu->arch.vrsave);
> +}
> +EXPORT_SYMBOL_GPL(load_vcpu_state);
> +
> +void store_vcpu_state(struct kvm_vcpu *vcpu)
> +{
> + store_spr_state(vcpu);
> +
> + store_fp_state(&vcpu->arch.fp);
> +#ifdef CONFIG_ALTIVEC
> + store_vr_state(&vcpu->arch.vr);
> +#endif
> + vcpu->arch.vrsave = mfspr(SPRN_VRSAVE);
> +
> + if (cpu_has_feature(CPU_FTR_TM) ||
> + cpu_has_feature(CPU_FTR_P9_TM_HV_ASSIST))
> + kvmppc_save_tm_hv(vcpu, vcpu->arch.shregs.msr, true);
> +}
> +EXPORT_SYMBOL_GPL(store_vcpu_state);
> +
> +void save_p9_host_os_sprs(struct p9_host_os_sprs *host_os_sprs)
> +{
> + if (!cpu_has_feature(CPU_FTR_ARCH_31))
> + host_os_sprs->tidr = mfspr(SPRN_TIDR);
> + host_os_sprs->iamr = mfspr(SPRN_IAMR);
> + host_os_sprs->amr = mfspr(SPRN_AMR);
> + host_os_sprs->fscr = mfspr(SPRN_FSCR);
> + host_os_sprs->dscr = mfspr(SPRN_DSCR);
> +}
> +EXPORT_SYMBOL_GPL(save_p9_host_os_sprs);
> +
> +/* vcpu guest regs must already be saved */
> +void restore_p9_host_os_sprs(struct kvm_vcpu *vcpu,
> + struct p9_host_os_sprs *host_os_sprs)
> +{
> + mtspr(SPRN_SPRG_VDSO_WRITE, local_paca->sprg_vdso);
> +
> + if (!cpu_has_feature(CPU_FTR_ARCH_31))
> + mtspr(SPRN_TIDR, host_os_sprs->tidr);
> + if (host_os_sprs->iamr != vcpu->arch.iamr)
> + mtspr(SPRN_IAMR, host_os_sprs->iamr);
> + if (vcpu->arch.uamor != 0)
> + mtspr(SPRN_UAMOR, 0);
> + if (host_os_sprs->amr != vcpu->arch.amr)
> + mtspr(SPRN_AMR, host_os_sprs->amr);
> + if (host_os_sprs->fscr != vcpu->arch.fscr)
> + mtspr(SPRN_FSCR, host_os_sprs->fscr);
> + if (host_os_sprs->dscr != vcpu->arch.dscr)
> + mtspr(SPRN_DSCR, host_os_sprs->dscr);
> + if (vcpu->arch.pspb != 0)
> + mtspr(SPRN_PSPB, 0);
> +
> + /* Save guest CTRL register, set runlatch to 1 */
> + if (!(vcpu->arch.ctrl & 1))
> + mtspr(SPRN_CTRLT, 1);
> +}
> +EXPORT_SYMBOL_GPL(restore_p9_host_os_sprs);
> +
> #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
> static void __start_timing(struct kvm_vcpu *vcpu, struct kvmhv_tb_accumulator *next)
> {
> --
> 2.23.0
>
^ permalink raw reply
* [RFC PATCH v0 1/1] powerpc/percpu: Use 2MB atom_size in percpu allocator on radix
From: Bharata B Rao @ 2021-07-08 5:29 UTC (permalink / raw)
To: linuxppc-dev; +Cc: aneesh.kumar, Bharata B Rao, npiggin
The atom_size used by percpu allocator on powerpc is currently
determined by mmu_linear_psize which is initialized to 4K and
mmu_linear_psize is modified only by hash. Till now for radix
the atom_size was defaulting to PAGE_SIZE(64K). Go for 2MB
atom_size on radix if support for 2MB pages exist.
2MB atom_size on radix will allow using PMD mappings in the
vmalloc area if and when support for higher sized vmalloc
mappings is enabled for the pecpu allocator. However right now
this change will result in more number of units to be allocated
within one allocation due to increased upa(units per allocation).
Signed-off-by: Bharata B Rao <bharata@linux.ibm.com>
---
arch/powerpc/kernel/setup_64.c | 34 +++++++++++++++++++++++++---------
1 file changed, 25 insertions(+), 9 deletions(-)
diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
index 1ff258f6c76c..45ce2d6e8112 100644
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -871,6 +871,30 @@ static void __init pcpu_populate_pte(unsigned long addr)
__func__, PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
}
+static size_t pcpu_atom_size(void)
+{
+ size_t atom_size = PAGE_SIZE;
+
+ /*
+ * Radix: Use PAGE_SIZE by default or 2M if available.
+ */
+ if (radix_enabled()) {
+ if (mmu_psize_defs[MMU_PAGE_2M].shift)
+ atom_size = 1 << mmu_psize_defs[MMU_PAGE_2M].shift;
+ goto out;
+ }
+
+ /*
+ * Hash: Linear mapping is one of 4K, 1M and 16M. For 4K, no need
+ * to group units. For larger mappings, use 1M atom which
+ * should be large enough to contain a number of units.
+ */
+ if (mmu_linear_psize != MMU_PAGE_4K)
+ atom_size = 1 << 20;
+
+out:
+ return atom_size;
+}
void __init setup_per_cpu_areas(void)
{
@@ -880,15 +904,7 @@ void __init setup_per_cpu_areas(void)
unsigned int cpu;
int rc = -EINVAL;
- /*
- * Linear mapping is one of 4K, 1M and 16M. For 4K, no need
- * to group units. For larger mappings, use 1M atom which
- * should be large enough to contain a number of units.
- */
- if (mmu_linear_psize == MMU_PAGE_4K)
- atom_size = PAGE_SIZE;
- else
- atom_size = 1 << 20;
+ atom_size = pcpu_atom_size();
if (pcpu_chosen_fc != PCPU_FC_PAGE) {
rc = pcpu_embed_first_chunk(0, dyn_size, atom_size, pcpu_cpu_distance,
--
2.31.1
^ permalink raw reply related
* Re: [PATCH v8 3/6] KVM: PPC: Book3S HV: Add support for H_RPT_INVALIDATE
From: Bharata B Rao @ 2021-07-08 4:29 UTC (permalink / raw)
To: David Gibson; +Cc: farosas, aneesh.kumar, npiggin, kvm-ppc, linuxppc-dev
In-Reply-To: <YOZ3zNsGbSoymVKI@yekko>
On Thu, Jul 08, 2021 at 01:58:04PM +1000, David Gibson wrote:
> On Tue, Jul 06, 2021 at 10:56:32AM +0530, Bharata B Rao wrote:
> > On Mon, Jul 05, 2021 at 02:42:33PM +1000, David Gibson wrote:
> > > On Mon, Jun 21, 2021 at 02:20:00PM +0530, Bharata B Rao wrote:
> > > > diff --git a/arch/powerpc/include/asm/mmu_context.h b/arch/powerpc/include/asm/mmu_context.h
> > > > index 4bc45d3ed8b0..b44f291fc909 100644
> > > > --- a/arch/powerpc/include/asm/mmu_context.h
> > > > +++ b/arch/powerpc/include/asm/mmu_context.h
> > > > @@ -124,8 +124,17 @@ static inline bool need_extra_context(struct mm_struct *mm, unsigned long ea)
> > > >
> > > > #if defined(CONFIG_KVM_BOOK3S_HV_POSSIBLE) && defined(CONFIG_PPC_RADIX_MMU)
> > > > extern void radix_kvm_prefetch_workaround(struct mm_struct *mm);
> > > > +void do_h_rpt_invalidate_prt(unsigned long pid, unsigned long lpid,
> > > > + unsigned long type, unsigned long pg_sizes,
> > > > + unsigned long start, unsigned long end);
> > > > #else
> > > > static inline void radix_kvm_prefetch_workaround(struct mm_struct *mm) { }
> > > > +static inline void do_h_rpt_invalidate_prt(unsigned long pid,
> > > > + unsigned long lpid,
> > > > + unsigned long type,
> > > > + unsigned long pg_sizes,
> > > > + unsigned long start,
> > > > + unsigned long end) { }
> > >
> > > Since the only plausible caller is in KVM HV code, why do you need the
> > > #else clause.
> >
> > The call to the above routine is prevented for non-radix guests
> > in KVM HV code at runtime using kvm_is_radix() check and not by
> > CONFIG_PPC_RADIX_MMU. Hence the #else version would be needed.
>
> kvm_is_radix() should evaluate to false at compile time if
> !defined(CONFIG_PPC_RADIX_MMU), in which case, no you shouldn't need
> the else version.
At least in the latest mainline, I don't see the definition of
kvm_is_radix() being conditional to CONFIG_PPC_RADIX_MMU.
Anyway this is what I see in practice if the #else version is
removed and CONFIG_PPC_RADIX_MMU is turned off:
arch/powerpc/kvm/book3s_hv.c: In function ‘kvmppc_h_rpt_invalidate’:
arch/powerpc/kvm/book3s_hv.c:983:2: error: implicit declaration of function ‘do_h_rpt_invalidate_prt’; did you mean ‘do_h_rpt_invalidate_pat’? [-Werror=implicit-function-declaration]
983 | do_h_rpt_invalidate_prt(id, vcpu->kvm->arch.lpid,
| ^~~~~~~~~~~~~~~~~~~~~~~
| do_h_rpt_invalidate_pat
Regards,
Bharata.
^ permalink raw reply
* Re: [PATCH v8 3/6] KVM: PPC: Book3S HV: Add support for H_RPT_INVALIDATE
From: David Gibson @ 2021-07-08 3:58 UTC (permalink / raw)
To: Bharata B Rao; +Cc: farosas, aneesh.kumar, npiggin, kvm-ppc, linuxppc-dev
In-Reply-To: <YOPpiLJlsEBtTmgt@in.ibm.com>
[-- Attachment #1: Type: text/plain, Size: 1920 bytes --]
On Tue, Jul 06, 2021 at 10:56:32AM +0530, Bharata B Rao wrote:
> On Mon, Jul 05, 2021 at 02:42:33PM +1000, David Gibson wrote:
> > On Mon, Jun 21, 2021 at 02:20:00PM +0530, Bharata B Rao wrote:
> > > diff --git a/arch/powerpc/include/asm/mmu_context.h b/arch/powerpc/include/asm/mmu_context.h
> > > index 4bc45d3ed8b0..b44f291fc909 100644
> > > --- a/arch/powerpc/include/asm/mmu_context.h
> > > +++ b/arch/powerpc/include/asm/mmu_context.h
> > > @@ -124,8 +124,17 @@ static inline bool need_extra_context(struct mm_struct *mm, unsigned long ea)
> > >
> > > #if defined(CONFIG_KVM_BOOK3S_HV_POSSIBLE) && defined(CONFIG_PPC_RADIX_MMU)
> > > extern void radix_kvm_prefetch_workaround(struct mm_struct *mm);
> > > +void do_h_rpt_invalidate_prt(unsigned long pid, unsigned long lpid,
> > > + unsigned long type, unsigned long pg_sizes,
> > > + unsigned long start, unsigned long end);
> > > #else
> > > static inline void radix_kvm_prefetch_workaround(struct mm_struct *mm) { }
> > > +static inline void do_h_rpt_invalidate_prt(unsigned long pid,
> > > + unsigned long lpid,
> > > + unsigned long type,
> > > + unsigned long pg_sizes,
> > > + unsigned long start,
> > > + unsigned long end) { }
> >
> > Since the only plausible caller is in KVM HV code, why do you need the
> > #else clause.
>
> The call to the above routine is prevented for non-radix guests
> in KVM HV code at runtime using kvm_is_radix() check and not by
> CONFIG_PPC_RADIX_MMU. Hence the #else version would be needed.
kvm_is_radix() should evaluate to false at compile time if
!defined(CONFIG_PPC_RADIX_MMU), in which case, no you shouldn't need
the else version.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply
* Re: [PATCH v2 0/4] bus: Make remove callback return void
From: Sven Van Asbroeck @ 2021-07-08 2:08 UTC (permalink / raw)
To: Uwe Kleine-König
Cc: nvdimm, Alexey Kardashevskiy, Samuel Iglesias Gonsalvez,
Jens Taprogge, Ulf Hansson, Jaroslav Kysela, linux-fpga,
Benjamin Tissoires, Paul Mackerras, Srinivas Pandruvada,
K. Y. Srinivasan, Mike Christie, Wei Liu, Maxim Levitsky,
Samuel Holland, linux-acpi, linux-pci, xen-devel, Tomas Winkler,
Julien Grall, Ohad Ben-Cohen, Alex Williamson, Alex Elder,
linux-parisc, Geoff Levand, Greg Kroah-Hartman, linux-usb,
Rafael J. Wysocki, Linux Kernel Mailing List, linux-spi,
Thorsten Scherer, Sascha Hauer, Jon Mason, linux-ntb, Wu Hao,
David Woodhouse, Krzysztof Wilczyński, Alexandre Belloni,
Manohar Vanga, linux-wireless, Dominik Brodowski, virtualization,
James E.J. Bottomley, target-devel, Srinivas Kandagatla,
linux-i2c, Kai-Heng Feng, Stefano Stabellini, Stephen Hemminger,
Ira Weiny, Helge Deller, Rafał Miłecki,
industrypack-devel, linux-mips, Len Brown, alsa-devel,
linux-arm-msm, linux-media, Maxime Ripard, Johan Hovold,
greybus-dev, Bjorn Helgaas, Dave Jiang, Boris Ostrovsky,
Mika Westerberg,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
Johannes Thumshirn, Mathieu Poirier, Stephen Boyd, Cornelia Huck,
Wolfram Sang, Joey Pabalan, Yehezkel Bernat, Pali Rohár,
Bodo Stroesser, Alison Schofield, Heikki Krogerus, Tyrel Datwyler,
Alexander Shishkin, Tom Rix, Jason Wang, SeongJae Park,
linux-hyperv, platform-driver-x86, Frank Li, netdev,
Qinglang Miao, Jiri Slaby, Rob Herring, Lorenzo Pieralisi,
Mark Gross, linux-staging, Dexuan Cui, Jernej Skrabec,
Kishon Vijay Abraham I, Chen-Yu Tsai, linux-input, Allen Hubbe,
Alex Dubov, Haiyang Zhang, Jiri Kosina, Vladimir Zapolskiy,
Ben Widawsky, Moritz Fischer, linux-cxl, Michael Buesch,
Dan Williams, Mauro Carvalho Chehab, Cristian Marussi,
Thomas Bogendoerfer, Martin K. Petersen, Martyn Welch,
Dmitry Torokhov, linux-mmc, linux-sunxi, Stefan Richter,
Sudeep Holla, David S. Miller, kvm, Michael S. Tsirkin,
linux-remoteproc, Bjorn Andersson, Kirti Wankhede, Andreas Noever,
linux-i3c, linux1394-devel, Lee Jones, Arnd Bergmann, linux-scsi,
Vishal Verma, Russell King, Andy Gross, linux-serial,
Jakub Kicinski, Michael Jamet, William Breathitt Gray,
Hans de Goede, Hannes Reinecke, Adrian Hunter, Juergen Gross,
linuxppc-dev, Takashi Iwai, Alexandre Bounine, Vinod Koul,
Mark Brown, Marc Zyngier, dmaengine, Johannes Berg,
Maximilian Luz
In-Reply-To: <20210706154803.1631813-1-u.kleine-koenig@pengutronix.de>
On Tue, Jul 6, 2021 at 11:50 AM Uwe Kleine-König
<u.kleine-koenig@pengutronix.de> wrote:
>
> drivers/staging/fieldbus/anybuss/host.c | 4 +---
Awesome !
Acked-by: Sven Van Asbroeck <TheSven73@gmail.com>
^ permalink raw reply
* Re: [PATCH kernel] KVM: PPC: Book3S HV: Make unique debugfs nodename
From: Alexey Kardashevskiy @ 2021-07-08 2:22 UTC (permalink / raw)
To: Fabiano Rosas, linuxppc-dev; +Cc: linux-kernel, kvm-ppc
In-Reply-To: <87zguynhfo.fsf@linux.ibm.com>
On 08/07/2021 03:48, Fabiano Rosas wrote:
> Alexey Kardashevskiy <aik@ozlabs.ru> writes:
>
>> Currently it is vm-$currentpid which works as long as there is just one
>> VM per the userspace (99.99% cases) but produces a bunch
>> of "debugfs: Directory 'vm16679' with parent 'kvm' already present!"
>> when syzkaller (syscall fuzzer) is running so only one VM is present in
>> the debugfs for a given process.
>>
>> This changes the debugfs node to include the LPID which alone should be
>> system wide unique. This leaves the existing pid for the convenience of
>> matching the VM's debugfs with the running userspace process (QEMU).
>>
>> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
>
> Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
thanks.
Strangely it also fixes a bunch of
BUG: unable to handle kernel NULL pointer dereference in corrupted
BUG: unable to handle kernel paging request in corrupted
I was having 3 of these for every hour of running syzkaller and not
anymore with this patch.
>
>> ---
>> arch/powerpc/kvm/book3s_hv.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
>> index 1d1fcc290fca..0223ddc0eed0 100644
>> --- a/arch/powerpc/kvm/book3s_hv.c
>> +++ b/arch/powerpc/kvm/book3s_hv.c
>> @@ -5227,7 +5227,7 @@ static int kvmppc_core_init_vm_hv(struct kvm *kvm)
>> /*
>> * Create a debugfs directory for the VM
>> */
>> - snprintf(buf, sizeof(buf), "vm%d", current->pid);
>> + snprintf(buf, sizeof(buf), "vm%d-lp%ld", current->pid, lpid);
>> kvm->arch.debugfs_dir = debugfs_create_dir(buf, kvm_debugfs_dir);
>> kvmppc_mmu_debugfs_init(kvm);
>> if (radix_enabled())
--
Alexey
^ permalink raw reply
* Re: [PATCH v2 4/4] bus: Make remove callback return void
From: Thorsten Scherer @ 2021-07-07 21:51 UTC (permalink / raw)
To: Uwe Kleine-König
Cc: nvdimm, Alexey Kardashevskiy, Samuel Iglesias Gonsalvez,
Jens Taprogge, Ulf Hansson, Jaroslav Kysela, linux-fpga,
Benjamin Tissoires, Paul Mackerras, Srinivas Pandruvada,
K. Y. Srinivasan, Mike Christie, Wei Liu, Maxim Levitsky,
Samuel Holland, linux-acpi, linux-pci, xen-devel, Tomas Winkler,
Julien Grall, Ohad Ben-Cohen, Alex Williamson, Alex Elder,
linux-parisc, Geoff Levand, Greg Kroah-Hartman, linux-usb,
Rafael J. Wysocki, linux-kernel, linux-spi, Kai-Heng Feng, kernel,
Jon Mason, linux-ntb, Wu Hao, David Woodhouse,
Krzysztof Wilczyński, Alexandre Belloni, Manohar Vanga,
linux-wireless, Dominik Brodowski, virtualization,
James E.J. Bottomley, target-devel, Srinivas Kandagatla,
linux-i2c, Stefano Stabellini, Stephen Hemminger, Ira Weiny,
Helge Deller, Rafał Miłecki, industrypack-devel,
linux-mips, Len Brown, alsa-devel, linux-arm-msm, linux-media,
Maxime Ripard, Johan Hovold, greybus-dev, Bjorn Helgaas,
Dave Jiang, Boris Ostrovsky, Mika Westerberg, linux-arm-kernel,
Johannes Thumshirn, Mathieu Poirier, Stephen Boyd, Cornelia Huck,
Wolfram Sang, Joey Pabalan, Yehezkel Bernat, Pali Rohár,
Bodo Stroesser, Alison Schofield, Heikki Krogerus, Tyrel Datwyler,
Alexander Shishkin, Tom Rix, Jason Wang, SeongJae Park,
linux-hyperv, platform-driver-x86, Frank Li, netdev,
Qinglang Miao, Jiri Slaby, Rob Herring, Lorenzo Pieralisi,
Mark Gross, linux-staging, Dexuan Cui, Jernej Skrabec,
Kishon Vijay Abraham I, Chen-Yu Tsai, linux-input, Allen Hubbe,
Alex Dubov, Haiyang Zhang, Jiri Kosina, Vladimir Zapolskiy,
Russell King, Ben Widawsky, Moritz Fischer, linux-cxl,
Michael Buesch, Dan Williams, Mauro Carvalho Chehab,
Cristian Marussi, Thomas Bogendoerfer, Martin K. Petersen,
Martyn Welch, Dmitry Torokhov, linux-mmc, linux-sunxi,
Stefan Richter, Sudeep Holla, David S. Miller, Sven Van Asbroeck,
kvm, Michael S. Tsirkin, linux-remoteproc, Bjorn Andersson,
Kirti Wankhede, Andreas Noever, linux-i3c, linux1394-devel,
Lee Jones, Arnd Bergmann, linux-scsi, Vishal Verma, Russell King,
Andy Gross, linux-serial, Jakub Kicinski, Michael Jamet,
William Breathitt Gray, Hans de Goede, Hannes Reinecke,
Adrian Hunter, Juergen Gross, linuxppc-dev, Takashi Iwai,
Alexandre Bounine, Vinod Koul, Mark Brown, Marc Zyngier,
dmaengine, Johannes Berg, Johannes Thumshirn, Maximilian Luz
In-Reply-To: <20210706154803.1631813-5-u.kleine-koenig@pengutronix.de>
On Tue, Jul 06, 2021 at 05:48:03PM +0200, Uwe Kleine-König wrote:
> The driver core ignores the return value of this callback because there
> is only little it can do when a device disappears.
>
> This is the final bit of a long lasting cleanup quest where several
> buses were converted to also return void from their remove callback.
> Additionally some resource leaks were fixed that were caused by drivers
> returning an error code in the expectation that the driver won't go
> away.
>
> With struct bus_type::remove returning void it's prevented that newly
> implemented buses return an ignored error code and so don't anticipate
> wrong expectations for driver authors.
[...]
> drivers/siox/siox-core.c | 4 +---
(For drivers/siox)
Acked-by: Thorsten Scherer <t.scherer@eckelmann.de>
Best regards
Thorsten
--
Thorsten Scherer | Eckelmann AG | www.eckelmann.de |
^ permalink raw reply
* Re: [PATCH v2 4/4] bus: Make remove callback return void
From: Benjamin Tissoires @ 2021-07-07 14:24 UTC (permalink / raw)
To: Uwe Kleine-König, Greg Kroah-Hartman
Cc: nvdimm, Alexey Kardashevskiy, Samuel Iglesias Gonsalvez,
Jens Taprogge, Ulf Hansson, Jaroslav Kysela, Thorsten Scherer,
Paul Mackerras, Srinivas Pandruvada, K. Y. Srinivasan,
Mike Christie, Wei Liu, Maxim Levitsky, Samuel Holland,
linux-acpi, linux-pci, xen-devel, Tomas Winkler, Julien Grall,
Ohad Ben-Cohen, Alex Williamson, Alex Elder, linux-parisc,
Geoff Levand, linux-fpga, linux-usb, Rafael J. Wysocki,
linux-kernel, linux-spi, Kai-Heng Feng, kernel, Jon Mason,
linux-ntb, Wu Hao, David Woodhouse, Krzysztof Wilczyński,
Alexandre Belloni, Manohar Vanga, linux-wireless,
Dominik Brodowski, virtualization, James E.J. Bottomley,
target-devel, Srinivas Kandagatla, linux-i2c, Stefano Stabellini,
Stephen Hemminger, Ira Weiny, Helge Deller,
Rafał Miłecki, industrypack-devel, linux-mips,
Len Brown, alsa-devel, linux-arm-msm, linux-media, Maxime Ripard,
Johan Hovold, greybus-dev, Bjorn Helgaas, Dave Jiang,
Boris Ostrovsky, Mika Westerberg, linux-arm-kernel,
Johannes Thumshirn, Mathieu Poirier, Stephen Boyd, Cornelia Huck,
Wolfram Sang, Joey Pabalan, Yehezkel Bernat, Pali Rohár,
Bodo Stroesser, Alison Schofield, Heikki Krogerus, Tyrel Datwyler,
Alexander Shishkin, Tom Rix, Jason Wang, SeongJae Park,
linux-hyperv, platform-driver-x86, Frank Li, netdev,
Qinglang Miao, Jiri Slaby, Rob Herring, Lorenzo Pieralisi,
Mark Gross, linux-staging, Dexuan Cui, Jernej Skrabec,
Kishon Vijay Abraham I, Chen-Yu Tsai, linux-input, Allen Hubbe,
Alex Dubov, Haiyang Zhang, Jiri Kosina, Vladimir Zapolskiy,
Russell King, Ben Widawsky, Moritz Fischer, linux-cxl,
Michael Buesch, Dan Williams, Mauro Carvalho Chehab,
Cristian Marussi, Thomas Bogendoerfer, Martin K. Petersen,
Martyn Welch, Dmitry Torokhov, linux-mmc, linux-sunxi,
Stefan Richter, Sudeep Holla, David S. Miller, Sven Van Asbroeck,
kvm, Michael S. Tsirkin, linux-remoteproc, Bjorn Andersson,
Kirti Wankhede, Andreas Noever, linux-i3c, linux1394-devel,
Lee Jones, Arnd Bergmann, linux-scsi, Vishal Verma, Russell King,
Andy Gross, linux-serial, Jakub Kicinski, Michael Jamet,
William Breathitt Gray, Hans de Goede, Hannes Reinecke,
Adrian Hunter, Juergen Gross, linuxppc-dev, Takashi Iwai,
Alexandre Bounine, Vinod Koul, Mark Brown, Marc Zyngier,
dmaengine, Johannes Berg, Johannes Thumshirn, Maximilian Luz
In-Reply-To: <20210706154803.1631813-5-u.kleine-koenig@pengutronix.de>
On 7/6/21 5:48 PM, Uwe Kleine-König wrote:
> The driver core ignores the return value of this callback because there
> is only little it can do when a device disappears.
>
> This is the final bit of a long lasting cleanup quest where several
> buses were converted to also return void from their remove callback.
> Additionally some resource leaks were fixed that were caused by drivers
> returning an error code in the expectation that the driver won't go
> away.
>
> With struct bus_type::remove returning void it's prevented that newly
> implemented buses return an ignored error code and so don't anticipate
> wrong expectations for driver authors.
>
> Acked-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> (For ARM, Amba and related parts)
> Acked-by: Mark Brown <broonie@kernel.org>
> Acked-by: Chen-Yu Tsai <wens@csie.org> (for drivers/bus/sunxi-rsb.c)
> Acked-by: Pali Rohár <pali@kernel.org>
> Acked-by: Mauro Carvalho Chehab <mchehab@kernel.org> (for drivers/media)
> Acked-by: Hans de Goede <hdegoede@redhat.com> (For drivers/platform)
> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
> Acked-By: Vinod Koul <vkoul@kernel.org>
> Acked-by: Juergen Gross <jgross@suse.com> (For Xen)
> Acked-by: Lee Jones <lee.jones@linaro.org> (For drivers/mfd)
> Acked-by: Johannes Thumshirn <jth@kernel.org> (For drivers/mcb)
> Acked-by: Johan Hovold <johan@kernel.org>
> Acked-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> (For drivers/slimbus)
> Acked-by: Kirti Wankhede <kwankhede@nvidia.com> (For drivers/vfio)
> Acked-by: Maximilian Luz <luzmaximilian@gmail.com>
> Acked-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> (For ulpi and typec)
> Acked-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com> (For ipack)
> Reviewed-by: Tom Rix <trix@redhat.com> (For fpga)
> Acked-by: Geoff Levand <geoff@infradead.org> (For ps3)
> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
> ---
>
[...]
> drivers/hid/hid-core.c | 4 +---
> drivers/hid/intel-ish-hid/ishtp/bus.c | 4 +---
[...]
> diff --git a/drivers/hid/hid-core.c b/drivers/hid/hid-core.c
> index 7db332139f7d..dbed2524fd47 100644
> --- a/drivers/hid/hid-core.c
> +++ b/drivers/hid/hid-core.c
> @@ -2302,7 +2302,7 @@ static int hid_device_probe(struct device *dev)
> return ret;
> }
>
> -static int hid_device_remove(struct device *dev)
> +static void hid_device_remove(struct device *dev)
> {
> struct hid_device *hdev = to_hid_device(dev);
> struct hid_driver *hdrv;
> @@ -2322,8 +2322,6 @@ static int hid_device_remove(struct device *dev)
>
> if (!hdev->io_started)
> up(&hdev->driver_input_lock);
> -
> - return 0;
> }
>
> static ssize_t modalias_show(struct device *dev, struct device_attribute *a,
> diff --git a/drivers/hid/intel-ish-hid/ishtp/bus.c b/drivers/hid/intel-ish-hid/ishtp/bus.c
> index f0802b047ed8..8a51bd9cd093 100644
> --- a/drivers/hid/intel-ish-hid/ishtp/bus.c
> +++ b/drivers/hid/intel-ish-hid/ishtp/bus.c
> @@ -255,7 +255,7 @@ static int ishtp_cl_bus_match(struct device *dev, struct device_driver *drv)
> *
> * Return: Return value from driver remove() call.
> */
> -static int ishtp_cl_device_remove(struct device *dev)
> +static void ishtp_cl_device_remove(struct device *dev)
> {
> struct ishtp_cl_device *device = to_ishtp_cl_device(dev);
> struct ishtp_cl_driver *driver = to_ishtp_cl_driver(dev->driver);
> @@ -267,8 +267,6 @@ static int ishtp_cl_device_remove(struct device *dev)
>
> if (driver->remove)
> driver->remove(device);
> -
> - return 0;
> }
>
> /**
For the HID part:
Acked-by: Benjamin Tissoires <benjamin.tissoires@redhat.com>
Cheers,
Benjamin
^ permalink raw reply
* Re: [PATCH] powerpc: preempt: Don't touch the idle task's preempt_count during hotplug
From: Guenter Roeck @ 2021-07-07 19:18 UTC (permalink / raw)
To: Valentin Schneider
Cc: Srikar Dronamraju, Arnd Bergmann, Peter Zijlstra, linux-kernel,
Bharata B Rao, Paul Mackerras, linuxppc-dev, Ingo Molnar
On Wed, Jul 07, 2021 at 07:38:31PM +0100, Valentin Schneider wrote:
> Powerpc currently resets a CPU's idle task preempt_count to 0 before said
> task starts executing the secondary startup routine (and becomes an idle
> task proper).
>
> This conflicts with commit
>
> f1a0a376ca0c ("sched/core: Initialize the idle task with preemption disabled")
>
> which initializes all of the idle tasks' preempt_count to PREEMPT_DISABLED
> during smp_init(). Note that this was superfluous before said commit, as
> back then the hotplug machinery would invoke init_idle() via
> idle_thread_get(), which would have already reset the CPU's idle task's
> preempt_count to PREEMPT_ENABLED.
>
> Get rid of this preempt_count write.
>
> Cc: Guenter Roeck <linux@roeck-us.net>
> Fixes: f1a0a376ca0c ("sched/core: Initialize the idle task with preemption disabled")
> Reported-by: Bharata B Rao <bharata@linux.ibm.com>
> Signed-off-by: Valentin Schneider <valentin.schneider@arm.com>
Tested-by: Guenter Roeck <linux@roeck-us.net>
> ---
> arch/powerpc/platforms/cell/smp.c | 3 ---
> arch/powerpc/platforms/pseries/smp.c | 5 +----
> 2 files changed, 1 insertion(+), 7 deletions(-)
>
> diff --git a/arch/powerpc/platforms/cell/smp.c b/arch/powerpc/platforms/cell/smp.c
> index c855a0aeb49c..d7ab868aab54 100644
> --- a/arch/powerpc/platforms/cell/smp.c
> +++ b/arch/powerpc/platforms/cell/smp.c
> @@ -78,9 +78,6 @@ static inline int smp_startup_cpu(unsigned int lcpu)
>
> pcpu = get_hard_smp_processor_id(lcpu);
>
> - /* Fixup atomic count: it exited inside IRQ handler. */
> - task_thread_info(paca_ptrs[lcpu]->__current)->preempt_count = 0;
> -
> /*
> * If the RTAS start-cpu token does not exist then presume the
> * cpu is already spinning.
> diff --git a/arch/powerpc/platforms/pseries/smp.c b/arch/powerpc/platforms/pseries/smp.c
> index 096629f54576..7ebf3382816a 100644
> --- a/arch/powerpc/platforms/pseries/smp.c
> +++ b/arch/powerpc/platforms/pseries/smp.c
> @@ -105,10 +105,7 @@ static inline int smp_startup_cpu(unsigned int lcpu)
> return 1;
> }
>
> - /* Fixup atomic count: it exited inside IRQ handler. */
> - task_thread_info(paca_ptrs[lcpu]->__current)->preempt_count = 0;
> -
> - /*
> + /*
> * If the RTAS start-cpu token does not exist then presume the
> * cpu is already spinning.
> */
> --
> 2.25.1
>
^ permalink raw reply
* [PATCH] powerpc: preempt: Don't touch the idle task's preempt_count during hotplug
From: Valentin Schneider @ 2021-07-07 18:38 UTC (permalink / raw)
To: linux-kernel, linuxppc-dev
Cc: Srikar Dronamraju, Arnd Bergmann, Peter Zijlstra, Bharata B Rao,
Paul Mackerras, Ingo Molnar, Guenter Roeck
Powerpc currently resets a CPU's idle task preempt_count to 0 before said
task starts executing the secondary startup routine (and becomes an idle
task proper).
This conflicts with commit
f1a0a376ca0c ("sched/core: Initialize the idle task with preemption disabled")
which initializes all of the idle tasks' preempt_count to PREEMPT_DISABLED
during smp_init(). Note that this was superfluous before said commit, as
back then the hotplug machinery would invoke init_idle() via
idle_thread_get(), which would have already reset the CPU's idle task's
preempt_count to PREEMPT_ENABLED.
Get rid of this preempt_count write.
Cc: Guenter Roeck <linux@roeck-us.net>
Fixes: f1a0a376ca0c ("sched/core: Initialize the idle task with preemption disabled")
Reported-by: Bharata B Rao <bharata@linux.ibm.com>
Signed-off-by: Valentin Schneider <valentin.schneider@arm.com>
---
arch/powerpc/platforms/cell/smp.c | 3 ---
arch/powerpc/platforms/pseries/smp.c | 5 +----
2 files changed, 1 insertion(+), 7 deletions(-)
diff --git a/arch/powerpc/platforms/cell/smp.c b/arch/powerpc/platforms/cell/smp.c
index c855a0aeb49c..d7ab868aab54 100644
--- a/arch/powerpc/platforms/cell/smp.c
+++ b/arch/powerpc/platforms/cell/smp.c
@@ -78,9 +78,6 @@ static inline int smp_startup_cpu(unsigned int lcpu)
pcpu = get_hard_smp_processor_id(lcpu);
- /* Fixup atomic count: it exited inside IRQ handler. */
- task_thread_info(paca_ptrs[lcpu]->__current)->preempt_count = 0;
-
/*
* If the RTAS start-cpu token does not exist then presume the
* cpu is already spinning.
diff --git a/arch/powerpc/platforms/pseries/smp.c b/arch/powerpc/platforms/pseries/smp.c
index 096629f54576..7ebf3382816a 100644
--- a/arch/powerpc/platforms/pseries/smp.c
+++ b/arch/powerpc/platforms/pseries/smp.c
@@ -105,10 +105,7 @@ static inline int smp_startup_cpu(unsigned int lcpu)
return 1;
}
- /* Fixup atomic count: it exited inside IRQ handler. */
- task_thread_info(paca_ptrs[lcpu]->__current)->preempt_count = 0;
-
- /*
+ /*
* If the RTAS start-cpu token does not exist then presume the
* cpu is already spinning.
*/
--
2.25.1
^ permalink raw reply related
* Re: [PATCH kernel] KVM: PPC: Book3S HV: Make unique debugfs nodename
From: Fabiano Rosas @ 2021-07-07 17:48 UTC (permalink / raw)
To: Alexey Kardashevskiy, linuxppc-dev
Cc: Alexey Kardashevskiy, linux-kernel, kvm-ppc
In-Reply-To: <20210707041344.3803554-1-aik@ozlabs.ru>
Alexey Kardashevskiy <aik@ozlabs.ru> writes:
> Currently it is vm-$currentpid which works as long as there is just one
> VM per the userspace (99.99% cases) but produces a bunch
> of "debugfs: Directory 'vm16679' with parent 'kvm' already present!"
> when syzkaller (syscall fuzzer) is running so only one VM is present in
> the debugfs for a given process.
>
> This changes the debugfs node to include the LPID which alone should be
> system wide unique. This leaves the existing pid for the convenience of
> matching the VM's debugfs with the running userspace process (QEMU).
>
> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
> ---
> arch/powerpc/kvm/book3s_hv.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
> index 1d1fcc290fca..0223ddc0eed0 100644
> --- a/arch/powerpc/kvm/book3s_hv.c
> +++ b/arch/powerpc/kvm/book3s_hv.c
> @@ -5227,7 +5227,7 @@ static int kvmppc_core_init_vm_hv(struct kvm *kvm)
> /*
> * Create a debugfs directory for the VM
> */
> - snprintf(buf, sizeof(buf), "vm%d", current->pid);
> + snprintf(buf, sizeof(buf), "vm%d-lp%ld", current->pid, lpid);
> kvm->arch.debugfs_dir = debugfs_create_dir(buf, kvm_debugfs_dir);
> kvmppc_mmu_debugfs_init(kvm);
> if (radix_enabled())
^ permalink raw reply
* Re: [PATCH] powerpc/xive: Do not skip CPU-less nodes when creating the IPIs
From: Laurent Vivier @ 2021-07-07 17:37 UTC (permalink / raw)
To: Cédric Le Goater, linuxppc-dev
Cc: Geetika Moolchandani, Srikar Dronamraju, stable
In-Reply-To: <20210629131542.743888-1-clg@kaod.org>
On 29/06/2021 15:15, Cédric Le Goater wrote:
> On PowerVM, CPU-less nodes can be populated with hot-plugged CPUs at
> runtime. Today, the IPI is not created for such nodes, and hot-plugged
> CPUs use a bogus IPI, which leads to soft lockups.
>
> We could create the node IPI on demand but it is a bit complex because
> this code would be called under bringup_up() and some IRQ locking is
> being done. The simplest solution is to create the IPIs for all nodes
> at startup.
>
> Fixes: 7dcc37b3eff9 ("powerpc/xive: Map one IPI interrupt per node")
> Cc: stable@vger.kernel.org # v5.13
> Reported-by: Geetika Moolchandani <Geetika.Moolchandani1@ibm.com>
> Cc: Srikar Dronamraju <srikar@linux.vnet.ibm.com>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
>
> This patch breaks old versions of irqbalance (<= v1.4). Possible nodes
> are collected from /sys/devices/system/node/ but CPU-less nodes are
> not listed there. When interrupts are scanned, the link representing
> the node structure is NULL and segfault occurs.
>
> Version 1.7 seems immune.
>
> ---
> arch/powerpc/sysdev/xive/common.c | 4 ----
> 1 file changed, 4 deletions(-)
>
> diff --git a/arch/powerpc/sysdev/xive/common.c b/arch/powerpc/sysdev/xive/common.c
> index f3b16ed48b05..5d2c58dba57e 100644
> --- a/arch/powerpc/sysdev/xive/common.c
> +++ b/arch/powerpc/sysdev/xive/common.c
> @@ -1143,10 +1143,6 @@ static int __init xive_request_ipi(void)
> struct xive_ipi_desc *xid = &xive_ipis[node];
> struct xive_ipi_alloc_info info = { node };
>
> - /* Skip nodes without CPUs */
> - if (cpumask_empty(cpumask_of_node(node)))
> - continue;
> -
> /*
> * Map one IPI interrupt per node for all cpus of that node.
> * Since the HW interrupt number doesn't have any meaning,
Tested-by: Laurent Vivier <lvivier@redhat.com>
^ permalink raw reply
* Re: [PATCH v2] perf vendor events power10: Adds 24x7 nest metric events for power10 platform
From: Arnaldo Carvalho de Melo @ 2021-07-07 14:36 UTC (permalink / raw)
To: Kajol Jain
Cc: ravi.bangoria, atrajeev, rnsastry, linuxppc-dev, linux-kernel,
linux-perf-users, maddy, pc, jolsa
In-Reply-To: <20210628064935.163465-1-kjain@linux.ibm.com>
Em Mon, Jun 28, 2021 at 12:19:35PM +0530, Kajol Jain escreveu:
> Patch adds 24x7 nest metric events for POWER10.
Thanks, applied.
- Arnaldo
> Tested-by: Nageswara R Sastry <rnsastry@linux.ibm.com>
> Signed-off-by: Kajol Jain <kjain@linux.ibm.com>
> ---
> .../arch/powerpc/power10/nest_metrics.json | 424 ++++++++++++++++++
> 1 file changed, 424 insertions(+)
> create mode 100644 tools/perf/pmu-events/arch/powerpc/power10/nest_metrics.json
>
> ---
> Changelog:
> v1 -> v2
> - Removed "BriefDescription" field as its value was same as "MetricName"
> field as suggested by Paul A. Clarke
> - Added Tested-by tag.
> ---
> diff --git a/tools/perf/pmu-events/arch/powerpc/power10/nest_metrics.json b/tools/perf/pmu-events/arch/powerpc/power10/nest_metrics.json
> new file mode 100644
> index 000000000000..8ba3e81c9808
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/powerpc/power10/nest_metrics.json
> @@ -0,0 +1,424 @@
> +[
> + {
> + "MetricName": "VEC_GROUP_PUMP_RETRY_RATIO_P01",
> + "MetricExpr": "(hv_24x7@PM_PB_RTY_VG_PUMP01\\,chip\\=?@ / hv_24x7@PM_PB_VG_PUMP01\\,chip\\=?@) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "VEC_GROUP_PUMP_RETRY_RATIO_P23",
> + "MetricExpr": "(hv_24x7@PM_PB_RTY_VG_PUMP23\\,chip\\=?@ / hv_24x7@PM_PB_VG_PUMP23\\,chip\\=?@) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "LOCAL_NODE_PUMP_RETRY_RATIO_P01",
> + "MetricExpr": "(hv_24x7@PM_PB_RTY_LNS_PUMP01\\,chip\\=?@ / hv_24x7@PM_PB_LNS_PUMP01\\,chip\\=?@) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "LOCAL_NODE_PUMP_RETRY_RATIO_P23",
> + "MetricExpr": "(hv_24x7@PM_PB_RTY_LNS_PUMP23\\,chip\\=?@ / hv_24x7@PM_PB_LNS_PUMP23\\,chip\\=?@) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "GROUP_PUMP_RETRY_RATIO_P01",
> + "MetricExpr": "(hv_24x7@PM_PB_RTY_GROUP_PUMP01\\,chip\\=?@ / hv_24x7@PM_PB_GROUP_PUMP01\\,chip\\=?@) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "GROUP_PUMP_RETRY_RATIO_P23",
> + "MetricExpr": "(hv_24x7@PM_PB_RTY_GROUP_PUMP23\\,chip\\=?@ / hv_24x7@PM_PB_GROUP_PUMP23\\,chip\\=?@) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_GROUP_PUMPS_P01",
> + "MetricExpr": "(hv_24x7@PM_PB_GROUP_PUMP01\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
> + "ScaleUnit": "4",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_GROUP_PUMPS_P23",
> + "MetricExpr": "(hv_24x7@PM_PB_GROUP_PUMP23\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
> + "ScaleUnit": "4",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_GROUP_PUMPS_RETRIES_P01",
> + "MetricExpr": "(hv_24x7@PM_PB_RTY_GROUP_PUMP01\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
> + "ScaleUnit": "4",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_GROUP_PUMPS_RETRIES_P23",
> + "MetricExpr": "(hv_24x7@PM_PB_RTY_GROUP_PUMP23\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
> + "ScaleUnit": "4",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "REMOTE_NODE_PUMPS_RETRIES_RATIO_P01",
> + "MetricExpr": "(hv_24x7@PM_PB_RTY_RNS_PUMP01\\,chip\\=?@ / hv_24x7@PM_PB_RNS_PUMP01\\,chip\\=?@) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "REMOTE_NODE_PUMPS_RETRIES_RATIO_P23",
> + "MetricExpr": "(hv_24x7@PM_PB_RTY_RNS_PUMP23\\,chip\\=?@ / hv_24x7@PM_PB_RNS_PUMP23\\,chip\\=?@) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_VECTOR_GROUP_PUMPS_P01",
> + "MetricExpr": "(hv_24x7@PM_PB_VG_PUMP01\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
> + "ScaleUnit": "4",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_VECTOR_GROUP_PUMPS_P23",
> + "MetricExpr": "(hv_24x7@PM_PB_VG_PUMP23\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
> + "ScaleUnit": "4",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_LOCAL_NODE_PUMPS_P01",
> + "MetricExpr": "(hv_24x7@PM_PB_LNS_PUMP01\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
> + "ScaleUnit": "4",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_LOCAL_NODE_PUMPS_P23",
> + "MetricExpr": "(hv_24x7@PM_PB_LNS_PUMP23\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
> + "ScaleUnit": "4",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_VECTOR_GROUP_PUMPS_RETRIES_P01",
> + "MetricExpr": "(hv_24x7@PM_PB_RTY_VG_PUMP01\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
> + "ScaleUnit": "4",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_VECTOR_GROUP_PUMPS_RETRIES_P23",
> + "MetricExpr": "(hv_24x7@PM_PB_RTY_VG_PUMP23\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
> + "ScaleUnit": "4",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_LOCAL_NODE_PUMPS_RETRIES_P01",
> + "MetricExpr": "(hv_24x7@PM_PB_RTY_LNS_PUMP01\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
> + "ScaleUnit": "4",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_LOCAL_NODE_PUMPS_RETRIES_P23",
> + "MetricExpr": "(hv_24x7@PM_PB_RTY_LNS_PUMP23\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
> + "ScaleUnit": "4",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_REMOTE_NODE_PUMPS_P01",
> + "MetricExpr": "(hv_24x7@PM_PB_RNS_PUMP01\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
> + "ScaleUnit": "4",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_REMOTE_NODE_PUMPS_P23",
> + "MetricExpr": "(hv_24x7@PM_PB_RNS_PUMP23\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
> + "ScaleUnit": "4",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_NEAR_NODE_PUMPS_P01",
> + "MetricExpr": "(hv_24x7@PM_PB_NNS_PUMP01\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
> + "ScaleUnit": "4",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_NEAR_NODE_PUMPS_P23",
> + "MetricExpr": "(hv_24x7@PM_PB_NNS_PUMP23\\,chip\\=?@ / hv_24x7@PM_PAU_CYC\\,chip\\=?@)",
> + "ScaleUnit": "4",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_INT_PB_BW",
> + "MetricExpr": "(hv_24x7@PM_PB_INT_DATA_XFER\\,chip\\=?@)",
> + "ScaleUnit": "2.09MB",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "XLINK0_OUT_TOTAL_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_XLINK0_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_XLINK0_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_XLINK0_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK0_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "XLINK1_OUT_TOTAL_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_XLINK1_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_XLINK1_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_XLINK1_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK1_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "XLINK2_OUT_TOTAL_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_XLINK2_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_XLINK2_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_XLINK2_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK2_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "XLINK3_OUT_TOTAL_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_XLINK3_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_XLINK3_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_XLINK3_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK3_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "XLINK4_OUT_TOTAL_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_XLINK4_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_XLINK4_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_XLINK4_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK4_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "XLINK5_OUT_TOTAL_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_XLINK5_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_XLINK5_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_XLINK5_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK5_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "XLINK6_OUT_TOTAL_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_XLINK6_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_XLINK6_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_XLINK6_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK6_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "XLINK7_OUT_TOTAL_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_XLINK7_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_XLINK7_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_XLINK7_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK7_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "XLINK0_OUT_DATA_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_XLINK0_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_XLINK0_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_XLINK0_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK0_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1.063%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "XLINK1_OUT_DATA_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_XLINK1_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_XLINK1_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_XLINK1_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK1_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1.063%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "XLINK2_OUT_DATA_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_XLINK2_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_XLINK2_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_XLINK2_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK2_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1.063%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "XLINK3_OUT_DATA_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_XLINK3_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_XLINK3_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_XLINK3_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK3_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1.063%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "XLINK4_OUT_DATA_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_XLINK4_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_XLINK4_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_XLINK4_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK4_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1.063%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "XLINK5_OUT_DATA_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_XLINK5_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_XLINK5_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_XLINK5_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK5_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1.063%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "XLINK6_OUT_DATA_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_XLINK6_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_XLINK6_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_XLINK6_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK6_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1.063%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "XLINK7_OUT_DATA_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_XLINK7_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_XLINK7_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_XLINK7_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_XLINK7_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1.063%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "ALINK0_OUT_TOTAL_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_ALINK0_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_ALINK0_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_ALINK0_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK0_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "ALINK1_OUT_TOTAL_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_ALINK1_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_ALINK1_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_ALINK1_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK1_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "ALINK2_OUT_TOTAL_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_ALINK2_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_ALINK2_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_ALINK2_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK2_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "ALINK3_OUT_TOTAL_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_ALINK3_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_ALINK3_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_ALINK3_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK3_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "ALINK4_OUT_TOTAL_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_ALINK4_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_ALINK4_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_ALINK4_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK4_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "ALINK5_OUT_TOTAL_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_ALINK5_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_ALINK5_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_ALINK5_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK5_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "ALINK6_OUT_TOTAL_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_ALINK6_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_ALINK6_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_ALINK6_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK6_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "ALINK7_OUT_TOTAL_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_ALINK7_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + hv_24x7@PM_ALINK7_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (hv_24x7@PM_ALINK7_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK7_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "ALINK0_OUT_DATA_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_ALINK0_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_ALINK0_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_ALINK0_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK0_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1.063%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "ALINK1_OUT_DATA_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_ALINK1_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_ALINK1_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_ALINK1_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK1_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1.063%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "ALINK2_OUT_DATA_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_ALINK2_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_ALINK2_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_ALINK2_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK2_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1.063%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "ALINK3_OUT_DATA_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_ALINK3_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_ALINK3_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_ALINK3_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK3_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1.063%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "ALINK4_OUT_DATA_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_ALINK4_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_ALINK4_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_ALINK4_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK4_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1.063%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "ALINK5_OUT_DATA_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_ALINK5_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_ALINK5_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_ALINK5_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK5_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1.063%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "ALINK6_OUT_DATA_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_ALINK6_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_ALINK6_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_ALINK6_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK6_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1.063%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "ALINK7_OUT_DATA_UTILIZATION",
> + "MetricExpr": "((hv_24x7@PM_ALINK7_OUT_ODD_DATA\\,chip\\=?@ + hv_24x7@PM_ALINK7_OUT_EVEN_DATA\\,chip\\=?@) / (hv_24x7@PM_ALINK7_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + hv_24x7@PM_ALINK7_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> + "ScaleUnit": "1.063%",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_DATA_BANDWIDTH_TRANSFERRED_OVER_PB_PCI1",
> + "MetricExpr": "(hv_24x7@PM_PCI1_32B_INOUT\\,chip\\=?@)",
> + "ScaleUnit": "3.28e-2MB",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_DATA_BANDWIDTH_TRANSFERRED_OVER_PB_PCI0",
> + "MetricExpr": "(hv_24x7@PM_PCI0_32B_INOUT\\,chip\\=?@)",
> + "ScaleUnit": "3.28e-2MB",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_MCS_READ_BW_MC0_CHAN01",
> + "MetricExpr": "(hv_24x7@PM_MCS_128B_RD_DATA_BLOCKS_MC0_CHAN01\\,chip\\=?@)",
> + "ScaleUnit": "5.24e-1MB",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_MCS_READ_BW_MC1_CHAN01",
> + "MetricExpr": "(hv_24x7@PM_MCS_128B_RD_DATA_BLOCKS_MC1_CHAN01\\,chip\\=?@)",
> + "ScaleUnit": "5.24e-1MB",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_MCS_READ_BW_MC2_CHAN01",
> + "MetricExpr": "(hv_24x7@PM_MCS_128B_RD_DATA_BLOCKS_MC2_CHAN01\\,chip\\=?@)",
> + "ScaleUnit": "5.24e-1MB",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_MCS_READ_BW_MC3_CHAN01",
> + "MetricExpr": "(hv_24x7@PM_MCS_128B_RD_DATA_BLOCKS_MC3_CHAN01\\,chip\\=?@)",
> + "ScaleUnit": "5.24e-1MB",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_MCS_WRITE_BW_MC0_CHAN01",
> + "MetricExpr": "(hv_24x7@PM_MCS_64B_WR_DATA_BLOCKS_MC0_CHAN01\\,chip\\=?@)",
> + "ScaleUnit": "2.6e-1MB",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_MCS_WRITE_BW_MC1_CHAN01",
> + "MetricExpr": "(hv_24x7@PM_MCS_64B_WR_DATA_BLOCKS_MC1_CHAN01\\,chip\\=?@)",
> + "ScaleUnit": "2.6e-1MB",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_MCS_WRITE_BW_MC2_CHAN01",
> + "MetricExpr": "(hv_24x7@PM_MCS_64B_WR_DATA_BLOCKS_MC2_CHAN01\\,chip\\=?@)",
> + "ScaleUnit": "2.6e-1MB",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "TOTAL_MCS_WRITE_BW_MC3_CHAN01",
> + "MetricExpr": "(hv_24x7@PM_MCS_64B_WR_DATA_BLOCKS_MC3_CHAN01\\,chip\\=?@)",
> + "ScaleUnit": "2.6e-1MB",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "Memory_RD_BW_Chip",
> + "MetricExpr": "(hv_24x7@PM_MCS_128B_RD_DATA_BLOCKS_MC0_CHAN01\\,chip\\=?@ + hv_24x7@PM_MCS_128B_RD_DATA_BLOCKS_MC1_CHAN01\\,chip\\=?@ + hv_24x7@PM_MCS_128B_RD_DATA_BLOCKS_MC2_CHAN01\\,chip\\=?@ + hv_24x7@PM_MCS_128B_RD_DATA_BLOCKS_MC3_CHAN01\\,chip\\=?@)",
> + "MetricGroup": "Memory_BW",
> + "ScaleUnit": "5.24e-1MB",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "Memory_WR_BW_Chip",
> + "MetricExpr": "(hv_24x7@PM_MCS_64B_WR_DATA_BLOCKS_MC0_CHAN01\\,chip\\=?@ + hv_24x7@PM_MCS_64B_WR_DATA_BLOCKS_MC1_CHAN01\\,chip\\=?@ + hv_24x7@PM_MCS_64B_WR_DATA_BLOCKS_MC2_CHAN01\\,chip\\=?@ + hv_24x7@PM_MCS_64B_WR_DATA_BLOCKS_MC3_CHAN01\\,chip\\=?@ )",
> + "MetricGroup": "Memory_BW",
> + "ScaleUnit": "2.6e-1MB",
> + "AggregationMode": "PerChip"
> + },
> + {
> + "MetricName": "PowerBUS_Frequency",
> + "MetricExpr": "(hv_24x7@PM_PAU_CYC\\,chip\\=?@ )",
> + "ScaleUnit": "2.56e-7GHz",
> + "AggregationMode": "PerChip"
> + }
> +]
> --
> 2.31.1
>
--
- Arnaldo
^ permalink raw reply
* Re: [PATCH] perf script python: Fix buffer size to report iregs in perf script
From: Arnaldo Carvalho de Melo @ 2021-07-07 14:04 UTC (permalink / raw)
To: kajoljain
Cc: ravi.bangoria, atrajeev, rnsastry, linuxppc-dev, linux-kernel,
linux-perf-users, maddy, Paul A. Clarke, Jiri Olsa
In-Reply-To: <d59266da-2aa6-69ff-646b-144ba874ee2f@linux.ibm.com>
Em Wed, Jul 07, 2021 at 11:16:20AM +0530, kajoljain escreveu:
> On 7/7/21 12:45 AM, Arnaldo Carvalho de Melo wrote:
> > Em Tue, Jul 06, 2021 at 05:26:12PM +0530, kajoljain escreveu:
> >> On 6/29/21 12:39 PM, kajoljain wrote:
> >>> On 6/28/21 8:19 PM, Paul A. Clarke wrote:
> >>>> On Mon, Jun 28, 2021 at 11:53:41AM +0530, Kajol Jain wrote:
> >>>>> @@ -713,7 +711,16 @@ static void set_regs_in_dict(PyObject *dict,
> >>>>> struct evsel *evsel)
> >>>>> {
> >>>>> struct perf_event_attr *attr = &evsel->core.attr;
> >>>>> - char bf[512];
> >>>>> +
> >>>>> + /*
> >>>>> + * Here value 28 is a constant size which can be used to print
> >>>>> + * one register value and its corresponds to:
> >>>>> + * 16 chars is to specify 64 bit register in hexadecimal.
> >>>>> + * 2 chars is for appending "0x" to the hexadecimal value and
> >>>>> + * 10 chars is for register name.
> >>>>> + */
> >>>>> + int size = __sw_hweight64(attr->sample_regs_intr) * 28;
> >>>>> + char bf[size];
> >>>> I propose using a template rather than a magic number here. Something like:
> >>>> const char reg_name_tmpl[] = "10 chars ";
> >>>> const char reg_value_tmpl[] = "0x0123456789abcdef";
> >>>> const int size = __sw_hweight64(attr->sample_regs_intr) +
> >>>> sizeof reg_name_tmpl + sizeof reg_value_tmpl;
> >>> Thanks for reviewing the patch. Yes these are
> >>> some standardization we can do by creating macros for different
> >>> fields.
> >>> The basic idea is, we want to provide significant buffer size
> >>> based on number of registers present in sample_regs_intr to accommodate
> >>> all data.
> >> Is the approach used in this patch looks fine to you?
> > Yeah, and the comment you provide right above it explains it, so I think
> > that is enough, ok?
> Thanks for reviewing it. As you said added comment already explains
> why we are taking size constant as 28, should we skip adding macros part?
> Can you pull this patch.
Sure.
- Arnaldo
^ permalink raw reply
* Re: [RFC PATCH] powerpc: flexible register range save/restore macros
From: Nicholas Piggin @ 2021-07-07 13:57 UTC (permalink / raw)
To: Christophe Leroy, linuxppc-dev
In-Reply-To: <dc76505a-dbb3-ba3b-651e-32bcacd64d28@csgroup.eu>
Excerpts from Christophe Leroy's message of July 5, 2021 3:52 pm:
>
>
> Le 03/07/2021 à 11:14, Nicholas Piggin a écrit :
>> Introduce macros that operate on a (start, end) range of registers,
>> which reduces lines of code and need to do mental arithmetic while
>> reading the code.
>
> Looks like a nice patch.
>
> Maybe you could split the patch in two parts, one part for GPRs and one patch for the FP/VR regs.
Sure I can do that.
Thanks,
Nick
^ permalink raw reply
* Re: [PATCH v2] xen/hvc: replace BUG_ON() with negative return value
From: Jiri Slaby @ 2021-07-07 10:58 UTC (permalink / raw)
To: Juergen Gross, Jan Beulich
Cc: Greg Kroah-Hartman, linuxppc-dev, linux-kernel, xen-devel
In-Reply-To: <dd32b09b-7345-664b-165d-dfb30c285448@suse.com>
On 07. 07. 21, 12:40, Juergen Gross wrote:
>> And btw, since I've got puzzled by the linuxppc-dev@ in the recipients
>> list, I did look up relevant entries in ./MAINTAINERS. Shouldn't the
>> file be part of "XEN HYPERVISOR INTERFACE"?
>
> I wouldn't mind. Greg, Jiri, what do you think?
/me concurs.
thanks,
--
js
suse labs
^ permalink raw reply
* Re: [PATCH v2] xen/hvc: replace BUG_ON() with negative return value
From: Juergen Gross @ 2021-07-07 10:40 UTC (permalink / raw)
To: Jan Beulich
Cc: Greg Kroah-Hartman, linuxppc-dev, Jiri Slaby, linux-kernel,
xen-devel
In-Reply-To: <9e45c5f8-0ac0-e1bb-4703-838679285e80@suse.com>
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On 07.07.21 11:57, Jan Beulich wrote:
> On 07.07.2021 11:10, Juergen Gross wrote:
>> Xen frontends shouldn't BUG() in case of illegal data received from
>> their backends. So replace the BUG_ON()s when reading illegal data from
>> the ring page with negative return values.
>>
>> Signed-off-by: Juergen Gross <jgross@suse.com>
>
> Reviewed-by: Jan Beulich <jbeulich@suse.com>
>
>> --- a/drivers/tty/hvc/hvc_xen.c
>> +++ b/drivers/tty/hvc/hvc_xen.c
>> @@ -86,7 +86,11 @@ static int __write_console(struct xencons_info *xencons,
>> cons = intf->out_cons;
>> prod = intf->out_prod;
>> mb(); /* update queue values before going on */
>
> Largely unrelated note: While in general the barriers here may want
> switching to virt_*mb(), this particular one looks to be too heavy
> anyway: a read barrier is all that's needed here afaict, just like
> there's only a write barrier between ring contents and producer
> writing in __write_console().
I agree.
> And btw, since I've got puzzled by the linuxppc-dev@ in the recipients
> list, I did look up relevant entries in ./MAINTAINERS. Shouldn't the
> file be part of "XEN HYPERVISOR INTERFACE"?
I wouldn't mind. Greg, Jiri, what do you think?
Juergen
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^ permalink raw reply
* Re: [PATCH v2] xen/hvc: replace BUG_ON() with negative return value
From: Jan Beulich @ 2021-07-07 9:57 UTC (permalink / raw)
To: Juergen Gross
Cc: Greg Kroah-Hartman, linuxppc-dev, Jiri Slaby, linux-kernel,
xen-devel
In-Reply-To: <20210707091045.460-1-jgross@suse.com>
On 07.07.2021 11:10, Juergen Gross wrote:
> Xen frontends shouldn't BUG() in case of illegal data received from
> their backends. So replace the BUG_ON()s when reading illegal data from
> the ring page with negative return values.
>
> Signed-off-by: Juergen Gross <jgross@suse.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
> --- a/drivers/tty/hvc/hvc_xen.c
> +++ b/drivers/tty/hvc/hvc_xen.c
> @@ -86,7 +86,11 @@ static int __write_console(struct xencons_info *xencons,
> cons = intf->out_cons;
> prod = intf->out_prod;
> mb(); /* update queue values before going on */
Largely unrelated note: While in general the barriers here may want
switching to virt_*mb(), this particular one looks to be too heavy
anyway: a read barrier is all that's needed here afaict, just like
there's only a write barrier between ring contents and producer
writing in __write_console().
And btw, since I've got puzzled by the linuxppc-dev@ in the recipients
list, I did look up relevant entries in ./MAINTAINERS. Shouldn't the
file be part of "XEN HYPERVISOR INTERFACE"?
Jan
^ permalink raw reply
* Re: [FSL P50xx] IRQ issues
From: Nicholas Piggin @ 2021-07-07 9:29 UTC (permalink / raw)
To: Christian Zigotzky, linuxppc-dev
Cc: Darren Stevens, R.T.Dickinson, mad skateman, Christian Zigotzky
In-Reply-To: <74509635-f4e2-d6e7-311f-dbdab8fe317f@xenosoft.de>
Nice, thanks for reporting and testing. I submitted a qemu patch to
hopefully avoid this happening again in future.
Thanks,
Nick
Excerpts from Christian Zigotzky's message of July 7, 2021 1:22 am:
> Hi Nick,
>
> Your patch works (see patch below)! Many thanks for your help! We tested
> it on an A-EON AmigaOne X5000/20 and in a virtual e5500 QEMU machine today.
>
> Screenshots:
>
> -
> http://www.skateman.nl/wp-content/uploads/2021/07/Screenshot-at-2021-07-06-113237.png
> - https://i.ibb.co/h813RRp/Kernel-5-14-alpha3-Power-PC.png
>
> Thanks,
> Christian
>
> On 06 July 2021 at 06:07 am, Christian Zigotzky wrote:
>> Hi Nick,
>>
>> Thanks a lot for your patch! We will test it as soon as possible.
>> You're right that this issue doesn't exist in a virtual e5500 QEMU
>> machine.
>>
>> Have a nice day,
>> Christian
>>
>> On 06 July 2021 at 01:36 am, Nicholas Piggin wrote:
>>> Excerpts from Christian Zigotzky's message of July 6, 2021 4:49 am:
>>>> Hi All,
>>>>
>>>> Our FSL P50xx machines don't boot anymore because of IRQ issues. [1]
>>>>
>>>> Please check the IRQ changes in the latest PowerPC updates 5.14-1. [2]
>>>>
>>>> Thanks,
>>>> Christian
>>>>
>>>> [1]
>>>> https://forum.hyperion-entertainment.com/download/file.php?id=2592&mode=view
>>>>
>>>> [2]
>>>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=019b3fd94ba73d3ac615f0537440b81f129821f6
>>>>
>>> This looks like mtmsrd in the 64e code. I think this should fix it.
>>>
>>> QEMU does not seem to trap on this, maybe something to improve.
>>>
>>> Thanks,
>>> Nick
>>> --
>>>
>>> diff --git a/arch/powerpc/kernel/interrupt_64.S
>>> b/arch/powerpc/kernel/interrupt_64.S
>>> index 4063e8a3f704..d4212d2ff0b5 100644
>>> --- a/arch/powerpc/kernel/interrupt_64.S
>>> +++ b/arch/powerpc/kernel/interrupt_64.S
>>> @@ -311,9 +311,13 @@ END_BTB_FLUSH_SECTION
>>> * trace_hardirqs_off().
>>> */
>>> li r11,IRQS_ALL_DISABLED
>>> - li r12,-1 /* Set MSR_EE and MSR_RI */
>>> stb r11,PACAIRQSOFTMASK(r13)
>>> +#ifdef CONFIG_PPC_BOOK3S
>>> + li r12,-1 /* Set MSR_EE and MSR_RI */
>>> mtmsrd r12,1
>>> +#else
>>> + wrteei 1
>>> +#endif
>>> /* Calling convention has r9 = orig r0, r10 = regs */
>>> mr r9,r0
>>
>
>
^ permalink raw reply
* [PATCH v2] xen/hvc: replace BUG_ON() with negative return value
From: Juergen Gross @ 2021-07-07 9:10 UTC (permalink / raw)
To: xen-devel, linuxppc-dev, linux-kernel
Cc: Juergen Gross, Greg Kroah-Hartman, Jiri Slaby
Xen frontends shouldn't BUG() in case of illegal data received from
their backends. So replace the BUG_ON()s when reading illegal data from
the ring page with negative return values.
Signed-off-by: Juergen Gross <jgross@suse.com>
---
V2:
- drop BUG_ON() (Christophe Leroy, Greg Kroah-Hartmann)
- replace WARN_ONCE() by pr_err_once() (Greg Kroah-Hartmann)
- break out from original series
---
drivers/tty/hvc/hvc_xen.c | 17 ++++++++++++++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/drivers/tty/hvc/hvc_xen.c b/drivers/tty/hvc/hvc_xen.c
index 92c9a476defc..8f143c09a169 100644
--- a/drivers/tty/hvc/hvc_xen.c
+++ b/drivers/tty/hvc/hvc_xen.c
@@ -86,7 +86,11 @@ static int __write_console(struct xencons_info *xencons,
cons = intf->out_cons;
prod = intf->out_prod;
mb(); /* update queue values before going on */
- BUG_ON((prod - cons) > sizeof(intf->out));
+
+ if ((prod - cons) > sizeof(intf->out)) {
+ pr_err_once("xencons: Illegal ring page indices");
+ return -EINVAL;
+ }
while ((sent < len) && ((prod - cons) < sizeof(intf->out)))
intf->out[MASK_XENCONS_IDX(prod++, intf->out)] = data[sent++];
@@ -114,7 +118,10 @@ static int domU_write_console(uint32_t vtermno, const char *data, int len)
*/
while (len) {
int sent = __write_console(cons, data, len);
-
+
+ if (sent < 0)
+ return sent;
+
data += sent;
len -= sent;
@@ -138,7 +145,11 @@ static int domU_read_console(uint32_t vtermno, char *buf, int len)
cons = intf->in_cons;
prod = intf->in_prod;
mb(); /* get pointers before reading ring */
- BUG_ON((prod - cons) > sizeof(intf->in));
+
+ if ((prod - cons) > sizeof(intf->in)) {
+ pr_err_once("xencons: Illegal ring page indices");
+ return -EINVAL;
+ }
while (cons != prod && recv < len)
buf[recv++] = intf->in[MASK_XENCONS_IDX(cons++, intf->in)];
--
2.26.2
^ permalink raw reply related
* [PATCH] powerpc/perf: Fix cycles/instructions as PM_CYC/PM_INST_CMPL in power10
From: Athira Rajeev @ 2021-07-07 6:39 UTC (permalink / raw)
To: mpe; +Cc: maddy, linuxppc-dev
From: Athira Rajeev <atrajeev@linux.vnet.ibm.cm>
Power10 performance monitoring unit (PMU) driver uses performance
monitor counter 5 (PMC5) and performance monitor counter 6 (PMC6)
for counting instructions and cycles. Event used for cycles is
PM_RUN_CYC and instructions is PM_RUN_INST_CMPL. But counting of these
events in wait state is controlled by the CC56RUN bit setting in
Monitor Mode Control Register0 (MMCR0). If the CC56RUN bit is not
set, PMC5/6 will not count when CTRL[RUN] is zero.
Patch sets the CC56RUN bit in MMCR0 for power10 which makes PMC5 and
PMC6 count instructions and cycles regardless of the run bit. With this
change, these events are also now renamed to PM_CYC and PM_INST_CMPL
rather than PM_RUN_CYC and PM_RUN_INST_CMPL.
Fixes: a64e697cef23 ("powerpc/perf: power10 Performance Monitoring support")
Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.cm>
Reviewed-by: Madhavan Srinivasan <maddy@linux.ibm.com>
---
Notes on testing done for this change:
Tested this patch change with a kernel module that
turns off and turns on the runlatch. kernel module also
reads the counter values for PMC5 and PMC6 during the
period when runlatch is off.
- Started PMU counters via "perf stat" and loaded the
test module.
- Checked the counter values captured from module during
the runlatch off period.
- Verified that counters were frozen without the patch and
with the patch, observed counters were incrementing.
arch/powerpc/perf/power10-events-list.h | 8 +++---
arch/powerpc/perf/power10-pmu.c | 44 +++++++++++++++++++++++----------
2 files changed, 35 insertions(+), 17 deletions(-)
diff --git a/arch/powerpc/perf/power10-events-list.h b/arch/powerpc/perf/power10-events-list.h
index 93be719..564f1409 100644
--- a/arch/powerpc/perf/power10-events-list.h
+++ b/arch/powerpc/perf/power10-events-list.h
@@ -9,10 +9,10 @@
/*
* Power10 event codes.
*/
-EVENT(PM_RUN_CYC, 0x600f4);
+EVENT(PM_CYC, 0x600f4);
EVENT(PM_DISP_STALL_CYC, 0x100f8);
EVENT(PM_EXEC_STALL, 0x30008);
-EVENT(PM_RUN_INST_CMPL, 0x500fa);
+EVENT(PM_INST_CMPL, 0x500fa);
EVENT(PM_BR_CMPL, 0x4d05e);
EVENT(PM_BR_MPRED_CMPL, 0x400f6);
EVENT(PM_BR_FIN, 0x2f04a);
@@ -50,8 +50,8 @@
/* ITLB Reloaded */
EVENT(PM_ITLB_MISS, 0x400fc);
-EVENT(PM_RUN_CYC_ALT, 0x0001e);
-EVENT(PM_RUN_INST_CMPL_ALT, 0x00002);
+EVENT(PM_CYC_ALT, 0x0001e);
+EVENT(PM_INST_CMPL_ALT, 0x00002);
/*
* Memory Access Events
diff --git a/arch/powerpc/perf/power10-pmu.c b/arch/powerpc/perf/power10-pmu.c
index f9d64c6..9dd75f3 100644
--- a/arch/powerpc/perf/power10-pmu.c
+++ b/arch/powerpc/perf/power10-pmu.c
@@ -91,8 +91,8 @@
/* Table of alternatives, sorted by column 0 */
static const unsigned int power10_event_alternatives[][MAX_ALT] = {
- { PM_RUN_CYC_ALT, PM_RUN_CYC },
- { PM_RUN_INST_CMPL_ALT, PM_RUN_INST_CMPL },
+ { PM_CYC_ALT, PM_CYC },
+ { PM_INST_CMPL_ALT, PM_INST_CMPL },
};
static int power10_get_alternatives(u64 event, unsigned int flags, u64 alt[])
@@ -118,8 +118,8 @@ static int power10_check_attr_config(struct perf_event *ev)
return 0;
}
-GENERIC_EVENT_ATTR(cpu-cycles, PM_RUN_CYC);
-GENERIC_EVENT_ATTR(instructions, PM_RUN_INST_CMPL);
+GENERIC_EVENT_ATTR(cpu-cycles, PM_CYC);
+GENERIC_EVENT_ATTR(instructions, PM_INST_CMPL);
GENERIC_EVENT_ATTR(branch-instructions, PM_BR_CMPL);
GENERIC_EVENT_ATTR(branch-misses, PM_BR_MPRED_CMPL);
GENERIC_EVENT_ATTR(cache-references, PM_LD_REF_L1);
@@ -148,8 +148,8 @@ static int power10_check_attr_config(struct perf_event *ev)
CACHE_EVENT_ATTR(iTLB-load-misses, PM_ITLB_MISS);
static struct attribute *power10_events_attr_dd1[] = {
- GENERIC_EVENT_PTR(PM_RUN_CYC),
- GENERIC_EVENT_PTR(PM_RUN_INST_CMPL),
+ GENERIC_EVENT_PTR(PM_CYC),
+ GENERIC_EVENT_PTR(PM_INST_CMPL),
GENERIC_EVENT_PTR(PM_BR_CMPL),
GENERIC_EVENT_PTR(PM_BR_MPRED_CMPL),
GENERIC_EVENT_PTR(PM_LD_REF_L1),
@@ -173,8 +173,8 @@ static int power10_check_attr_config(struct perf_event *ev)
};
static struct attribute *power10_events_attr[] = {
- GENERIC_EVENT_PTR(PM_RUN_CYC),
- GENERIC_EVENT_PTR(PM_RUN_INST_CMPL),
+ GENERIC_EVENT_PTR(PM_CYC),
+ GENERIC_EVENT_PTR(PM_INST_CMPL),
GENERIC_EVENT_PTR(PM_BR_FIN),
GENERIC_EVENT_PTR(PM_MPRED_BR_FIN),
GENERIC_EVENT_PTR(PM_LD_REF_L1),
@@ -271,8 +271,8 @@ static int power10_check_attr_config(struct perf_event *ev)
};
static int power10_generic_events_dd1[] = {
- [PERF_COUNT_HW_CPU_CYCLES] = PM_RUN_CYC,
- [PERF_COUNT_HW_INSTRUCTIONS] = PM_RUN_INST_CMPL,
+ [PERF_COUNT_HW_CPU_CYCLES] = PM_CYC,
+ [PERF_COUNT_HW_INSTRUCTIONS] = PM_INST_CMPL,
[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = PM_BR_CMPL,
[PERF_COUNT_HW_BRANCH_MISSES] = PM_BR_MPRED_CMPL,
[PERF_COUNT_HW_CACHE_REFERENCES] = PM_LD_REF_L1,
@@ -280,8 +280,8 @@ static int power10_check_attr_config(struct perf_event *ev)
};
static int power10_generic_events[] = {
- [PERF_COUNT_HW_CPU_CYCLES] = PM_RUN_CYC,
- [PERF_COUNT_HW_INSTRUCTIONS] = PM_RUN_INST_CMPL,
+ [PERF_COUNT_HW_CPU_CYCLES] = PM_CYC,
+ [PERF_COUNT_HW_INSTRUCTIONS] = PM_INST_CMPL,
[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = PM_BR_FIN,
[PERF_COUNT_HW_BRANCH_MISSES] = PM_MPRED_BR_FIN,
[PERF_COUNT_HW_CACHE_REFERENCES] = PM_LD_REF_L1,
@@ -548,6 +548,24 @@ static void power10_config_bhrb(u64 pmu_bhrb_filter)
#undef C
+/*
+ * Set the MMCR0[CC56RUN] bit to enable counting for
+ * PMC5 and PMC6 regardless of the state of CTRL[RUN],
+ * so that we can use counters 5 and 6 as PM_INST_CMPL and
+ * PM_CYC.
+ */
+static int power10_compute_mmcr(u64 event[], int n_ev,
+ unsigned int hwc[], struct mmcr_regs *mmcr,
+ struct perf_event *pevents[], u32 flags)
+{
+ int ret;
+
+ ret = isa207_compute_mmcr(event, n_ev, hwc, mmcr, pevents, flags);
+ if (!ret)
+ mmcr->mmcr0 |= MMCR0_C56RUN;
+ return ret;
+}
+
static struct power_pmu power10_pmu = {
.name = "POWER10",
.n_counter = MAX_PMU_COUNTERS,
@@ -555,7 +573,7 @@ static void power10_config_bhrb(u64 pmu_bhrb_filter)
.test_adder = ISA207_TEST_ADDER,
.group_constraint_mask = CNST_CACHE_PMC4_MASK,
.group_constraint_val = CNST_CACHE_PMC4_VAL,
- .compute_mmcr = isa207_compute_mmcr,
+ .compute_mmcr = power10_compute_mmcr,
.config_bhrb = power10_config_bhrb,
.bhrb_filter_map = power10_bhrb_filter_map,
.get_constraint = isa207_get_constraint,
--
1.8.3.1
^ permalink raw reply related
* [PATCH] powerpc/32: Fix critical and debug interrupts on BOOKE
From: Christophe Leroy @ 2021-07-07 5:55 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman,
radu.rendec
Cc: linuxppc-dev, linux-kernel
32 bits BOOKE have special interrupts for debug and other
critical events.
When handling those interrupts, dedicated registers are saved
in the stack frame in addition to the standard registers, leading
to a shift of the pt_regs struct.
Since commit db297c3b07af ("powerpc/32: Don't save thread.regs on
interrupt entry"), the pt_regs struct is expected to be at the
same place all the time.
Instead of handling a special struct in addition to pt_regs, just
add those special registers to struct pt_regs.
Reported-by: Radu Rendec <radu.rendec@gmail.com>
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Fixes: db297c3b07af ("powerpc/32: Don't save thread.regs on interrupt entry")
Cc: stable@vger.kernel.org
---
arch/powerpc/include/asm/ptrace.h | 16 ++++++++++++++++
arch/powerpc/kernel/asm-offsets.c | 31 ++++++++++++++-----------------
arch/powerpc/kernel/head_booke.h | 27 +++------------------------
3 files changed, 33 insertions(+), 41 deletions(-)
diff --git a/arch/powerpc/include/asm/ptrace.h b/arch/powerpc/include/asm/ptrace.h
index 3e5d470a6155..14422e851494 100644
--- a/arch/powerpc/include/asm/ptrace.h
+++ b/arch/powerpc/include/asm/ptrace.h
@@ -70,6 +70,22 @@ struct pt_regs
unsigned long __pad[4]; /* Maintain 16 byte interrupt stack alignment */
};
#endif
+#if defined(CONFIG_PPC32) && defined(CONFIG_BOOKE)
+ struct { /* Must be a multiple of 16 bytes */
+ unsigned long mas0;
+ unsigned long mas1;
+ unsigned long mas2;
+ unsigned long mas3;
+ unsigned long mas6;
+ unsigned long mas7;
+ unsigned long srr0;
+ unsigned long srr1;
+ unsigned long csrr0;
+ unsigned long csrr1;
+ unsigned long dsrr0;
+ unsigned long dsrr1;
+ };
+#endif
};
#endif
diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c
index a47eefa09bcb..5bee245d832b 100644
--- a/arch/powerpc/kernel/asm-offsets.c
+++ b/arch/powerpc/kernel/asm-offsets.c
@@ -309,24 +309,21 @@ int main(void)
STACK_PT_REGS_OFFSET(STACK_REGS_IAMR, iamr);
#endif
-#if defined(CONFIG_PPC32)
-#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
- DEFINE(EXC_LVL_SIZE, STACK_EXC_LVL_FRAME_SIZE);
- DEFINE(MAS0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas0));
+#if defined(CONFIG_PPC32) && defined(CONFIG_BOOKE)
+ STACK_PT_REGS_OFFSET(MAS0, mas0);
/* we overload MMUCR for 44x on MAS0 since they are mutually exclusive */
- DEFINE(MMUCR, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas0));
- DEFINE(MAS1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas1));
- DEFINE(MAS2, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas2));
- DEFINE(MAS3, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas3));
- DEFINE(MAS6, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas6));
- DEFINE(MAS7, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas7));
- DEFINE(_SRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, srr0));
- DEFINE(_SRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, srr1));
- DEFINE(_CSRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, csrr0));
- DEFINE(_CSRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, csrr1));
- DEFINE(_DSRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, dsrr0));
- DEFINE(_DSRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, dsrr1));
-#endif
+ STACK_PT_REGS_OFFSET(MMUCR, mas0);
+ STACK_PT_REGS_OFFSET(MAS1, mas1);
+ STACK_PT_REGS_OFFSET(MAS2, mas2);
+ STACK_PT_REGS_OFFSET(MAS3, mas3);
+ STACK_PT_REGS_OFFSET(MAS6, mas6);
+ STACK_PT_REGS_OFFSET(MAS7, mas7);
+ STACK_PT_REGS_OFFSET(_SRR0, srr0);
+ STACK_PT_REGS_OFFSET(_SRR1, srr1);
+ STACK_PT_REGS_OFFSET(_CSRR0, csrr0);
+ STACK_PT_REGS_OFFSET(_CSRR1, csrr1);
+ STACK_PT_REGS_OFFSET(_DSRR0, dsrr0);
+ STACK_PT_REGS_OFFSET(_DSRR1, dsrr1);
#endif
/* About the CPU features table */
diff --git a/arch/powerpc/kernel/head_booke.h b/arch/powerpc/kernel/head_booke.h
index 87b806e8eded..e5503420b6c6 100644
--- a/arch/powerpc/kernel/head_booke.h
+++ b/arch/powerpc/kernel/head_booke.h
@@ -168,20 +168,18 @@ ALT_FTR_SECTION_END_IFSET(CPU_FTR_EMB_HV)
/* only on e500mc */
#define DBG_STACK_BASE dbgirq_ctx
-#define EXC_LVL_FRAME_OVERHEAD (THREAD_SIZE - INT_FRAME_SIZE - EXC_LVL_SIZE)
-
#ifdef CONFIG_SMP
#define BOOKE_LOAD_EXC_LEVEL_STACK(level) \
mfspr r8,SPRN_PIR; \
slwi r8,r8,2; \
addis r8,r8,level##_STACK_BASE@ha; \
lwz r8,level##_STACK_BASE@l(r8); \
- addi r8,r8,EXC_LVL_FRAME_OVERHEAD;
+ addi r8,r8,THREAD_SIZE - INT_FRAME_SIZE;
#else
#define BOOKE_LOAD_EXC_LEVEL_STACK(level) \
lis r8,level##_STACK_BASE@ha; \
lwz r8,level##_STACK_BASE@l(r8); \
- addi r8,r8,EXC_LVL_FRAME_OVERHEAD;
+ addi r8,r8,THREAD_SIZE - INT_FRAME_SIZE;
#endif
/*
@@ -208,7 +206,7 @@ ALT_FTR_SECTION_END_IFSET(CPU_FTR_EMB_HV)
mtmsr r11; \
mfspr r11,SPRN_SPRG_THREAD; /* if from user, start at top of */\
lwz r11, TASK_STACK - THREAD(r11); /* this thread's kernel stack */\
- addi r11,r11,EXC_LVL_FRAME_OVERHEAD; /* allocate stack frame */\
+ addi r11,r11,THREAD_SIZE - INT_FRAME_SIZE; /* allocate stack frame */\
beq 1f; \
/* COMING FROM USER MODE */ \
stw r9,_CCR(r11); /* save CR */\
@@ -516,24 +514,5 @@ ALT_FTR_SECTION_END_IFSET(CPU_FTR_EMB_HV)
bl kernel_fp_unavailable_exception; \
b interrupt_return
-#else /* __ASSEMBLY__ */
-struct exception_regs {
- unsigned long mas0;
- unsigned long mas1;
- unsigned long mas2;
- unsigned long mas3;
- unsigned long mas6;
- unsigned long mas7;
- unsigned long srr0;
- unsigned long srr1;
- unsigned long csrr0;
- unsigned long csrr1;
- unsigned long dsrr0;
- unsigned long dsrr1;
-};
-
-/* ensure this structure is always sized to a multiple of the stack alignment */
-#define STACK_EXC_LVL_FRAME_SIZE ALIGN(sizeof (struct exception_regs), 16)
-
#endif /* __ASSEMBLY__ */
#endif /* __HEAD_BOOKE_H__ */
--
2.25.0
^ permalink raw reply related
* Re: [PATCH] perf script python: Fix buffer size to report iregs in perf script
From: kajoljain @ 2021-07-07 5:46 UTC (permalink / raw)
To: Arnaldo Carvalho de Melo
Cc: ravi.bangoria, atrajeev, rnsastry, linuxppc-dev, linux-kernel,
linux-perf-users, maddy, Paul A. Clarke, Jiri Olsa
In-Reply-To: <YOSr25+a+r3MF2Ob@kernel.org>
On 7/7/21 12:45 AM, Arnaldo Carvalho de Melo wrote:
> Em Tue, Jul 06, 2021 at 05:26:12PM +0530, kajoljain escreveu:
>>
>>
>> On 6/29/21 12:39 PM, kajoljain wrote:
>>>
>>>
>>> On 6/28/21 8:19 PM, Paul A. Clarke wrote:
>>>> On Mon, Jun 28, 2021 at 11:53:41AM +0530, Kajol Jain wrote:
>>>>> Commit 48a1f565261d ("perf script python: Add more PMU fields
>>>>> to event handler dict") added functionality to report fields like
>>>>> weight, iregs, uregs etc via perf report.
>>>>> That commit predefined buffer size to 512 bytes to print those fields.
>>>>>
>>>>> But incase of powerpc, since we added extended regs support
>>>>> in commits:
>>>>>
>>>>> Commit 068aeea3773a ("perf powerpc: Support exposing Performance Monitor
>>>>> Counter SPRs as part of extended regs")
>>>>> Commit d735599a069f ("powerpc/perf: Add extended regs support for
>>>>> power10 platform")
>>>>>
>>>>> Now iregs can carry more bytes of data and this predefined buffer size
>>>>> can result to data loss in perf script output.
>>>>>
>>>>> Patch resolve this issue by making buffer size dynamic based on number
>>>>> of registers needed to print. It also changed return type for function
>>>>> "regs_map" from int to void, as the return value is not being used by
>>>>> the caller function "set_regs_in_dict".
>>>>>
>>>>> Fixes: 068aeea3773a ("perf powerpc: Support exposing Performance Monitor
>>>>> Counter SPRs as part of extended regs")
>>>>> Signed-off-by: Kajol Jain <kjain@linux.ibm.com>
>>>>> ---
>>>>> .../util/scripting-engines/trace-event-python.c | 17 ++++++++++++-----
>>>>> 1 file changed, 12 insertions(+), 5 deletions(-)
>>>>>
>>>>> diff --git a/tools/perf/util/scripting-engines/trace-event-python.c b/tools/perf/util/scripting-engines/trace-event-python.c
>>>>> index 4e4aa4c97ac5..c8c9706b4643 100644
>>>>> --- a/tools/perf/util/scripting-engines/trace-event-python.c
>>>>> +++ b/tools/perf/util/scripting-engines/trace-event-python.c
>>>> [...]
>>>>> @@ -713,7 +711,16 @@ static void set_regs_in_dict(PyObject *dict,
>>>>> struct evsel *evsel)
>>>>> {
>>>>> struct perf_event_attr *attr = &evsel->core.attr;
>>>>> - char bf[512];
>>>>> +
>>>>> + /*
>>>>> + * Here value 28 is a constant size which can be used to print
>>>>> + * one register value and its corresponds to:
>>>>> + * 16 chars is to specify 64 bit register in hexadecimal.
>>>>> + * 2 chars is for appending "0x" to the hexadecimal value and
>>>>> + * 10 chars is for register name.
>>>>> + */
>>>>> + int size = __sw_hweight64(attr->sample_regs_intr) * 28;
>>>>> + char bf[size];
>>>>
>>>> I propose using a template rather than a magic number here. Something like:
>>>> const char reg_name_tmpl[] = "10 chars ";
>>>> const char reg_value_tmpl[] = "0x0123456789abcdef";
>>>> const int size = __sw_hweight64(attr->sample_regs_intr) +
>>>> sizeof reg_name_tmpl + sizeof reg_value_tmpl;
>>>>
>>>
>>> Hi Paul,
>>> Thanks for reviewing the patch. Yes these are
>>> some standardization we can do by creating macros for different
>>> fields.
>>> The basic idea is, we want to provide significant buffer size
>>> based on number of registers present in sample_regs_intr to accommodate
>>> all data.
>>>
>>
>> Hi Arnaldo/Jiri,
>> Is the approach used in this patch looks fine to you?
>
> Yeah, and the comment you provide right above it explains it, so I think
> that is enough, ok?
>
Hi Arnaldo,
Thanks for reviewing it. As you said added comment already explains
why we are taking size constant as 28, should we skip adding macros part?
Can you pull this patch.
Thanks,
Kajol Jain
> - Arnaldo
>
>> Thanks,
>> Kajol Jain
>>
>>> But before going to optimizing code, Arnaldo/Jiri, is this approach looks good to you?
>>>
>>>> Pardon my ignorance, but is there no separation/whitespace between the name
>>>> and the value?
>>>
>>> This is how we will get data via perf script
>>>
>>> r0:0xc000000000112008
>>> r1:0xc000000023b37920
>>> r2:0xc00000000144c900
>>> r3:0xc0000000bc566120
>>> r4:0xc0000000c5600000
>>> r5:0x2606c6506ca
>>> r6:0xc000000023b378f8
>>> r7:0xfffffd9f93a48f0e
>>> .....
>>>
>>> And is there some significance to 10 characters for the
>>>> register name, or is that a magic number?
>>>
>>> Most of the register name are within 10 characters, basically we are giving this
>>> magic number to make sure we have enough space in buffer to contain all registers
>>> name with colon.
>>>
>>> Thanks,
>>> Kajol Jain
>>>
>>>>
>>>> PC
>>>>
>
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