* [PATCH v2 10/10] powerpc/bpf ppc32: Fix BPF_SUB when imm == 0x80000000
From: Naveen N. Rao @ 2021-10-05 20:25 UTC (permalink / raw)
To: Michael Ellerman, Nicholas Piggin, Jordan Niethe, Daniel Borkmann,
Alexei Starovoitov, Christophe Leroy, Johan Almbladh, Song Liu
Cc: bpf, linuxppc-dev
In-Reply-To: <cover.1633464148.git.naveen.n.rao@linux.vnet.ibm.com>
Special case handling of the smallest 32-bit negative number for BPF_SUB.
Fixes: 51c66ad849a703 ("powerpc/bpf: Implement extended BPF on PPC32")
Signed-off-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com>
---
arch/powerpc/net/bpf_jit_comp32.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/net/bpf_jit_comp32.c b/arch/powerpc/net/bpf_jit_comp32.c
index 68dc8a8231de04..0da31d41d41310 100644
--- a/arch/powerpc/net/bpf_jit_comp32.c
+++ b/arch/powerpc/net/bpf_jit_comp32.c
@@ -357,7 +357,7 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, struct codegen_context *
PPC_LI32(_R0, imm);
EMIT(PPC_RAW_ADDC(dst_reg, dst_reg, _R0));
}
- if (imm >= 0)
+ if (imm >= 0 || (BPF_OP(code) == BPF_SUB && imm == 0x80000000))
EMIT(PPC_RAW_ADDZE(dst_reg_h, dst_reg_h));
else
EMIT(PPC_RAW_ADDME(dst_reg_h, dst_reg_h));
--
2.33.0
^ permalink raw reply related
* [PATCH v2 09/10] powerpc/bpf ppc32: Do not emit zero extend instruction for 64-bit BPF_END
From: Naveen N. Rao @ 2021-10-05 20:25 UTC (permalink / raw)
To: Michael Ellerman, Nicholas Piggin, Jordan Niethe, Daniel Borkmann,
Alexei Starovoitov, Christophe Leroy, Johan Almbladh, Song Liu
Cc: bpf, linuxppc-dev
In-Reply-To: <cover.1633464148.git.naveen.n.rao@linux.vnet.ibm.com>
Suppress emitting zero extend instruction for 64-bit BPF_END_FROM_[L|B]E
operation.
Fixes: 51c66ad849a703 ("powerpc/bpf: Implement extended BPF on PPC32")
Signed-off-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com>
---
arch/powerpc/net/bpf_jit_comp32.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/net/bpf_jit_comp32.c b/arch/powerpc/net/bpf_jit_comp32.c
index 7c65de9ed4fa64..68dc8a8231de04 100644
--- a/arch/powerpc/net/bpf_jit_comp32.c
+++ b/arch/powerpc/net/bpf_jit_comp32.c
@@ -1107,7 +1107,7 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, struct codegen_context *
return -EOPNOTSUPP;
}
if (BPF_CLASS(code) == BPF_ALU && !fp->aux->verifier_zext &&
- !insn_is_zext(&insn[i + 1]))
+ !insn_is_zext(&insn[i + 1]) && !(BPF_OP(code) == BPF_END && imm == 64))
EMIT(PPC_RAW_LI(dst_reg_h, 0));
}
--
2.33.0
^ permalink raw reply related
* [RFC 1/5] ipmi:bt-bmc: Separate out ASPEED specific bits
From: Anton Blanchard @ 2021-10-06 2:12 UTC (permalink / raw)
To: alistair, joel, andrew, clg, mikey, jk; +Cc: linuxppc-dev
Most of the IPMI BT BMC driver is architecture agnostic - it deals with
architected registers and behaviour in the IPMI specification.
Separate out the few ASPEED specific bits into their own functions
so we can use this driver on other architectures.
Signed-off-by: Anton Blanchard <anton@ozlabs.org>
---
drivers/char/ipmi/bt-bmc.c | 26 ++++++++++++++++----------
1 file changed, 16 insertions(+), 10 deletions(-)
diff --git a/drivers/char/ipmi/bt-bmc.c b/drivers/char/ipmi/bt-bmc.c
index 6e3d247b55d1..f85fafc96ef6 100644
--- a/drivers/char/ipmi/bt-bmc.c
+++ b/drivers/char/ipmi/bt-bmc.c
@@ -39,6 +39,7 @@
#define BT_CR2_IRQ_H2B 0x01
#define BT_CR2_IRQ_HBUSY 0x40
#define BT_CR3 0xc
+
#define BT_CTRL 0x10
#define BT_CTRL_B_BUSY 0x80
#define BT_CTRL_H_BUSY 0x40
@@ -372,7 +373,7 @@ static void poll_timer(struct timer_list *t)
add_timer(&bt_bmc->poll_timer);
}
-static irqreturn_t bt_bmc_irq(int irq, void *arg)
+static irqreturn_t aspeed_bt_bmc_irq(int irq, void *arg)
{
struct bt_bmc *bt_bmc = arg;
u32 reg;
@@ -393,7 +394,7 @@ static irqreturn_t bt_bmc_irq(int irq, void *arg)
return IRQ_HANDLED;
}
-static int bt_bmc_config_irq(struct bt_bmc *bt_bmc,
+static int aspeed_bt_bmc_config_irq(struct bt_bmc *bt_bmc,
struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -403,7 +404,7 @@ static int bt_bmc_config_irq(struct bt_bmc *bt_bmc,
if (bt_bmc->irq < 0)
return bt_bmc->irq;
- rc = devm_request_irq(dev, bt_bmc->irq, bt_bmc_irq, IRQF_SHARED,
+ rc = devm_request_irq(dev, bt_bmc->irq, aspeed_bt_bmc_irq, IRQF_SHARED,
DEVICE_NAME, bt_bmc);
if (rc < 0) {
dev_warn(dev, "Unable to request IRQ %d\n", bt_bmc->irq);
@@ -424,6 +425,16 @@ static int bt_bmc_config_irq(struct bt_bmc *bt_bmc,
return rc;
}
+static void aspeed_enable_bt(struct bt_bmc *bt_bmc)
+{
+ regmap_write(bt_bmc->map, bt_bmc->offset + BT_CR0,
+ (BT_IO_BASE << BT_CR0_IO_BASE) |
+ (BT_IRQ << BT_CR0_IRQ) |
+ BT_CR0_EN_CLR_SLV_RDP |
+ BT_CR0_EN_CLR_SLV_WRP |
+ BT_CR0_ENABLE_IBT);
+}
+
static int bt_bmc_probe(struct platform_device *pdev)
{
struct bt_bmc *bt_bmc;
@@ -472,7 +483,7 @@ static int bt_bmc_probe(struct platform_device *pdev)
return rc;
}
- bt_bmc_config_irq(bt_bmc, pdev);
+ aspeed_bt_bmc_config_irq(bt_bmc, pdev);
if (bt_bmc->irq >= 0) {
dev_info(dev, "Using IRQ %d\n", bt_bmc->irq);
@@ -483,12 +494,7 @@ static int bt_bmc_probe(struct platform_device *pdev)
add_timer(&bt_bmc->poll_timer);
}
- regmap_write(bt_bmc->map, bt_bmc->offset + BT_CR0,
- (BT_IO_BASE << BT_CR0_IO_BASE) |
- (BT_IRQ << BT_CR0_IRQ) |
- BT_CR0_EN_CLR_SLV_RDP |
- BT_CR0_EN_CLR_SLV_WRP |
- BT_CR0_ENABLE_IBT);
+ aspeed_enable_bt(bt_bmc);
clr_b_busy(bt_bmc);
--
2.31.1
^ permalink raw reply related
* [RFC 2/5] ipmi:bt-bmc: Prefix ASPEED specific registers with ASPEED_
From: Anton Blanchard @ 2021-10-06 2:12 UTC (permalink / raw)
To: alistair, joel, andrew, clg, mikey, jk; +Cc: linuxppc-dev
In-Reply-To: <20211006021205.2579057-1-anton@ozlabs.org>
Signed-off-by: Anton Blanchard <anton@ozlabs.org>
---
drivers/char/ipmi/bt-bmc.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/char/ipmi/bt-bmc.c b/drivers/char/ipmi/bt-bmc.c
index f85fafc96ef6..2b0fe1255026 100644
--- a/drivers/char/ipmi/bt-bmc.c
+++ b/drivers/char/ipmi/bt-bmc.c
@@ -26,19 +26,19 @@
#define BT_IO_BASE 0xe4
#define BT_IRQ 10
-#define BT_CR0 0x0
+#define ASPEED_BT_CR0 0x0
#define BT_CR0_IO_BASE 16
#define BT_CR0_IRQ 12
#define BT_CR0_EN_CLR_SLV_RDP 0x8
#define BT_CR0_EN_CLR_SLV_WRP 0x4
#define BT_CR0_ENABLE_IBT 0x1
-#define BT_CR1 0x4
+#define ASPEED_BT_CR1 0x4
#define BT_CR1_IRQ_H2B 0x01
#define BT_CR1_IRQ_HBUSY 0x40
-#define BT_CR2 0x8
+#define ASPEED_BT_CR2 0x8
#define BT_CR2_IRQ_H2B 0x01
#define BT_CR2_IRQ_HBUSY 0x40
-#define BT_CR3 0xc
+#define ASPEED_BT_CR3 0xc
#define BT_CTRL 0x10
#define BT_CTRL_B_BUSY 0x80
@@ -379,7 +379,7 @@ static irqreturn_t aspeed_bt_bmc_irq(int irq, void *arg)
u32 reg;
int rc;
- rc = regmap_read(bt_bmc->map, bt_bmc->offset + BT_CR2, ®);
+ rc = regmap_read(bt_bmc->map, bt_bmc->offset + ASPEED_BT_CR2, ®);
if (rc)
return IRQ_NONE;
@@ -388,7 +388,7 @@ static irqreturn_t aspeed_bt_bmc_irq(int irq, void *arg)
return IRQ_NONE;
/* ack pending IRQs */
- regmap_write(bt_bmc->map, bt_bmc->offset + BT_CR2, reg);
+ regmap_write(bt_bmc->map, bt_bmc->offset + ASPEED_BT_CR2, reg);
wake_up(&bt_bmc->queue);
return IRQ_HANDLED;
@@ -418,7 +418,7 @@ static int aspeed_bt_bmc_config_irq(struct bt_bmc *bt_bmc,
* will be cleared (along with B2H) when we can write the next
* message to the BT buffer
*/
- rc = regmap_update_bits(bt_bmc->map, bt_bmc->offset + BT_CR1,
+ rc = regmap_update_bits(bt_bmc->map, bt_bmc->offset + ASPEED_BT_CR1,
(BT_CR1_IRQ_H2B | BT_CR1_IRQ_HBUSY),
(BT_CR1_IRQ_H2B | BT_CR1_IRQ_HBUSY));
@@ -427,7 +427,7 @@ static int aspeed_bt_bmc_config_irq(struct bt_bmc *bt_bmc,
static void aspeed_enable_bt(struct bt_bmc *bt_bmc)
{
- regmap_write(bt_bmc->map, bt_bmc->offset + BT_CR0,
+ regmap_write(bt_bmc->map, bt_bmc->offset + ASPEED_BT_CR0,
(BT_IO_BASE << BT_CR0_IO_BASE) |
(BT_IRQ << BT_CR0_IRQ) |
BT_CR0_EN_CLR_SLV_RDP |
--
2.31.1
^ permalink raw reply related
* [RFC 3/5] ipmi:bt-bmc: Put arch specific function into bt_bmc_ops
From: Anton Blanchard @ 2021-10-06 2:12 UTC (permalink / raw)
To: alistair, joel, andrew, clg, mikey, jk; +Cc: linuxppc-dev
In-Reply-To: <20211006021205.2579057-1-anton@ozlabs.org>
While most of the driver is arch agnostic, setting up and handling
interrupts, and enabling the hardware is not. Create bt_bmc_ops to
handle these functions.
Signed-off-by: Anton Blanchard <anton@ozlabs.org>
---
drivers/char/ipmi/bt-bmc.c | 24 ++++++++++++++++++++----
1 file changed, 20 insertions(+), 4 deletions(-)
diff --git a/drivers/char/ipmi/bt-bmc.c b/drivers/char/ipmi/bt-bmc.c
index 2b0fe1255026..b48e04405ac4 100644
--- a/drivers/char/ipmi/bt-bmc.c
+++ b/drivers/char/ipmi/bt-bmc.c
@@ -17,6 +17,7 @@
#include <linux/regmap.h>
#include <linux/sched.h>
#include <linux/timer.h>
+#include <linux/of_device.h>
/*
* This is a BMC device used to communicate to the host
@@ -435,15 +436,30 @@ static void aspeed_enable_bt(struct bt_bmc *bt_bmc)
BT_CR0_ENABLE_IBT);
}
+struct bt_bmc_ops {
+ int (*config_irq)(struct bt_bmc *bt_bmc, struct platform_device *pdev);
+ void (*enable_bt)(struct bt_bmc *bt_bmc);
+};
+
+static const struct bt_bmc_ops aspeed_bt_bmc_ops = {
+ .config_irq = aspeed_bt_bmc_config_irq,
+ .enable_bt = aspeed_enable_bt,
+};
+
static int bt_bmc_probe(struct platform_device *pdev)
{
struct bt_bmc *bt_bmc;
struct device *dev;
int rc;
+ const struct bt_bmc_ops *ops;
dev = &pdev->dev;
dev_info(dev, "Found bt bmc device\n");
+ ops = of_device_get_match_data(&pdev->dev);
+ if (!ops)
+ return -ENODEV;
+
bt_bmc = devm_kzalloc(dev, sizeof(*bt_bmc), GFP_KERNEL);
if (!bt_bmc)
return -ENOMEM;
@@ -483,7 +499,7 @@ static int bt_bmc_probe(struct platform_device *pdev)
return rc;
}
- aspeed_bt_bmc_config_irq(bt_bmc, pdev);
+ ops->config_irq(bt_bmc, pdev);
if (bt_bmc->irq >= 0) {
dev_info(dev, "Using IRQ %d\n", bt_bmc->irq);
@@ -494,7 +510,7 @@ static int bt_bmc_probe(struct platform_device *pdev)
add_timer(&bt_bmc->poll_timer);
}
- aspeed_enable_bt(bt_bmc);
+ ops->enable_bt(bt_bmc);
clr_b_busy(bt_bmc);
@@ -512,8 +528,8 @@ static int bt_bmc_remove(struct platform_device *pdev)
}
static const struct of_device_id bt_bmc_match[] = {
- { .compatible = "aspeed,ast2400-ibt-bmc" },
- { .compatible = "aspeed,ast2500-ibt-bmc" },
+ { .compatible = "aspeed,ast2400-ibt-bmc", .data = &aspeed_bt_bmc_ops },
+ { .compatible = "aspeed,ast2500-ibt-bmc", .data = &aspeed_bt_bmc_ops },
{ },
};
--
2.31.1
^ permalink raw reply related
* [RFC 4/5] ipmi:bt-bmc: No longer ASPEED specific
From: Anton Blanchard @ 2021-10-06 2:12 UTC (permalink / raw)
To: alistair, joel, andrew, clg, mikey, jk; +Cc: linuxppc-dev
In-Reply-To: <20211006021205.2579057-1-anton@ozlabs.org>
The driver is no longer specific to ASPEED, so rename the config option
and remove the dependency on ARCH_ASPEED.
Signed-off-by: Anton Blanchard <anton@ozlabs.org>
---
.../bindings/ipmi/{aspeed,ast2400-ibt-bmc.txt => ibt-bmc.txt} | 2 +-
arch/arm/configs/aspeed_g4_defconfig | 2 +-
arch/arm/configs/aspeed_g5_defconfig | 2 +-
arch/arm/configs/multi_v5_defconfig | 2 +-
arch/arm/configs/multi_v7_defconfig | 2 +-
drivers/char/ipmi/Kconfig | 2 +-
drivers/char/ipmi/Makefile | 2 +-
7 files changed, 7 insertions(+), 7 deletions(-)
rename Documentation/devicetree/bindings/ipmi/{aspeed,ast2400-ibt-bmc.txt => ibt-bmc.txt} (93%)
diff --git a/Documentation/devicetree/bindings/ipmi/aspeed,ast2400-ibt-bmc.txt b/Documentation/devicetree/bindings/ipmi/ibt-bmc.txt
similarity index 93%
rename from Documentation/devicetree/bindings/ipmi/aspeed,ast2400-ibt-bmc.txt
rename to Documentation/devicetree/bindings/ipmi/ibt-bmc.txt
index 028268fd99ee..78ee716a950e 100644
--- a/Documentation/devicetree/bindings/ipmi/aspeed,ast2400-ibt-bmc.txt
+++ b/Documentation/devicetree/bindings/ipmi/ibt-bmc.txt
@@ -1,4 +1,4 @@
-* Aspeed BT (Block Transfer) IPMI interface
+* BT (Block Transfer) IPMI interface
The Aspeed SOCs (AST2400 and AST2500) are commonly used as BMCs
(BaseBoard Management Controllers) and the BT interface can be used to
diff --git a/arch/arm/configs/aspeed_g4_defconfig b/arch/arm/configs/aspeed_g4_defconfig
index acaafa351d08..51696ba49c80 100644
--- a/arch/arm/configs/aspeed_g4_defconfig
+++ b/arch/arm/configs/aspeed_g4_defconfig
@@ -124,7 +124,7 @@ CONFIG_SERIAL_8250_ASPEED_VUART=y
CONFIG_SERIAL_8250_SHARE_IRQ=y
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_ASPEED_KCS_IPMI_BMC=y
-CONFIG_ASPEED_BT_IPMI_BMC=y
+CONFIG_BT_IPMI_BMC=y
CONFIG_HW_RANDOM_TIMERIOMEM=y
# CONFIG_I2C_COMPAT is not set
CONFIG_I2C_CHARDEV=y
diff --git a/arch/arm/configs/aspeed_g5_defconfig b/arch/arm/configs/aspeed_g5_defconfig
index 480dbbb4ff91..758dac62f34f 100644
--- a/arch/arm/configs/aspeed_g5_defconfig
+++ b/arch/arm/configs/aspeed_g5_defconfig
@@ -141,7 +141,7 @@ CONFIG_SERIAL_8250_DW=y
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_ASPEED_KCS_IPMI_BMC=y
CONFIG_IPMI_KCS_BMC_SERIO=y
-CONFIG_ASPEED_BT_IPMI_BMC=y
+CONFIG_BT_IPMI_BMC=y
CONFIG_HW_RANDOM_TIMERIOMEM=y
# CONFIG_I2C_COMPAT is not set
CONFIG_I2C_CHARDEV=y
diff --git a/arch/arm/configs/multi_v5_defconfig b/arch/arm/configs/multi_v5_defconfig
index 80a3ae02d759..f3ed5da74dfa 100644
--- a/arch/arm/configs/multi_v5_defconfig
+++ b/arch/arm/configs/multi_v5_defconfig
@@ -150,7 +150,7 @@ CONFIG_SERIAL_ATMEL_TTYAT=y
CONFIG_SERIAL_IMX=y
CONFIG_SERIAL_IMX_CONSOLE=y
CONFIG_ASPEED_KCS_IPMI_BMC=m
-CONFIG_ASPEED_BT_IPMI_BMC=m
+CONFIG_BT_IPMI_BMC=m
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_TIMERIOMEM=m
# CONFIG_I2C_COMPAT is not set
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index ba67c4717dcc..03e97d95c251 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -384,7 +384,7 @@ CONFIG_SERIAL_OWL_CONSOLE=y
CONFIG_SERIAL_DEV_BUS=y
CONFIG_VIRTIO_CONSOLE=y
CONFIG_ASPEED_KCS_IPMI_BMC=m
-CONFIG_ASPEED_BT_IPMI_BMC=m
+CONFIG_BT_IPMI_BMC=m
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_ST=y
CONFIG_TCG_TPM=m
diff --git a/drivers/char/ipmi/Kconfig b/drivers/char/ipmi/Kconfig
index 249b31197eea..8b2f0f675e5f 100644
--- a/drivers/char/ipmi/Kconfig
+++ b/drivers/char/ipmi/Kconfig
@@ -151,7 +151,7 @@ config IPMI_KCS_BMC_SERIO
This support is also available as a module. The module will be
called kcs_bmc_serio.
-config ASPEED_BT_IPMI_BMC
+config BT_IPMI_BMC
depends on ARCH_ASPEED || COMPILE_TEST
depends on REGMAP && REGMAP_MMIO && MFD_SYSCON
tristate "BT IPMI bmc driver"
diff --git a/drivers/char/ipmi/Makefile b/drivers/char/ipmi/Makefile
index 84f47d18007f..75c71cbd568b 100644
--- a/drivers/char/ipmi/Makefile
+++ b/drivers/char/ipmi/Makefile
@@ -25,7 +25,7 @@ obj-$(CONFIG_IPMI_POWEROFF) += ipmi_poweroff.o
obj-$(CONFIG_IPMI_KCS_BMC) += kcs_bmc.o
obj-$(CONFIG_IPMI_KCS_BMC_SERIO) += kcs_bmc_serio.o
obj-$(CONFIG_IPMI_KCS_BMC_CDEV_IPMI) += kcs_bmc_cdev_ipmi.o
-obj-$(CONFIG_ASPEED_BT_IPMI_BMC) += bt-bmc.o
+obj-$(CONFIG_BT_IPMI_BMC) += bt-bmc.o
obj-$(CONFIG_ASPEED_KCS_IPMI_BMC) += kcs_bmc_aspeed.o
obj-$(CONFIG_NPCM7XX_KCS_IPMI_BMC) += kcs_bmc_npcm7xx.o
obj-$(CONFIG_IPMB_DEVICE_INTERFACE) += ipmb_dev_int.o
--
2.31.1
^ permalink raw reply related
* [RFC 5/5] ipmi:bt-bmc: Add Microwatt
From: Anton Blanchard @ 2021-10-06 2:12 UTC (permalink / raw)
To: alistair, joel, andrew, clg, mikey, jk; +Cc: linuxppc-dev
In-Reply-To: <20211006021205.2579057-1-anton@ozlabs.org>
This adds the Microwatt specific bits, including interrupt support.
Signed-off-by: Anton Blanchard <anton@ozlabs.org>
---
.../devicetree/bindings/ipmi/ibt-bmc.txt | 1 +
drivers/char/ipmi/Kconfig | 8 ++-
drivers/char/ipmi/bt-bmc.c | 69 +++++++++++++++++++
3 files changed, 75 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/ipmi/ibt-bmc.txt b/Documentation/devicetree/bindings/ipmi/ibt-bmc.txt
index 78ee716a950e..1b661daf0193 100644
--- a/Documentation/devicetree/bindings/ipmi/ibt-bmc.txt
+++ b/Documentation/devicetree/bindings/ipmi/ibt-bmc.txt
@@ -9,6 +9,7 @@ Required properties:
- compatible : should be one of
"aspeed,ast2400-ibt-bmc"
"aspeed,ast2500-ibt-bmc"
+ "ibm,microwatt-ibt-bmc"
- reg: physical address and size of the registers
Optional properties:
diff --git a/drivers/char/ipmi/Kconfig b/drivers/char/ipmi/Kconfig
index 8b2f0f675e5f..079302f4eef2 100644
--- a/drivers/char/ipmi/Kconfig
+++ b/drivers/char/ipmi/Kconfig
@@ -152,13 +152,15 @@ config IPMI_KCS_BMC_SERIO
called kcs_bmc_serio.
config BT_IPMI_BMC
- depends on ARCH_ASPEED || COMPILE_TEST
+ depends on ARCH_ASPEED || PPC_MICROWATT || COMPILE_TEST
depends on REGMAP && REGMAP_MMIO && MFD_SYSCON
tristate "BT IPMI bmc driver"
help
Provides a driver for the BT (Block Transfer) IPMI interface
- found on Aspeed SOCs (AST2400 and AST2500). The driver
- implements the BMC side of the BT interface.
+ found on Aspeed SOCs (AST2400 and AST2500) as well as the OpenPOWER
+ LPC peripheral macro at
+ <https://github.com/OpenPOWERFoundation/lpcperipheral>
+ The driver implements the BMC side of the BT interface.
config IPMB_DEVICE_INTERFACE
tristate 'IPMB Interface handler'
diff --git a/drivers/char/ipmi/bt-bmc.c b/drivers/char/ipmi/bt-bmc.c
index b48e04405ac4..24327b57c60b 100644
--- a/drivers/char/ipmi/bt-bmc.c
+++ b/drivers/char/ipmi/bt-bmc.c
@@ -41,6 +41,11 @@
#define BT_CR2_IRQ_HBUSY 0x40
#define ASPEED_BT_CR3 0xc
+#define MICROWATT_IRQ_MASK 0x0
+#define MICROWATT_IRQ_STATUS 0x4
+#define IRQ_HOST_TO_BMC_ATTN 0x1
+#define IRQ_HOST_NOT_BUSY 0x2
+
#define BT_CTRL 0x10
#define BT_CTRL_B_BUSY 0x80
#define BT_CTRL_H_BUSY 0x40
@@ -395,6 +400,27 @@ static irqreturn_t aspeed_bt_bmc_irq(int irq, void *arg)
return IRQ_HANDLED;
}
+static irqreturn_t microwatt_bt_bmc_irq(int irq, void *arg)
+{
+ struct bt_bmc *bt_bmc = arg;
+ u32 reg;
+ int rc;
+
+ rc = regmap_read(bt_bmc->map, bt_bmc->offset + MICROWATT_IRQ_STATUS, ®);
+ if (rc)
+ return IRQ_NONE;
+
+ /* Interrupt wasn't something we knew about */
+ if (!(reg & (IRQ_HOST_TO_BMC_ATTN | IRQ_HOST_NOT_BUSY)))
+ return IRQ_NONE;
+
+ /* ack all pending IRQs */
+ regmap_write(bt_bmc->map, bt_bmc->offset + MICROWATT_IRQ_STATUS, 0);
+
+ wake_up(&bt_bmc->queue);
+ return IRQ_HANDLED;
+}
+
static int aspeed_bt_bmc_config_irq(struct bt_bmc *bt_bmc,
struct platform_device *pdev)
{
@@ -446,6 +472,48 @@ static const struct bt_bmc_ops aspeed_bt_bmc_ops = {
.enable_bt = aspeed_enable_bt,
};
+static int microwatt_bt_bmc_config_irq(struct bt_bmc *bt_bmc,
+ struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ int rc;
+
+ bt_bmc->irq = platform_get_irq_optional(pdev, 0);
+ if (bt_bmc->irq < 0)
+ return bt_bmc->irq;
+
+ rc = devm_request_irq(dev, bt_bmc->irq, microwatt_bt_bmc_irq, IRQF_SHARED,
+ DEVICE_NAME, bt_bmc);
+ if (rc < 0) {
+ dev_warn(dev, "Unable to request IRQ %d\n", bt_bmc->irq);
+ bt_bmc->irq = rc;
+ return rc;
+ }
+
+ /*
+ * Configure the hardware to give us an interrupt whenever the H2B
+ * bit is set or the HBUSY bit is cleared.
+ *
+ * H2B will be asserted when the bmc has data for us; HBUSY
+ * will be cleared (along with B2H) when we can write the next
+ * message to the BT buffer
+ */
+ rc = regmap_update_bits(bt_bmc->map, bt_bmc->offset + MICROWATT_IRQ_MASK,
+ (IRQ_HOST_TO_BMC_ATTN | IRQ_HOST_NOT_BUSY),
+ (IRQ_HOST_TO_BMC_ATTN | IRQ_HOST_NOT_BUSY));
+
+ return rc;
+}
+
+static void microwatt_enable_bt(struct bt_bmc *bt_bmc)
+{
+}
+
+static const struct bt_bmc_ops microwatt_bt_bmc_ops = {
+ .config_irq = microwatt_bt_bmc_config_irq,
+ .enable_bt = microwatt_enable_bt,
+};
+
static int bt_bmc_probe(struct platform_device *pdev)
{
struct bt_bmc *bt_bmc;
@@ -530,6 +598,7 @@ static int bt_bmc_remove(struct platform_device *pdev)
static const struct of_device_id bt_bmc_match[] = {
{ .compatible = "aspeed,ast2400-ibt-bmc", .data = &aspeed_bt_bmc_ops },
{ .compatible = "aspeed,ast2500-ibt-bmc", .data = &aspeed_bt_bmc_ops },
+ { .compatible = "ibm,microwatt-ibt-bmc", .data = µwatt_bt_bmc_ops },
{ },
};
--
2.31.1
^ permalink raw reply related
* Re: [RFC 5/5] ipmi:bt-bmc: Add Microwatt
From: Joel Stanley @ 2021-10-06 2:35 UTC (permalink / raw)
To: Anton Blanchard
Cc: Michael Neuling, Andrew Jeffery, Alistair Popple,
Cédric Le Goater, Jeremy Kerr, linuxppc-dev
In-Reply-To: <20211006021205.2579057-5-anton@ozlabs.org>
Hi Anton,
On Wed, 6 Oct 2021 at 02:12, Anton Blanchard <anton@ozlabs.org> wrote:
>
> This adds the Microwatt specific bits, including interrupt support.
The series looks good.
I've got a couple of patches on the ipmi list that this will conflict with:
https://sourceforge.net/p/openipmi/mailman/message/37345391/
https://lore.kernel.org/all/20210903015314.177987-1-joel@jms.id.au/
If there's no feedback from others I suggest basing your series on top
of those, and sending them to Corey on the ipmi list to merge.
Cheers,
Joel
>
> Signed-off-by: Anton Blanchard <anton@ozlabs.org>
> ---
> .../devicetree/bindings/ipmi/ibt-bmc.txt | 1 +
> drivers/char/ipmi/Kconfig | 8 ++-
> drivers/char/ipmi/bt-bmc.c | 69 +++++++++++++++++++
> 3 files changed, 75 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/ipmi/ibt-bmc.txt b/Documentation/devicetree/bindings/ipmi/ibt-bmc.txt
> index 78ee716a950e..1b661daf0193 100644
> --- a/Documentation/devicetree/bindings/ipmi/ibt-bmc.txt
> +++ b/Documentation/devicetree/bindings/ipmi/ibt-bmc.txt
> @@ -9,6 +9,7 @@ Required properties:
> - compatible : should be one of
> "aspeed,ast2400-ibt-bmc"
> "aspeed,ast2500-ibt-bmc"
> + "ibm,microwatt-ibt-bmc"
> - reg: physical address and size of the registers
>
> Optional properties:
> diff --git a/drivers/char/ipmi/Kconfig b/drivers/char/ipmi/Kconfig
> index 8b2f0f675e5f..079302f4eef2 100644
> --- a/drivers/char/ipmi/Kconfig
> +++ b/drivers/char/ipmi/Kconfig
> @@ -152,13 +152,15 @@ config IPMI_KCS_BMC_SERIO
> called kcs_bmc_serio.
>
> config BT_IPMI_BMC
> - depends on ARCH_ASPEED || COMPILE_TEST
> + depends on ARCH_ASPEED || PPC_MICROWATT || COMPILE_TEST
> depends on REGMAP && REGMAP_MMIO && MFD_SYSCON
> tristate "BT IPMI bmc driver"
> help
> Provides a driver for the BT (Block Transfer) IPMI interface
> - found on Aspeed SOCs (AST2400 and AST2500). The driver
> - implements the BMC side of the BT interface.
> + found on Aspeed SOCs (AST2400 and AST2500) as well as the OpenPOWER
> + LPC peripheral macro at
> + <https://github.com/OpenPOWERFoundation/lpcperipheral>
> + The driver implements the BMC side of the BT interface.
>
> config IPMB_DEVICE_INTERFACE
> tristate 'IPMB Interface handler'
> diff --git a/drivers/char/ipmi/bt-bmc.c b/drivers/char/ipmi/bt-bmc.c
> index b48e04405ac4..24327b57c60b 100644
> --- a/drivers/char/ipmi/bt-bmc.c
> +++ b/drivers/char/ipmi/bt-bmc.c
> @@ -41,6 +41,11 @@
> #define BT_CR2_IRQ_HBUSY 0x40
> #define ASPEED_BT_CR3 0xc
>
> +#define MICROWATT_IRQ_MASK 0x0
> +#define MICROWATT_IRQ_STATUS 0x4
> +#define IRQ_HOST_TO_BMC_ATTN 0x1
> +#define IRQ_HOST_NOT_BUSY 0x2
> +
> #define BT_CTRL 0x10
> #define BT_CTRL_B_BUSY 0x80
> #define BT_CTRL_H_BUSY 0x40
> @@ -395,6 +400,27 @@ static irqreturn_t aspeed_bt_bmc_irq(int irq, void *arg)
> return IRQ_HANDLED;
> }
>
> +static irqreturn_t microwatt_bt_bmc_irq(int irq, void *arg)
> +{
> + struct bt_bmc *bt_bmc = arg;
> + u32 reg;
> + int rc;
> +
> + rc = regmap_read(bt_bmc->map, bt_bmc->offset + MICROWATT_IRQ_STATUS, ®);
> + if (rc)
> + return IRQ_NONE;
> +
> + /* Interrupt wasn't something we knew about */
> + if (!(reg & (IRQ_HOST_TO_BMC_ATTN | IRQ_HOST_NOT_BUSY)))
> + return IRQ_NONE;
> +
> + /* ack all pending IRQs */
> + regmap_write(bt_bmc->map, bt_bmc->offset + MICROWATT_IRQ_STATUS, 0);
> +
> + wake_up(&bt_bmc->queue);
> + return IRQ_HANDLED;
> +}
> +
> static int aspeed_bt_bmc_config_irq(struct bt_bmc *bt_bmc,
> struct platform_device *pdev)
> {
> @@ -446,6 +472,48 @@ static const struct bt_bmc_ops aspeed_bt_bmc_ops = {
> .enable_bt = aspeed_enable_bt,
> };
>
> +static int microwatt_bt_bmc_config_irq(struct bt_bmc *bt_bmc,
> + struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + int rc;
> +
> + bt_bmc->irq = platform_get_irq_optional(pdev, 0);
> + if (bt_bmc->irq < 0)
> + return bt_bmc->irq;
> +
> + rc = devm_request_irq(dev, bt_bmc->irq, microwatt_bt_bmc_irq, IRQF_SHARED,
> + DEVICE_NAME, bt_bmc);
> + if (rc < 0) {
> + dev_warn(dev, "Unable to request IRQ %d\n", bt_bmc->irq);
> + bt_bmc->irq = rc;
> + return rc;
> + }
> +
> + /*
> + * Configure the hardware to give us an interrupt whenever the H2B
> + * bit is set or the HBUSY bit is cleared.
> + *
> + * H2B will be asserted when the bmc has data for us; HBUSY
> + * will be cleared (along with B2H) when we can write the next
> + * message to the BT buffer
> + */
> + rc = regmap_update_bits(bt_bmc->map, bt_bmc->offset + MICROWATT_IRQ_MASK,
> + (IRQ_HOST_TO_BMC_ATTN | IRQ_HOST_NOT_BUSY),
> + (IRQ_HOST_TO_BMC_ATTN | IRQ_HOST_NOT_BUSY));
> +
> + return rc;
> +}
> +
> +static void microwatt_enable_bt(struct bt_bmc *bt_bmc)
> +{
> +}
> +
> +static const struct bt_bmc_ops microwatt_bt_bmc_ops = {
> + .config_irq = microwatt_bt_bmc_config_irq,
> + .enable_bt = microwatt_enable_bt,
> +};
> +
> static int bt_bmc_probe(struct platform_device *pdev)
> {
> struct bt_bmc *bt_bmc;
> @@ -530,6 +598,7 @@ static int bt_bmc_remove(struct platform_device *pdev)
> static const struct of_device_id bt_bmc_match[] = {
> { .compatible = "aspeed,ast2400-ibt-bmc", .data = &aspeed_bt_bmc_ops },
> { .compatible = "aspeed,ast2500-ibt-bmc", .data = &aspeed_bt_bmc_ops },
> + { .compatible = "ibm,microwatt-ibt-bmc", .data = µwatt_bt_bmc_ops },
> { },
> };
>
> --
> 2.31.1
>
^ permalink raw reply
* Re: [RFC 5/5] ipmi:bt-bmc: Add Microwatt
From: Anton Blanchard @ 2021-10-06 3:06 UTC (permalink / raw)
To: Joel Stanley
Cc: Michael Neuling, Andrew Jeffery, Alistair Popple,
Cédric Le Goater, Jeremy Kerr, linuxppc-dev
In-Reply-To: <CACPK8XetfycURqsznmA1dMZ5h5=uJb6xrzg-ihsZH9Xft=phdA@mail.gmail.com>
Hi Joel,
> The series looks good.
>
> I've got a couple of patches on the ipmi list that this will conflict
> with:
>
> https://sourceforge.net/p/openipmi/mailman/message/37345391/
> https://lore.kernel.org/all/20210903015314.177987-1-joel@jms.id.au/
>
> If there's no feedback from others I suggest basing your series on top
> of those, and sending them to Corey on the ipmi list to merge.
Looks good, will do.
Thanks,
Anton
> Cheers,
>
> Joel
>
> >
> > Signed-off-by: Anton Blanchard <anton@ozlabs.org>
> > ---
> > .../devicetree/bindings/ipmi/ibt-bmc.txt | 1 +
> > drivers/char/ipmi/Kconfig | 8 ++-
> > drivers/char/ipmi/bt-bmc.c | 69
> > +++++++++++++++++++ 3 files changed, 75 insertions(+), 3
> > deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/ipmi/ibt-bmc.txt
> > b/Documentation/devicetree/bindings/ipmi/ibt-bmc.txt index
> > 78ee716a950e..1b661daf0193 100644 ---
> > a/Documentation/devicetree/bindings/ipmi/ibt-bmc.txt +++
> > b/Documentation/devicetree/bindings/ipmi/ibt-bmc.txt @@ -9,6 +9,7
> > @@ Required properties:
> > - compatible : should be one of
> > "aspeed,ast2400-ibt-bmc"
> > "aspeed,ast2500-ibt-bmc"
> > + "ibm,microwatt-ibt-bmc"
> > - reg: physical address and size of the registers
> >
> > Optional properties:
> > diff --git a/drivers/char/ipmi/Kconfig b/drivers/char/ipmi/Kconfig
> > index 8b2f0f675e5f..079302f4eef2 100644
> > --- a/drivers/char/ipmi/Kconfig
> > +++ b/drivers/char/ipmi/Kconfig
> > @@ -152,13 +152,15 @@ config IPMI_KCS_BMC_SERIO
> > called kcs_bmc_serio.
> >
> > config BT_IPMI_BMC
> > - depends on ARCH_ASPEED || COMPILE_TEST
> > + depends on ARCH_ASPEED || PPC_MICROWATT || COMPILE_TEST
> > depends on REGMAP && REGMAP_MMIO && MFD_SYSCON
> > tristate "BT IPMI bmc driver"
> > help
> > Provides a driver for the BT (Block Transfer) IPMI
> > interface
> > - found on Aspeed SOCs (AST2400 and AST2500). The driver
> > - implements the BMC side of the BT interface.
> > + found on Aspeed SOCs (AST2400 and AST2500) as well as the
> > OpenPOWER
> > + LPC peripheral macro at
> > + <https://github.com/OpenPOWERFoundation/lpcperipheral>
> > + The driver implements the BMC side of the BT interface.
> >
> > config IPMB_DEVICE_INTERFACE
> > tristate 'IPMB Interface handler'
> > diff --git a/drivers/char/ipmi/bt-bmc.c b/drivers/char/ipmi/bt-bmc.c
> > index b48e04405ac4..24327b57c60b 100644
> > --- a/drivers/char/ipmi/bt-bmc.c
> > +++ b/drivers/char/ipmi/bt-bmc.c
> > @@ -41,6 +41,11 @@
> > #define BT_CR2_IRQ_HBUSY 0x40
> > #define ASPEED_BT_CR3 0xc
> >
> > +#define MICROWATT_IRQ_MASK 0x0
> > +#define MICROWATT_IRQ_STATUS 0x4
> > +#define IRQ_HOST_TO_BMC_ATTN 0x1
> > +#define IRQ_HOST_NOT_BUSY 0x2
> > +
> > #define BT_CTRL 0x10
> > #define BT_CTRL_B_BUSY 0x80
> > #define BT_CTRL_H_BUSY 0x40
> > @@ -395,6 +400,27 @@ static irqreturn_t aspeed_bt_bmc_irq(int irq,
> > void *arg) return IRQ_HANDLED;
> > }
> >
> > +static irqreturn_t microwatt_bt_bmc_irq(int irq, void *arg)
> > +{
> > + struct bt_bmc *bt_bmc = arg;
> > + u32 reg;
> > + int rc;
> > +
> > + rc = regmap_read(bt_bmc->map, bt_bmc->offset +
> > MICROWATT_IRQ_STATUS, ®);
> > + if (rc)
> > + return IRQ_NONE;
> > +
> > + /* Interrupt wasn't something we knew about */
> > + if (!(reg & (IRQ_HOST_TO_BMC_ATTN | IRQ_HOST_NOT_BUSY)))
> > + return IRQ_NONE;
> > +
> > + /* ack all pending IRQs */
> > + regmap_write(bt_bmc->map, bt_bmc->offset +
> > MICROWATT_IRQ_STATUS, 0); +
> > + wake_up(&bt_bmc->queue);
> > + return IRQ_HANDLED;
> > +}
> > +
> > static int aspeed_bt_bmc_config_irq(struct bt_bmc *bt_bmc,
> > struct platform_device *pdev)
> > {
> > @@ -446,6 +472,48 @@ static const struct bt_bmc_ops
> > aspeed_bt_bmc_ops = { .enable_bt = aspeed_enable_bt,
> > };
> >
> > +static int microwatt_bt_bmc_config_irq(struct bt_bmc *bt_bmc,
> > + struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + int rc;
> > +
> > + bt_bmc->irq = platform_get_irq_optional(pdev, 0);
> > + if (bt_bmc->irq < 0)
> > + return bt_bmc->irq;
> > +
> > + rc = devm_request_irq(dev, bt_bmc->irq,
> > microwatt_bt_bmc_irq, IRQF_SHARED,
> > + DEVICE_NAME, bt_bmc);
> > + if (rc < 0) {
> > + dev_warn(dev, "Unable to request IRQ %d\n",
> > bt_bmc->irq);
> > + bt_bmc->irq = rc;
> > + return rc;
> > + }
> > +
> > + /*
> > + * Configure the hardware to give us an interrupt whenever
> > the H2B
> > + * bit is set or the HBUSY bit is cleared.
> > + *
> > + * H2B will be asserted when the bmc has data for us; HBUSY
> > + * will be cleared (along with B2H) when we can write the
> > next
> > + * message to the BT buffer
> > + */
> > + rc = regmap_update_bits(bt_bmc->map, bt_bmc->offset +
> > MICROWATT_IRQ_MASK,
> > + (IRQ_HOST_TO_BMC_ATTN |
> > IRQ_HOST_NOT_BUSY),
> > + (IRQ_HOST_TO_BMC_ATTN |
> > IRQ_HOST_NOT_BUSY)); +
> > + return rc;
> > +}
> > +
> > +static void microwatt_enable_bt(struct bt_bmc *bt_bmc)
> > +{
> > +}
> > +
> > +static const struct bt_bmc_ops microwatt_bt_bmc_ops = {
> > + .config_irq = microwatt_bt_bmc_config_irq,
> > + .enable_bt = microwatt_enable_bt,
> > +};
> > +
> > static int bt_bmc_probe(struct platform_device *pdev)
> > {
> > struct bt_bmc *bt_bmc;
> > @@ -530,6 +598,7 @@ static int bt_bmc_remove(struct platform_device
> > *pdev) static const struct of_device_id bt_bmc_match[] = {
> > { .compatible = "aspeed,ast2400-ibt-bmc", .data =
> > &aspeed_bt_bmc_ops }, { .compatible = "aspeed,ast2500-ibt-bmc",
> > .data = &aspeed_bt_bmc_ops },
> > + { .compatible = "ibm,microwatt-ibt-bmc", .data =
> > µwatt_bt_bmc_ops }, { },
> > };
> >
> > --
> > 2.31.1
> >
>
^ permalink raw reply
* [PATCH kernel v2] powerps/pseries/dma: Add support for 2M IOMMU page size
From: Alexey Kardashevskiy @ 2021-10-06 4:47 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Alexey Kardashevskiy, Frederic Barrat, Leonardo Bras
The upcoming PAPR spec adds a 2M page size, bit 23 right after 16G page
size in the "ibm,query-pe-dma-window" call.
This adds support for the new page size. Since the new page size is out
of sorted order, this changes the loop to not assume that shift[] is
sorted.
This has now been tested and is known to work on a pre-release version
of phyp.
Reviewed-by: Leonardo Bras <leobras.c@gmail.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
Changes:
v2:
* adjusted the commit log about testing
---
arch/powerpc/platforms/pseries/iommu.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/platforms/pseries/iommu.c b/arch/powerpc/platforms/pseries/iommu.c
index dab5c56ffd0e..269f61d519c2 100644
--- a/arch/powerpc/platforms/pseries/iommu.c
+++ b/arch/powerpc/platforms/pseries/iommu.c
@@ -1159,14 +1159,15 @@ static void reset_dma_window(struct pci_dev *dev, struct device_node *par_dn)
/* Return largest page shift based on "IO Page Sizes" output of ibm,query-pe-dma-window. */
static int iommu_get_page_shift(u32 query_page_size)
{
- /* Supported IO page-sizes according to LoPAR */
+ /* Supported IO page-sizes according to LoPAR, note that 2M is out of order */
const int shift[] = {
__builtin_ctzll(SZ_4K), __builtin_ctzll(SZ_64K), __builtin_ctzll(SZ_16M),
__builtin_ctzll(SZ_32M), __builtin_ctzll(SZ_64M), __builtin_ctzll(SZ_128M),
- __builtin_ctzll(SZ_256M), __builtin_ctzll(SZ_16G)
+ __builtin_ctzll(SZ_256M), __builtin_ctzll(SZ_16G), __builtin_ctzll(SZ_2M)
};
int i = ARRAY_SIZE(shift) - 1;
+ int ret = 0;
/*
* On LoPAR, ibm,query-pe-dma-window outputs "IO Page Sizes" using a bit field:
@@ -1176,11 +1177,10 @@ static int iommu_get_page_shift(u32 query_page_size)
*/
for (; i >= 0 ; i--) {
if (query_page_size & (1 << i))
- return shift[i];
+ ret = max(ret, shift[i]);
}
- /* No valid page size found. */
- return 0;
+ return ret;
}
static struct property *ddw_property_create(const char *propname, u32 liobn, u64 dma_addr,
--
2.30.2
^ permalink raw reply related
* Re: [PATCH v2 01/10] powerpc/lib: Add helper to check if offset is within conditional branch range
From: Christophe Leroy @ 2021-10-06 4:50 UTC (permalink / raw)
To: Naveen N. Rao, Michael Ellerman, Nicholas Piggin, Jordan Niethe,
Daniel Borkmann, Alexei Starovoitov, Johan Almbladh, Song Liu
Cc: bpf, linuxppc-dev
In-Reply-To: <442b69a34ced32ca346a0d9a855f3f6cfdbbbd41.1633464148.git.naveen.n.rao@linux.vnet.ibm.com>
Le 05/10/2021 à 22:25, Naveen N. Rao a écrit :
> Add a helper to check if a given offset is within the branch range for a
> powerpc conditional branch instruction, and update some sites to use the
> new helper.
>
> Acked-by: Song Liu <songliubraving@fb.com>
> Signed-off-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
> ---
> Changelog:
> - Change 0x7FFF to 0x7fff, per Christophe
>
>
> arch/powerpc/include/asm/code-patching.h | 1 +
> arch/powerpc/lib/code-patching.c | 7 ++++++-
> arch/powerpc/net/bpf_jit.h | 7 +------
> 3 files changed, 8 insertions(+), 7 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/code-patching.h b/arch/powerpc/include/asm/code-patching.h
> index a95f63788c6b14..4ba834599c4d4c 100644
> --- a/arch/powerpc/include/asm/code-patching.h
> +++ b/arch/powerpc/include/asm/code-patching.h
> @@ -23,6 +23,7 @@
> #define BRANCH_ABSOLUTE 0x2
>
> bool is_offset_in_branch_range(long offset);
> +bool is_offset_in_cond_branch_range(long offset);
> int create_branch(struct ppc_inst *instr, const u32 *addr,
> unsigned long target, int flags);
> int create_cond_branch(struct ppc_inst *instr, const u32 *addr,
> diff --git a/arch/powerpc/lib/code-patching.c b/arch/powerpc/lib/code-patching.c
> index f9a3019e37b43c..c5ed9882383521 100644
> --- a/arch/powerpc/lib/code-patching.c
> +++ b/arch/powerpc/lib/code-patching.c
> @@ -228,6 +228,11 @@ bool is_offset_in_branch_range(long offset)
> return (offset >= -0x2000000 && offset <= 0x1fffffc && !(offset & 0x3));
> }
>
> +bool is_offset_in_cond_branch_range(long offset)
> +{
> + return offset >= -0x8000 && offset <= 0x7fff && !(offset & 0x3);
> +}
> +
> /*
> * Helper to check if a given instruction is a conditional branch
> * Derived from the conditional checks in analyse_instr()
> @@ -280,7 +285,7 @@ int create_cond_branch(struct ppc_inst *instr, const u32 *addr,
> offset = offset - (unsigned long)addr;
>
> /* Check we can represent the target in the instruction format */
> - if (offset < -0x8000 || offset > 0x7FFF || offset & 0x3)
> + if (!is_offset_in_cond_branch_range(offset))
> return 1;
>
> /* Mask out the flags and target, so they don't step on each other. */
> diff --git a/arch/powerpc/net/bpf_jit.h b/arch/powerpc/net/bpf_jit.h
> index 99fad093f43ec1..935ea95b66359e 100644
> --- a/arch/powerpc/net/bpf_jit.h
> +++ b/arch/powerpc/net/bpf_jit.h
> @@ -78,11 +78,6 @@
> #define PPC_FUNC_ADDR(d,i) do { PPC_LI32(d, i); } while(0)
> #endif
>
> -static inline bool is_nearbranch(int offset)
> -{
> - return (offset < 32768) && (offset >= -32768);
> -}
> -
> /*
> * The fly in the ointment of code size changing from pass to pass is
> * avoided by padding the short branch case with a NOP. If code size differs
> @@ -91,7 +86,7 @@ static inline bool is_nearbranch(int offset)
> * state.
> */
> #define PPC_BCC(cond, dest) do { \
> - if (is_nearbranch((dest) - (ctx->idx * 4))) { \
> + if (is_offset_in_cond_branch_range((long)(dest) - (ctx->idx * 4))) { \
> PPC_BCC_SHORT(cond, dest); \
> EMIT(PPC_RAW_NOP()); \
> } else { \
>
^ permalink raw reply
* Re: [PATCH v2 02/10] powerpc/bpf: Validate branch ranges
From: Christophe Leroy @ 2021-10-06 4:51 UTC (permalink / raw)
To: Naveen N. Rao, Michael Ellerman, Nicholas Piggin, Jordan Niethe,
Daniel Borkmann, Alexei Starovoitov, Johan Almbladh, Song Liu
Cc: bpf, linuxppc-dev
In-Reply-To: <71d33a6b7603ec1013c9734dd8bdd4ff5e929142.1633464148.git.naveen.n.rao@linux.vnet.ibm.com>
Le 05/10/2021 à 22:25, Naveen N. Rao a écrit :
> Add checks to ensure that we never emit branch instructions with
> truncated branch offsets.
>
> Acked-by: Song Liu <songliubraving@fb.com>
> Acked-by: Johan Almbladh <johan.almbladh@anyfinetworks.com>
> Tested-by: Johan Almbladh <johan.almbladh@anyfinetworks.com>
> Suggested-by: Michael Ellerman <mpe@ellerman.id.au>
> Signed-off-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
> ---
> arch/powerpc/net/bpf_jit.h | 26 ++++++++++++++++++++------
> arch/powerpc/net/bpf_jit_comp.c | 6 +++++-
> arch/powerpc/net/bpf_jit_comp32.c | 8 ++++++--
> arch/powerpc/net/bpf_jit_comp64.c | 8 ++++++--
> 4 files changed, 37 insertions(+), 11 deletions(-)
>
> diff --git a/arch/powerpc/net/bpf_jit.h b/arch/powerpc/net/bpf_jit.h
> index 935ea95b66359e..7e9b978b768ed9 100644
> --- a/arch/powerpc/net/bpf_jit.h
> +++ b/arch/powerpc/net/bpf_jit.h
> @@ -24,16 +24,30 @@
> #define EMIT(instr) PLANT_INSTR(image, ctx->idx, instr)
>
> /* Long jump; (unconditional 'branch') */
> -#define PPC_JMP(dest) EMIT(PPC_INST_BRANCH | \
> - (((dest) - (ctx->idx * 4)) & 0x03fffffc))
> +#define PPC_JMP(dest) \
> + do { \
> + long offset = (long)(dest) - (ctx->idx * 4); \
> + if (!is_offset_in_branch_range(offset)) { \
> + pr_err_ratelimited("Branch offset 0x%lx (@%u) out of range\n", offset, ctx->idx); \
> + return -ERANGE; \
> + } \
> + EMIT(PPC_INST_BRANCH | (offset & 0x03fffffc)); \
> + } while (0)
> +
> /* blr; (unconditional 'branch' with link) to absolute address */
> #define PPC_BL_ABS(dest) EMIT(PPC_INST_BL | \
> (((dest) - (unsigned long)(image + ctx->idx)) & 0x03fffffc))
> /* "cond" here covers BO:BI fields. */
> -#define PPC_BCC_SHORT(cond, dest) EMIT(PPC_INST_BRANCH_COND | \
> - (((cond) & 0x3ff) << 16) | \
> - (((dest) - (ctx->idx * 4)) & \
> - 0xfffc))
> +#define PPC_BCC_SHORT(cond, dest) \
> + do { \
> + long offset = (long)(dest) - (ctx->idx * 4); \
> + if (!is_offset_in_cond_branch_range(offset)) { \
> + pr_err_ratelimited("Conditional branch offset 0x%lx (@%u) out of range\n", offset, ctx->idx); \
> + return -ERANGE; \
> + } \
> + EMIT(PPC_INST_BRANCH_COND | (((cond) & 0x3ff) << 16) | (offset & 0xfffc)); \
> + } while (0)
> +
> /* Sign-extended 32-bit immediate load */
> #define PPC_LI32(d, i) do { \
> if ((int)(uintptr_t)(i) >= -32768 && \
> diff --git a/arch/powerpc/net/bpf_jit_comp.c b/arch/powerpc/net/bpf_jit_comp.c
> index 53aefee3fe70be..fcbf7a917c566e 100644
> --- a/arch/powerpc/net/bpf_jit_comp.c
> +++ b/arch/powerpc/net/bpf_jit_comp.c
> @@ -210,7 +210,11 @@ struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *fp)
> /* Now build the prologue, body code & epilogue for real. */
> cgctx.idx = 0;
> bpf_jit_build_prologue(code_base, &cgctx);
> - bpf_jit_build_body(fp, code_base, &cgctx, addrs, extra_pass);
> + if (bpf_jit_build_body(fp, code_base, &cgctx, addrs, extra_pass)) {
> + bpf_jit_binary_free(bpf_hdr);
> + fp = org_fp;
> + goto out_addrs;
> + }
> bpf_jit_build_epilogue(code_base, &cgctx);
>
> if (bpf_jit_enable > 1)
> diff --git a/arch/powerpc/net/bpf_jit_comp32.c b/arch/powerpc/net/bpf_jit_comp32.c
> index beb12cbc8c2994..a74d52204f8da2 100644
> --- a/arch/powerpc/net/bpf_jit_comp32.c
> +++ b/arch/powerpc/net/bpf_jit_comp32.c
> @@ -200,7 +200,7 @@ void bpf_jit_emit_func_call_rel(u32 *image, struct codegen_context *ctx, u64 fun
> }
> }
>
> -static void bpf_jit_emit_tail_call(u32 *image, struct codegen_context *ctx, u32 out)
> +static int bpf_jit_emit_tail_call(u32 *image, struct codegen_context *ctx, u32 out)
> {
> /*
> * By now, the eBPF program has already setup parameters in r3-r6
> @@ -261,7 +261,9 @@ static void bpf_jit_emit_tail_call(u32 *image, struct codegen_context *ctx, u32
> bpf_jit_emit_common_epilogue(image, ctx);
>
> EMIT(PPC_RAW_BCTR());
> +
> /* out: */
> + return 0;
> }
>
> /* Assemble the body code between the prologue & epilogue */
> @@ -1090,7 +1092,9 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, struct codegen_context *
> */
> case BPF_JMP | BPF_TAIL_CALL:
> ctx->seen |= SEEN_TAILCALL;
> - bpf_jit_emit_tail_call(image, ctx, addrs[i + 1]);
> + ret = bpf_jit_emit_tail_call(image, ctx, addrs[i + 1]);
> + if (ret < 0)
> + return ret;
> break;
>
> default:
> diff --git a/arch/powerpc/net/bpf_jit_comp64.c b/arch/powerpc/net/bpf_jit_comp64.c
> index b87a63dba9c8fb..f06c62089b1457 100644
> --- a/arch/powerpc/net/bpf_jit_comp64.c
> +++ b/arch/powerpc/net/bpf_jit_comp64.c
> @@ -206,7 +206,7 @@ void bpf_jit_emit_func_call_rel(u32 *image, struct codegen_context *ctx, u64 fun
> EMIT(PPC_RAW_BCTRL());
> }
>
> -static void bpf_jit_emit_tail_call(u32 *image, struct codegen_context *ctx, u32 out)
> +static int bpf_jit_emit_tail_call(u32 *image, struct codegen_context *ctx, u32 out)
> {
> /*
> * By now, the eBPF program has already setup parameters in r3, r4 and r5
> @@ -267,7 +267,9 @@ static void bpf_jit_emit_tail_call(u32 *image, struct codegen_context *ctx, u32
> bpf_jit_emit_common_epilogue(image, ctx);
>
> EMIT(PPC_RAW_BCTR());
> +
> /* out: */
> + return 0;
> }
>
> /* Assemble the body code between the prologue & epilogue */
> @@ -993,7 +995,9 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, struct codegen_context *
> */
> case BPF_JMP | BPF_TAIL_CALL:
> ctx->seen |= SEEN_TAILCALL;
> - bpf_jit_emit_tail_call(image, ctx, addrs[i + 1]);
> + ret = bpf_jit_emit_tail_call(image, ctx, addrs[i + 1]);
> + if (ret < 0)
> + return ret;
> break;
>
> default:
>
^ permalink raw reply
* Re: [PATCH v2 02/10] powerpc/bpf: Validate branch ranges
From: LEROY Christophe @ 2021-10-06 4:51 UTC (permalink / raw)
To: Naveen N. Rao, Michael Ellerman, Nicholas Piggin, Jordan Niethe,
Daniel Borkmann, Alexei Starovoitov, Johan Almbladh, Song Liu
Cc: bpf@vger.kernel.org, linuxppc-dev@lists.ozlabs.org
In-Reply-To: <71d33a6b7603ec1013c9734dd8bdd4ff5e929142.1633464148.git.naveen.n.rao@linux.vnet.ibm.com>
Le 05/10/2021 à 22:25, Naveen N. Rao a écrit :
> Add checks to ensure that we never emit branch instructions with
> truncated branch offsets.
>
> Acked-by: Song Liu <songliubraving@fb.com>
> Acked-by: Johan Almbladh <johan.almbladh@anyfinetworks.com>
> Tested-by: Johan Almbladh <johan.almbladh@anyfinetworks.com>
> Suggested-by: Michael Ellerman <mpe@ellerman.id.au>
> Signed-off-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
> ---
> arch/powerpc/net/bpf_jit.h | 26 ++++++++++++++++++++------
> arch/powerpc/net/bpf_jit_comp.c | 6 +++++-
> arch/powerpc/net/bpf_jit_comp32.c | 8 ++++++--
> arch/powerpc/net/bpf_jit_comp64.c | 8 ++++++--
> 4 files changed, 37 insertions(+), 11 deletions(-)
>
> diff --git a/arch/powerpc/net/bpf_jit.h b/arch/powerpc/net/bpf_jit.h
> index 935ea95b66359e..7e9b978b768ed9 100644
> --- a/arch/powerpc/net/bpf_jit.h
> +++ b/arch/powerpc/net/bpf_jit.h
> @@ -24,16 +24,30 @@
> #define EMIT(instr) PLANT_INSTR(image, ctx->idx, instr)
>
> /* Long jump; (unconditional 'branch') */
> -#define PPC_JMP(dest) EMIT(PPC_INST_BRANCH | \
> - (((dest) - (ctx->idx * 4)) & 0x03fffffc))
> +#define PPC_JMP(dest) \
> + do { \
> + long offset = (long)(dest) - (ctx->idx * 4); \
> + if (!is_offset_in_branch_range(offset)) { \
> + pr_err_ratelimited("Branch offset 0x%lx (@%u) out of range\n", offset, ctx->idx); \
> + return -ERANGE; \
> + } \
> + EMIT(PPC_INST_BRANCH | (offset & 0x03fffffc)); \
> + } while (0)
> +
> /* blr; (unconditional 'branch' with link) to absolute address */
> #define PPC_BL_ABS(dest) EMIT(PPC_INST_BL | \
> (((dest) - (unsigned long)(image + ctx->idx)) & 0x03fffffc))
> /* "cond" here covers BO:BI fields. */
> -#define PPC_BCC_SHORT(cond, dest) EMIT(PPC_INST_BRANCH_COND | \
> - (((cond) & 0x3ff) << 16) | \
> - (((dest) - (ctx->idx * 4)) & \
> - 0xfffc))
> +#define PPC_BCC_SHORT(cond, dest) \
> + do { \
> + long offset = (long)(dest) - (ctx->idx * 4); \
> + if (!is_offset_in_cond_branch_range(offset)) { \
> + pr_err_ratelimited("Conditional branch offset 0x%lx (@%u) out of range\n", offset, ctx->idx); \
> + return -ERANGE; \
> + } \
> + EMIT(PPC_INST_BRANCH_COND | (((cond) & 0x3ff) << 16) | (offset & 0xfffc)); \
> + } while (0)
> +
> /* Sign-extended 32-bit immediate load */
> #define PPC_LI32(d, i) do { \
> if ((int)(uintptr_t)(i) >= -32768 && \
> diff --git a/arch/powerpc/net/bpf_jit_comp.c b/arch/powerpc/net/bpf_jit_comp.c
> index 53aefee3fe70be..fcbf7a917c566e 100644
> --- a/arch/powerpc/net/bpf_jit_comp.c
> +++ b/arch/powerpc/net/bpf_jit_comp.c
> @@ -210,7 +210,11 @@ struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *fp)
> /* Now build the prologue, body code & epilogue for real. */
> cgctx.idx = 0;
> bpf_jit_build_prologue(code_base, &cgctx);
> - bpf_jit_build_body(fp, code_base, &cgctx, addrs, extra_pass);
> + if (bpf_jit_build_body(fp, code_base, &cgctx, addrs, extra_pass)) {
> + bpf_jit_binary_free(bpf_hdr);
> + fp = org_fp;
> + goto out_addrs;
> + }
> bpf_jit_build_epilogue(code_base, &cgctx);
>
> if (bpf_jit_enable > 1)
> diff --git a/arch/powerpc/net/bpf_jit_comp32.c b/arch/powerpc/net/bpf_jit_comp32.c
> index beb12cbc8c2994..a74d52204f8da2 100644
> --- a/arch/powerpc/net/bpf_jit_comp32.c
> +++ b/arch/powerpc/net/bpf_jit_comp32.c
> @@ -200,7 +200,7 @@ void bpf_jit_emit_func_call_rel(u32 *image, struct codegen_context *ctx, u64 fun
> }
> }
>
> -static void bpf_jit_emit_tail_call(u32 *image, struct codegen_context *ctx, u32 out)
> +static int bpf_jit_emit_tail_call(u32 *image, struct codegen_context *ctx, u32 out)
> {
> /*
> * By now, the eBPF program has already setup parameters in r3-r6
> @@ -261,7 +261,9 @@ static void bpf_jit_emit_tail_call(u32 *image, struct codegen_context *ctx, u32
> bpf_jit_emit_common_epilogue(image, ctx);
>
> EMIT(PPC_RAW_BCTR());
> +
> /* out: */
> + return 0;
> }
>
> /* Assemble the body code between the prologue & epilogue */
> @@ -1090,7 +1092,9 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, struct codegen_context *
> */
> case BPF_JMP | BPF_TAIL_CALL:
> ctx->seen |= SEEN_TAILCALL;
> - bpf_jit_emit_tail_call(image, ctx, addrs[i + 1]);
> + ret = bpf_jit_emit_tail_call(image, ctx, addrs[i + 1]);
> + if (ret < 0)
> + return ret;
> break;
>
> default:
> diff --git a/arch/powerpc/net/bpf_jit_comp64.c b/arch/powerpc/net/bpf_jit_comp64.c
> index b87a63dba9c8fb..f06c62089b1457 100644
> --- a/arch/powerpc/net/bpf_jit_comp64.c
> +++ b/arch/powerpc/net/bpf_jit_comp64.c
> @@ -206,7 +206,7 @@ void bpf_jit_emit_func_call_rel(u32 *image, struct codegen_context *ctx, u64 fun
> EMIT(PPC_RAW_BCTRL());
> }
>
> -static void bpf_jit_emit_tail_call(u32 *image, struct codegen_context *ctx, u32 out)
> +static int bpf_jit_emit_tail_call(u32 *image, struct codegen_context *ctx, u32 out)
> {
> /*
> * By now, the eBPF program has already setup parameters in r3, r4 and r5
> @@ -267,7 +267,9 @@ static void bpf_jit_emit_tail_call(u32 *image, struct codegen_context *ctx, u32
> bpf_jit_emit_common_epilogue(image, ctx);
>
> EMIT(PPC_RAW_BCTR());
> +
> /* out: */
> + return 0;
> }
>
> /* Assemble the body code between the prologue & epilogue */
> @@ -993,7 +995,9 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, struct codegen_context *
> */
> case BPF_JMP | BPF_TAIL_CALL:
> ctx->seen |= SEEN_TAILCALL;
> - bpf_jit_emit_tail_call(image, ctx, addrs[i + 1]);
> + ret = bpf_jit_emit_tail_call(image, ctx, addrs[i + 1]);
> + if (ret < 0)
> + return ret;
> break;
>
> default:
>
^ permalink raw reply
* Re: [PATCH v2 03/10] powerpc/bpf: Fix BPF_MOD when imm == 1
From: Christophe Leroy @ 2021-10-06 4:52 UTC (permalink / raw)
To: Naveen N. Rao, Michael Ellerman, Nicholas Piggin, Jordan Niethe,
Daniel Borkmann, Alexei Starovoitov, Johan Almbladh, Song Liu
Cc: bpf, linuxppc-dev
In-Reply-To: <c674ca18c3046885602caebb326213731c675d06.1633464148.git.naveen.n.rao@linux.vnet.ibm.com>
Le 05/10/2021 à 22:25, Naveen N. Rao a écrit :
> Only ignore the operation if dividing by 1.
>
> Acked-by: Song Liu <songliubraving@fb.com>
> Acked-by: Johan Almbladh <johan.almbladh@anyfinetworks.com>
> Tested-by: Johan Almbladh <johan.almbladh@anyfinetworks.com>
> Fixes: 156d0e290e969c ("powerpc/ebpf/jit: Implement JIT compiler for extended BPF")
> Signed-off-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
> ---
> arch/powerpc/net/bpf_jit_comp64.c | 10 ++++++++--
> 1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/arch/powerpc/net/bpf_jit_comp64.c b/arch/powerpc/net/bpf_jit_comp64.c
> index f06c62089b1457..d67f6d62e2e1ff 100644
> --- a/arch/powerpc/net/bpf_jit_comp64.c
> +++ b/arch/powerpc/net/bpf_jit_comp64.c
> @@ -391,8 +391,14 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, struct codegen_context *
> case BPF_ALU64 | BPF_DIV | BPF_K: /* dst /= imm */
> if (imm == 0)
> return -EINVAL;
> - else if (imm == 1)
> - goto bpf_alu32_trunc;
> + if (imm == 1) {
> + if (BPF_OP(code) == BPF_DIV) {
> + goto bpf_alu32_trunc;
> + } else {
> + EMIT(PPC_RAW_LI(dst_reg, 0));
> + break;
> + }
> + }
>
> PPC_LI32(b2p[TMP_REG_1], imm);
> switch (BPF_CLASS(code)) {
>
^ permalink raw reply
* Re: [PATCH v2 04/10] powerpc/bpf: Fix BPF_SUB when imm == 0x80000000
From: Christophe Leroy @ 2021-10-06 4:55 UTC (permalink / raw)
To: Naveen N. Rao, Michael Ellerman, Nicholas Piggin, Jordan Niethe,
Daniel Borkmann, Alexei Starovoitov, Johan Almbladh, Song Liu
Cc: bpf, linuxppc-dev
In-Reply-To: <fc4b1276eb10761fd7ce0814c8dd089da2815251.1633464148.git.naveen.n.rao@linux.vnet.ibm.com>
Le 05/10/2021 à 22:25, Naveen N. Rao a écrit :
> We aren't handling subtraction involving an immediate value of
> 0x80000000 properly. Fix the same.
>
> Fixes: 156d0e290e969c ("powerpc/ebpf/jit: Implement JIT compiler for extended BPF")
> Signed-off-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com>
> ---
> Changelog:
> - Split up BPF_ADD and BPF_SUB cases per Christophe's comments
>
> arch/powerpc/net/bpf_jit_comp64.c | 27 +++++++++++++++++----------
> 1 file changed, 17 insertions(+), 10 deletions(-)
>
> diff --git a/arch/powerpc/net/bpf_jit_comp64.c b/arch/powerpc/net/bpf_jit_comp64.c
> index d67f6d62e2e1ff..6626e6c17d4ed2 100644
> --- a/arch/powerpc/net/bpf_jit_comp64.c
> +++ b/arch/powerpc/net/bpf_jit_comp64.c
> @@ -330,18 +330,25 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, struct codegen_context *
> EMIT(PPC_RAW_SUB(dst_reg, dst_reg, src_reg));
> goto bpf_alu32_trunc;
> case BPF_ALU | BPF_ADD | BPF_K: /* (u32) dst += (u32) imm */
> - case BPF_ALU | BPF_SUB | BPF_K: /* (u32) dst -= (u32) imm */
> case BPF_ALU64 | BPF_ADD | BPF_K: /* dst += imm */
> + if (!imm) {
> + goto bpf_alu32_trunc;
> + } else if (imm >= -32768 && imm < 32768) {
> + EMIT(PPC_RAW_ADDI(dst_reg, dst_reg, IMM_L(imm)));
> + } else {
> + PPC_LI32(b2p[TMP_REG_1], imm);
> + EMIT(PPC_RAW_ADD(dst_reg, dst_reg, b2p[TMP_REG_1]));
> + }
> + goto bpf_alu32_trunc;
> + case BPF_ALU | BPF_SUB | BPF_K: /* (u32) dst -= (u32) imm */
> case BPF_ALU64 | BPF_SUB | BPF_K: /* dst -= imm */
> - if (BPF_OP(code) == BPF_SUB)
> - imm = -imm;
> - if (imm) {
> - if (imm >= -32768 && imm < 32768)
> - EMIT(PPC_RAW_ADDI(dst_reg, dst_reg, IMM_L(imm)));
> - else {
> - PPC_LI32(b2p[TMP_REG_1], imm);
> - EMIT(PPC_RAW_ADD(dst_reg, dst_reg, b2p[TMP_REG_1]));
> - }
> + if (!imm) {
> + goto bpf_alu32_trunc;
> + } else if (imm > -32768 && imm < 32768) {
Why do you exclude imm == 32768 ?
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
> + EMIT(PPC_RAW_ADDI(dst_reg, dst_reg, IMM_L(-imm)));
> + } else {
> + PPC_LI32(b2p[TMP_REG_1], imm);
> + EMIT(PPC_RAW_SUB(dst_reg, dst_reg, b2p[TMP_REG_1]));
> }
> goto bpf_alu32_trunc;
> case BPF_ALU | BPF_MUL | BPF_X: /* (u32) dst *= (u32) src */
>
^ permalink raw reply
* Re: [PATCH v2 07/10] powerpc/bpf ppc32: Fix ALU32 BPF_ARSH operation
From: Christophe Leroy @ 2021-10-06 4:56 UTC (permalink / raw)
To: Naveen N. Rao, Michael Ellerman, Nicholas Piggin, Jordan Niethe,
Daniel Borkmann, Alexei Starovoitov, Johan Almbladh, Song Liu
Cc: bpf, linuxppc-dev
In-Reply-To: <6d24c1f9e79b6f61f5135eaf2ea1e8bcd4dac87b.1633464148.git.naveen.n.rao@linux.vnet.ibm.com>
Le 05/10/2021 à 22:25, Naveen N. Rao a écrit :
> Correct the destination register used for ALU32 BPF_ARSH operation.
>
> Fixes: 51c66ad849a703 ("powerpc/bpf: Implement extended BPF on PPC32")
> Signed-off-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
> ---
> arch/powerpc/net/bpf_jit_comp32.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/powerpc/net/bpf_jit_comp32.c b/arch/powerpc/net/bpf_jit_comp32.c
> index a74d52204f8da2..519ecb9ab67266 100644
> --- a/arch/powerpc/net/bpf_jit_comp32.c
> +++ b/arch/powerpc/net/bpf_jit_comp32.c
> @@ -625,7 +625,7 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, struct codegen_context *
> EMIT(PPC_RAW_LI(dst_reg_h, 0));
> break;
> case BPF_ALU | BPF_ARSH | BPF_X: /* (s32) dst >>= src */
> - EMIT(PPC_RAW_SRAW(dst_reg_h, dst_reg, src_reg));
> + EMIT(PPC_RAW_SRAW(dst_reg, dst_reg, src_reg));
> break;
> case BPF_ALU64 | BPF_ARSH | BPF_X: /* (s64) dst >>= src */
> bpf_set_seen_register(ctx, tmp_reg);
>
^ permalink raw reply
* Re: [PATCH v2 08/10] powerpc/bpf ppc32: Fix JMP32_JSET_K
From: Christophe Leroy @ 2021-10-06 5:00 UTC (permalink / raw)
To: Naveen N. Rao, Michael Ellerman, Nicholas Piggin, Jordan Niethe,
Daniel Borkmann, Alexei Starovoitov, Johan Almbladh, Song Liu
Cc: bpf, linuxppc-dev
In-Reply-To: <b94489f52831305ec15aca4dd04a3527236be7e8.1633464148.git.naveen.n.rao@linux.vnet.ibm.com>
Le 05/10/2021 à 22:25, Naveen N. Rao a écrit :
> 'andi' only takes an unsigned 16-bit value. Correct the imm range used
> when emitting andi.
>
> Fixes: 51c66ad849a703 ("powerpc/bpf: Implement extended BPF on PPC32")
> Signed-off-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
> ---
> arch/powerpc/net/bpf_jit_comp32.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/powerpc/net/bpf_jit_comp32.c b/arch/powerpc/net/bpf_jit_comp32.c
> index 519ecb9ab67266..7c65de9ed4fa64 100644
> --- a/arch/powerpc/net/bpf_jit_comp32.c
> +++ b/arch/powerpc/net/bpf_jit_comp32.c
> @@ -1075,7 +1075,7 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, struct codegen_context *
> break;
> case BPF_JMP32 | BPF_JSET | BPF_K:
> /* andi does not sign-extend the immediate */
> - if (imm >= -32768 && imm < 32768) {
> + if (imm >= 0 && imm < 32768) {
> /* PPC_ANDI is _only/always_ dot-form */
> EMIT(PPC_RAW_ANDI(_R0, dst_reg, imm));
> } else {
>
^ permalink raw reply
* Re: [PATCH v2 10/10] powerpc/bpf ppc32: Fix BPF_SUB when imm == 0x80000000
From: Christophe Leroy @ 2021-10-06 5:02 UTC (permalink / raw)
To: Naveen N. Rao, Michael Ellerman, Nicholas Piggin, Jordan Niethe,
Daniel Borkmann, Alexei Starovoitov, Johan Almbladh, Song Liu
Cc: bpf, linuxppc-dev
In-Reply-To: <7135360a0cdf70adedbccf9863128b8daef18764.1633464148.git.naveen.n.rao@linux.vnet.ibm.com>
Le 05/10/2021 à 22:25, Naveen N. Rao a écrit :
> Special case handling of the smallest 32-bit negative number for BPF_SUB.
>
> Fixes: 51c66ad849a703 ("powerpc/bpf: Implement extended BPF on PPC32")
> Signed-off-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
> ---
> arch/powerpc/net/bpf_jit_comp32.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/powerpc/net/bpf_jit_comp32.c b/arch/powerpc/net/bpf_jit_comp32.c
> index 68dc8a8231de04..0da31d41d41310 100644
> --- a/arch/powerpc/net/bpf_jit_comp32.c
> +++ b/arch/powerpc/net/bpf_jit_comp32.c
> @@ -357,7 +357,7 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, struct codegen_context *
> PPC_LI32(_R0, imm);
> EMIT(PPC_RAW_ADDC(dst_reg, dst_reg, _R0));
> }
> - if (imm >= 0)
> + if (imm >= 0 || (BPF_OP(code) == BPF_SUB && imm == 0x80000000))
> EMIT(PPC_RAW_ADDZE(dst_reg_h, dst_reg_h));
> else
> EMIT(PPC_RAW_ADDME(dst_reg_h, dst_reg_h));
>
^ permalink raw reply
* Re: [PATCH v2 09/10] powerpc/bpf ppc32: Do not emit zero extend instruction for 64-bit BPF_END
From: Christophe Leroy @ 2021-10-06 5:03 UTC (permalink / raw)
To: Naveen N. Rao, Michael Ellerman, Nicholas Piggin, Jordan Niethe,
Daniel Borkmann, Alexei Starovoitov, Johan Almbladh, Song Liu
Cc: bpf, linuxppc-dev
In-Reply-To: <b4e3c3546121315a8e2059b19a1bda84971816e4.1633464148.git.naveen.n.rao@linux.vnet.ibm.com>
Le 05/10/2021 à 22:25, Naveen N. Rao a écrit :
> Suppress emitting zero extend instruction for 64-bit BPF_END_FROM_[L|B]E
> operation.
>
> Fixes: 51c66ad849a703 ("powerpc/bpf: Implement extended BPF on PPC32")
> Signed-off-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
> ---
> arch/powerpc/net/bpf_jit_comp32.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/powerpc/net/bpf_jit_comp32.c b/arch/powerpc/net/bpf_jit_comp32.c
> index 7c65de9ed4fa64..68dc8a8231de04 100644
> --- a/arch/powerpc/net/bpf_jit_comp32.c
> +++ b/arch/powerpc/net/bpf_jit_comp32.c
> @@ -1107,7 +1107,7 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, struct codegen_context *
> return -EOPNOTSUPP;
> }
> if (BPF_CLASS(code) == BPF_ALU && !fp->aux->verifier_zext &&
> - !insn_is_zext(&insn[i + 1]))
> + !insn_is_zext(&insn[i + 1]) && !(BPF_OP(code) == BPF_END && imm == 64))
> EMIT(PPC_RAW_LI(dst_reg_h, 0));
> }
>
>
^ permalink raw reply
* Re: [PATCH v5 00/14] PCI: Add support for Apple M1
From: Michael Ellerman @ 2021-10-06 5:56 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, linuxppc-dev@lists.ozlabs.org list,
opensuse-ppc
Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Mark Kettenis, Lorenzo Pieralisi, Krzysztof Wilczyński,
Marc Zyngier, Joerg Roedel, Sven Peter,
linux-kernel@vger.kernel.org, Joey Gouly, Hector Martin, PCI,
Bjorn Helgaas, Android Kernel Team, Robin Murphy,
Alyssa Rosenzweig, Stan Skowronek
In-Reply-To: <CACRpkdaL=YEfqSmAogLcP0Gn2gUqSaEXZQrJD1GR5QU+DyuyDQ@mail.gmail.com>
Linus Walleij <linus.walleij@linaro.org> writes:
> On Mon, Oct 4, 2021 at 9:52 PM Rob Herring <robh+dt@kernel.org> wrote:
>
>> FYI, I pushed patches 1-3 to kernelCI and didn't see any regressions.
>> I am a bit worried about changes to the DT interrupt parsing and
>> ancient platforms (such as PowerMacs). Most likely there wouldn't be
>> any report until -rc1 or months later on those old systems.
>
> Lets page the PPC lists to see if someone can test on some powermac.
It boots and everything seems fine on an iMac-G5 of mine.
I don't have access to any other powermac hardware at the moment due to
the lockdown here.
cheers
^ permalink raw reply
* Re: [RFC 3/5] ipmi:bt-bmc: Put arch specific function into bt_bmc_ops
From: Cédric Le Goater @ 2021-10-06 6:01 UTC (permalink / raw)
To: Anton Blanchard, alistair, joel, andrew, mikey, jk; +Cc: linuxppc-dev
In-Reply-To: <20211006021205.2579057-3-anton@ozlabs.org>
On 10/6/21 04:12, Anton Blanchard wrote:
> While most of the driver is arch agnostic, setting up and handling
> interrupts, and enabling the hardware is not. Create bt_bmc_ops to
> handle these functions.
>
> Signed-off-by: Anton Blanchard <anton@ozlabs.org>
See comment on patch 5. Any how,
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks
C.
> ---
> drivers/char/ipmi/bt-bmc.c | 24 ++++++++++++++++++++----
> 1 file changed, 20 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/char/ipmi/bt-bmc.c b/drivers/char/ipmi/bt-bmc.c
> index 2b0fe1255026..b48e04405ac4 100644
> --- a/drivers/char/ipmi/bt-bmc.c
> +++ b/drivers/char/ipmi/bt-bmc.c
> @@ -17,6 +17,7 @@
> #include <linux/regmap.h>
> #include <linux/sched.h>
> #include <linux/timer.h>
> +#include <linux/of_device.h>
>
> /*
> * This is a BMC device used to communicate to the host
> @@ -435,15 +436,30 @@ static void aspeed_enable_bt(struct bt_bmc *bt_bmc)
> BT_CR0_ENABLE_IBT);
> }
>
> +struct bt_bmc_ops {
> + int (*config_irq)(struct bt_bmc *bt_bmc, struct platform_device *pdev);
> + void (*enable_bt)(struct bt_bmc *bt_bmc);
> +};
> +
> +static const struct bt_bmc_ops aspeed_bt_bmc_ops = {
> + .config_irq = aspeed_bt_bmc_config_irq,
> + .enable_bt = aspeed_enable_bt,
> +};
> +
> static int bt_bmc_probe(struct platform_device *pdev)
> {
> struct bt_bmc *bt_bmc;
> struct device *dev;
> int rc;
> + const struct bt_bmc_ops *ops;
>
> dev = &pdev->dev;
> dev_info(dev, "Found bt bmc device\n");
>
> + ops = of_device_get_match_data(&pdev->dev);
> + if (!ops)
> + return -ENODEV;
> +
> bt_bmc = devm_kzalloc(dev, sizeof(*bt_bmc), GFP_KERNEL);
> if (!bt_bmc)
> return -ENOMEM;
> @@ -483,7 +499,7 @@ static int bt_bmc_probe(struct platform_device *pdev)
> return rc;
> }
>
> - aspeed_bt_bmc_config_irq(bt_bmc, pdev);
> + ops->config_irq(bt_bmc, pdev);
>
> if (bt_bmc->irq >= 0) {
> dev_info(dev, "Using IRQ %d\n", bt_bmc->irq);
> @@ -494,7 +510,7 @@ static int bt_bmc_probe(struct platform_device *pdev)
> add_timer(&bt_bmc->poll_timer);
> }
>
> - aspeed_enable_bt(bt_bmc);
> + ops->enable_bt(bt_bmc);
>
> clr_b_busy(bt_bmc);
>
> @@ -512,8 +528,8 @@ static int bt_bmc_remove(struct platform_device *pdev)
> }
>
> static const struct of_device_id bt_bmc_match[] = {
> - { .compatible = "aspeed,ast2400-ibt-bmc" },
> - { .compatible = "aspeed,ast2500-ibt-bmc" },
> + { .compatible = "aspeed,ast2400-ibt-bmc", .data = &aspeed_bt_bmc_ops },
> + { .compatible = "aspeed,ast2500-ibt-bmc", .data = &aspeed_bt_bmc_ops },
> { },
> };
>
>
^ permalink raw reply
* Re: [RFC 5/5] ipmi:bt-bmc: Add Microwatt
From: Cédric Le Goater @ 2021-10-06 6:00 UTC (permalink / raw)
To: Anton Blanchard, alistair, joel, andrew, mikey, jk; +Cc: linuxppc-dev
In-Reply-To: <20211006021205.2579057-5-anton@ozlabs.org>
On 10/6/21 04:12, Anton Blanchard wrote:
> This adds the Microwatt specific bits, including interrupt support.
>
> Signed-off-by: Anton Blanchard <anton@ozlabs.org>
> ---
> .../devicetree/bindings/ipmi/ibt-bmc.txt | 1 +
> drivers/char/ipmi/Kconfig | 8 ++-
> drivers/char/ipmi/bt-bmc.c | 69 +++++++++++++++++++
> 3 files changed, 75 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/ipmi/ibt-bmc.txt b/Documentation/devicetree/bindings/ipmi/ibt-bmc.txt
> index 78ee716a950e..1b661daf0193 100644
> --- a/Documentation/devicetree/bindings/ipmi/ibt-bmc.txt
> +++ b/Documentation/devicetree/bindings/ipmi/ibt-bmc.txt
> @@ -9,6 +9,7 @@ Required properties:
> - compatible : should be one of
> "aspeed,ast2400-ibt-bmc"
> "aspeed,ast2500-ibt-bmc"
> + "ibm,microwatt-ibt-bmc"
> - reg: physical address and size of the registers
>
> Optional properties:
> diff --git a/drivers/char/ipmi/Kconfig b/drivers/char/ipmi/Kconfig
> index 8b2f0f675e5f..079302f4eef2 100644
> --- a/drivers/char/ipmi/Kconfig
> +++ b/drivers/char/ipmi/Kconfig
> @@ -152,13 +152,15 @@ config IPMI_KCS_BMC_SERIO
> called kcs_bmc_serio.
>
> config BT_IPMI_BMC
> - depends on ARCH_ASPEED || COMPILE_TEST
> + depends on ARCH_ASPEED || PPC_MICROWATT || COMPILE_TEST
> depends on REGMAP && REGMAP_MMIO && MFD_SYSCON
> tristate "BT IPMI bmc driver"
> help
> Provides a driver for the BT (Block Transfer) IPMI interface
> - found on Aspeed SOCs (AST2400 and AST2500). The driver
> - implements the BMC side of the BT interface.
> + found on Aspeed SOCs (AST2400 and AST2500) as well as the OpenPOWER
> + LPC peripheral macro at
> + <https://github.com/OpenPOWERFoundation/lpcperipheral>
> + The driver implements the BMC side of the BT interface.
>
> config IPMB_DEVICE_INTERFACE
> tristate 'IPMB Interface handler'
> diff --git a/drivers/char/ipmi/bt-bmc.c b/drivers/char/ipmi/bt-bmc.c
> index b48e04405ac4..24327b57c60b 100644
> --- a/drivers/char/ipmi/bt-bmc.c
> +++ b/drivers/char/ipmi/bt-bmc.c
> @@ -41,6 +41,11 @@
> #define BT_CR2_IRQ_HBUSY 0x40
> #define ASPEED_BT_CR3 0xc
>
> +#define MICROWATT_IRQ_MASK 0x0
> +#define MICROWATT_IRQ_STATUS 0x4
> +#define IRQ_HOST_TO_BMC_ATTN 0x1
> +#define IRQ_HOST_NOT_BUSY 0x2
> +
> #define BT_CTRL 0x10
> #define BT_CTRL_B_BUSY 0x80
> #define BT_CTRL_H_BUSY 0x40
> @@ -395,6 +400,27 @@ static irqreturn_t aspeed_bt_bmc_irq(int irq, void *arg)
> return IRQ_HANDLED;
> }
>
> +static irqreturn_t microwatt_bt_bmc_irq(int irq, void *arg)
> +{
> + struct bt_bmc *bt_bmc = arg;
> + u32 reg;
> + int rc;
> +
> + rc = regmap_read(bt_bmc->map, bt_bmc->offset + MICROWATT_IRQ_STATUS, ®);
> + if (rc)
> + return IRQ_NONE;
> +
> + /* Interrupt wasn't something we knew about */
> + if (!(reg & (IRQ_HOST_TO_BMC_ATTN | IRQ_HOST_NOT_BUSY)))
> + return IRQ_NONE;
> +
> + /* ack all pending IRQs */
> + regmap_write(bt_bmc->map, bt_bmc->offset + MICROWATT_IRQ_STATUS, 0);
> +
> + wake_up(&bt_bmc->queue);
> + return IRQ_HANDLED;
> +}
> +
> static int aspeed_bt_bmc_config_irq(struct bt_bmc *bt_bmc,
> struct platform_device *pdev)
> {
> @@ -446,6 +472,48 @@ static const struct bt_bmc_ops aspeed_bt_bmc_ops = {
> .enable_bt = aspeed_enable_bt,
> };
>
> +static int microwatt_bt_bmc_config_irq(struct bt_bmc *bt_bmc,
> + struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + int rc;
> +
> + bt_bmc->irq = platform_get_irq_optional(pdev, 0);
> + if (bt_bmc->irq < 0)
> + return bt_bmc->irq;
> +
> + rc = devm_request_irq(dev, bt_bmc->irq, microwatt_bt_bmc_irq, IRQF_SHARED,
> + DEVICE_NAME, bt_bmc);
> + if (rc < 0) {
> + dev_warn(dev, "Unable to request IRQ %d\n", bt_bmc->irq);
> + bt_bmc->irq = rc;
> + return rc;
> + }
> +
> + /*
> + * Configure the hardware to give us an interrupt whenever the H2B
> + * bit is set or the HBUSY bit is cleared.
> + *
> + * H2B will be asserted when the bmc has data for us; HBUSY
> + * will be cleared (along with B2H) when we can write the next
> + * message to the BT buffer
> + */
> + rc = regmap_update_bits(bt_bmc->map, bt_bmc->offset + MICROWATT_IRQ_MASK,
> + (IRQ_HOST_TO_BMC_ATTN | IRQ_HOST_NOT_BUSY),
> + (IRQ_HOST_TO_BMC_ATTN | IRQ_HOST_NOT_BUSY));
This is the only difference. May be we could introduce a ->config_irq_hw()
handler to keep a larger part common. No big deal.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
C.
> + return rc;
> +}
> +
> +static void microwatt_enable_bt(struct bt_bmc *bt_bmc)
> +{
> +}
> +
> +static const struct bt_bmc_ops microwatt_bt_bmc_ops = {
> + .config_irq = microwatt_bt_bmc_config_irq,
> + .enable_bt = microwatt_enable_bt,
> +};
> +
> static int bt_bmc_probe(struct platform_device *pdev)
> {
> struct bt_bmc *bt_bmc;
> @@ -530,6 +598,7 @@ static int bt_bmc_remove(struct platform_device *pdev)
> static const struct of_device_id bt_bmc_match[] = {
> { .compatible = "aspeed,ast2400-ibt-bmc", .data = &aspeed_bt_bmc_ops },
> { .compatible = "aspeed,ast2500-ibt-bmc", .data = &aspeed_bt_bmc_ops },
> + { .compatible = "ibm,microwatt-ibt-bmc", .data = µwatt_bt_bmc_ops },
> { },
> };
>
>
^ permalink raw reply
* Re: [RFC 1/5] ipmi:bt-bmc: Separate out ASPEED specific bits
From: Cédric Le Goater @ 2021-10-06 6:02 UTC (permalink / raw)
To: Anton Blanchard, alistair, joel, andrew, mikey, jk; +Cc: linuxppc-dev
In-Reply-To: <20211006021205.2579057-1-anton@ozlabs.org>
On 10/6/21 04:12, Anton Blanchard wrote:
> Most of the IPMI BT BMC driver is architecture agnostic - it deals with
> architected registers and behaviour in the IPMI specification.
>
> Separate out the few ASPEED specific bits into their own functions
> so we can use this driver on other architectures.
>
> Signed-off-by: Anton Blanchard <anton@ozlabs.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> drivers/char/ipmi/bt-bmc.c | 26 ++++++++++++++++----------
> 1 file changed, 16 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/char/ipmi/bt-bmc.c b/drivers/char/ipmi/bt-bmc.c
> index 6e3d247b55d1..f85fafc96ef6 100644
> --- a/drivers/char/ipmi/bt-bmc.c
> +++ b/drivers/char/ipmi/bt-bmc.c
> @@ -39,6 +39,7 @@
> #define BT_CR2_IRQ_H2B 0x01
> #define BT_CR2_IRQ_HBUSY 0x40
> #define BT_CR3 0xc
> +
> #define BT_CTRL 0x10
> #define BT_CTRL_B_BUSY 0x80
> #define BT_CTRL_H_BUSY 0x40
> @@ -372,7 +373,7 @@ static void poll_timer(struct timer_list *t)
> add_timer(&bt_bmc->poll_timer);
> }
>
> -static irqreturn_t bt_bmc_irq(int irq, void *arg)
> +static irqreturn_t aspeed_bt_bmc_irq(int irq, void *arg)
> {
> struct bt_bmc *bt_bmc = arg;
> u32 reg;
> @@ -393,7 +394,7 @@ static irqreturn_t bt_bmc_irq(int irq, void *arg)
> return IRQ_HANDLED;
> }
>
> -static int bt_bmc_config_irq(struct bt_bmc *bt_bmc,
> +static int aspeed_bt_bmc_config_irq(struct bt_bmc *bt_bmc,
> struct platform_device *pdev)
> {
> struct device *dev = &pdev->dev;
> @@ -403,7 +404,7 @@ static int bt_bmc_config_irq(struct bt_bmc *bt_bmc,
> if (bt_bmc->irq < 0)
> return bt_bmc->irq;
>
> - rc = devm_request_irq(dev, bt_bmc->irq, bt_bmc_irq, IRQF_SHARED,
> + rc = devm_request_irq(dev, bt_bmc->irq, aspeed_bt_bmc_irq, IRQF_SHARED,
> DEVICE_NAME, bt_bmc);
> if (rc < 0) {
> dev_warn(dev, "Unable to request IRQ %d\n", bt_bmc->irq);
> @@ -424,6 +425,16 @@ static int bt_bmc_config_irq(struct bt_bmc *bt_bmc,
> return rc;
> }
>
> +static void aspeed_enable_bt(struct bt_bmc *bt_bmc)
> +{
> + regmap_write(bt_bmc->map, bt_bmc->offset + BT_CR0,
> + (BT_IO_BASE << BT_CR0_IO_BASE) |
> + (BT_IRQ << BT_CR0_IRQ) |
> + BT_CR0_EN_CLR_SLV_RDP |
> + BT_CR0_EN_CLR_SLV_WRP |
> + BT_CR0_ENABLE_IBT);
> +}
> +
> static int bt_bmc_probe(struct platform_device *pdev)
> {
> struct bt_bmc *bt_bmc;
> @@ -472,7 +483,7 @@ static int bt_bmc_probe(struct platform_device *pdev)
> return rc;
> }
>
> - bt_bmc_config_irq(bt_bmc, pdev);
> + aspeed_bt_bmc_config_irq(bt_bmc, pdev);
>
> if (bt_bmc->irq >= 0) {
> dev_info(dev, "Using IRQ %d\n", bt_bmc->irq);
> @@ -483,12 +494,7 @@ static int bt_bmc_probe(struct platform_device *pdev)
> add_timer(&bt_bmc->poll_timer);
> }
>
> - regmap_write(bt_bmc->map, bt_bmc->offset + BT_CR0,
> - (BT_IO_BASE << BT_CR0_IO_BASE) |
> - (BT_IRQ << BT_CR0_IRQ) |
> - BT_CR0_EN_CLR_SLV_RDP |
> - BT_CR0_EN_CLR_SLV_WRP |
> - BT_CR0_ENABLE_IBT);
> + aspeed_enable_bt(bt_bmc);
>
> clr_b_busy(bt_bmc);
>
>
^ permalink raw reply
* Re: [PATCH 2/4] perf: Add mem_hops field in perf_mem_data_src structure
From: kajoljain @ 2021-10-06 6:38 UTC (permalink / raw)
To: Peter Zijlstra
Cc: mark.rutland, atrajeev, ak, daniel, rnsastry, alexander.shishkin,
linux-kernel, acme, ast, linux-perf-users, yao.jin, mingo, paulus,
maddy, jolsa, namhyung, songliubraving, linuxppc-dev, kan.liang
In-Reply-To: <20211005202015.GC174703@worktop.programming.kicks-ass.net>
On 10/6/21 1:50 AM, Peter Zijlstra wrote:
> On Tue, Oct 05, 2021 at 02:48:35PM +0530, Kajol Jain wrote:
>> Going forward, future generation systems can have more hierarchy
>> within the chip/package level but currently we don't have any data source
>> encoding field in perf, which can be used to represent this level of data.
>>
>> Add a new field called 'mem_hops' in the perf_mem_data_src structure
>> which can be used to represent intra-chip/package or inter-chip/off-package
>> details. This field is of size 3 bits where PERF_MEM_HOPS_{NA, 0..6} value
>> can be used to present different hop levels data.
>>
>> Also add corresponding macros to define mem_hop field values
>> and shift value.
>>
>> Currently we define macro for HOPS_0 which corresponds
>> to data coming from another core but same chip.
>>
>> For ex: Encodings for mem_hops fields with L2 cache:
>>
>> L2 - local L2
>> L2 | REMOTE | HOPS_0 - remote core, same chip L2
>
> Can we do s/chip/node/ ? Hops are something NUMA related, while chips
> come in a bag or something :-)
Hi Peter,
Sure, I will make this change in next version of this patch-set.
Thanks,
Kajol Jain
>
>> +/* hop level */
>> +#define PERF_MEM_HOPS_0 0x01 /* remote core, same chip */
>> +/* 2-7 available */
>> +#define PERF_MEM_HOPS_SHIFT 43
^ permalink raw reply
* [PATCH] perf vendor events power10: Add metric events json file for power10 platform
From: Kajol Jain @ 2021-10-06 7:31 UTC (permalink / raw)
To: acme
Cc: maddy, rnsastry, jolsa, linux-kernel, linux-perf-users, atrajeev,
Kajol Jain, linuxppc-dev
Add pmu metric json file for power10 platform.
Signed-off-by: Kajol Jain <kjain@linux.ibm.com>
---
.../arch/powerpc/power10/metrics.json | 772 ++++++++++++++++++
1 file changed, 772 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/powerpc/power10/metrics.json
diff --git a/tools/perf/pmu-events/arch/powerpc/power10/metrics.json b/tools/perf/pmu-events/arch/powerpc/power10/metrics.json
new file mode 100644
index 000000000000..028c9777a516
--- /dev/null
+++ b/tools/perf/pmu-events/arch/powerpc/power10/metrics.json
@@ -0,0 +1,772 @@
+[
+ {
+ "BriefDescription": "Percentage of cycles that are run cycles",
+ "MetricExpr": "PM_RUN_CYC / PM_CYC * 100",
+ "MetricGroup": "General",
+ "MetricName": "RUN_CYCLES_RATE",
+ "ScaleUnit": "1%"
+ },
+ {
+ "BriefDescription": "Average cycles per completed instruction",
+ "MetricExpr": "PM_CYC / PM_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "CYCLES_PER_INSTRUCTION"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when dispatch was stalled for any reason",
+ "MetricExpr": "PM_DISP_STALL_CYC / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DISPATCHED_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when dispatch was stalled because there was a flush",
+ "MetricExpr": "PM_DISP_STALL_FLUSH / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DISPATCHED_FLUSH_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when dispatch was stalled because the MMU was handling a translation miss",
+ "MetricExpr": "PM_DISP_STALL_TRANSLATION / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DISPATCHED_TRANSLATION_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when dispatch was stalled waiting to resolve an instruction ERAT miss",
+ "MetricExpr": "PM_DISP_STALL_IERAT_ONLY_MISS / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DISPATCHED_IERAT_ONLY_MISS_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when dispatch was stalled waiting to resolve an instruction TLB miss",
+ "MetricExpr": "PM_DISP_STALL_ITLB_MISS / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DISPATCHED_ITLB_MISS_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when dispatch was stalled due to an icache miss",
+ "MetricExpr": "PM_DISP_STALL_IC_MISS / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DISPATCHED_IC_MISS_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when dispatch was stalled while the instruction was fetched form the local L2",
+ "MetricExpr": "PM_DISP_STALL_IC_L2 / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DISPATCHED_IC_L2_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when dispatch was stalled while the instruction was fetched form the local L3",
+ "MetricExpr": "PM_DISP_STALL_IC_L3 / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DISPATCHED_IC_L3_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when dispatch was stalled while the instruction was fetched from any source beyond the local L3",
+ "MetricExpr": "PM_DISP_STALL_IC_L3MISS / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DISPATCHED_IC_L3MISS_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when dispatch was stalled due to an icache miss after a branch mispredict",
+ "MetricExpr": "PM_DISP_STALL_BR_MPRED_ICMISS / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DISPATCHED_BR_MPRED_ICMISS_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when dispatch was stalled while instruction was fetched from the local L2 after suffering a branch mispredict",
+ "MetricExpr": "PM_DISP_STALL_BR_MPRED_IC_L2 / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DISPATCHED_BR_MPRED_IC_L2_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when dispatch was stalled while instruction was fetched from the local L3 after suffering a branch mispredict",
+ "MetricExpr": "PM_DISP_STALL_BR_MPRED_IC_L3 / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DISPATCHED_BR_MPRED_IC_L3_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when dispatch was stalled while instruction was fetched from any source beyond the local L3 after suffering a branch mispredict",
+ "MetricExpr": "PM_DISP_STALL_BR_MPRED_IC_L3MISS / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DISPATCHED_BR_MPRED_IC_L3MISS_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when dispatch was stalled due to a branch mispredict",
+ "MetricExpr": "PM_DISP_STALL_BR_MPRED / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DISPATCHED_BR_MPRED_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the ntc instruction was held at dispatch for any reason",
+ "MetricExpr": "PM_DISP_STALL_HELD_CYC / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DISPATCHED_HELD_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the ntc instruction was held at dispatch because of a synchronizing instruction that requires the ICT to be empty before dispatch",
+ "MetricExpr": "PM_DISP_STALL_HELD_SYNC_CYC / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DISP_HELD_STALL_SYNC_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the ntc instruction was held at dispatch while waiting on the scoreboard",
+ "MetricExpr": "PM_DISP_STALL_HELD_SCOREBOARD_CYC / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DISP_HELD_STALL_SCOREBOARD_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the ntc instruction was held at dispatch due to issue q full",
+ "MetricExpr": "PM_DISP_STALL_HELD_ISSQ_FULL_CYC / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DISP_HELD_STALL_ISSQ_FULL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the ntc instruction was held at dispatch because the mapper/SRB was full",
+ "MetricExpr": "PM_DISP_STALL_HELD_RENAME_CYC / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DISPATCHED_HELD_RENAME_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the ntc instruction was held at dispatch because the STF mapper/SRB was full",
+ "MetricExpr": "PM_DISP_STALL_HELD_STF_MAPPER_CYC / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DISPATCHED_HELD_STF_MAPPER_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the ntc instruction was held at dispatch because the XVFC mapper/SRB was full",
+ "MetricExpr": "PM_DISP_STALL_HELD_XVFC_MAPPER_CYC / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DISPATCHED_HELD_XVFC_MAPPER_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the ntc instruction was held at dispatch for any other reason",
+ "MetricExpr": "PM_DISP_STALL_HELD_OTHER_CYC / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DISPATCHED_HELD_OTHER_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the ntc instruction has been dispatched but not issued for any reason",
+ "MetricExpr": "PM_ISSUE_STALL / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "ISSUE_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the ntc instruction is waiting to be finished in one of the execution units",
+ "MetricExpr": "PM_EXEC_STALL / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "EXECUTION_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction spent executing an NTC instruction that gets flushed some time after dispatch",
+ "MetricExpr": "PM_EXEC_STALL_NTC_FLUSH / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "NTC_FLUSH_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the instruction finishes at dispatch",
+ "MetricExpr": "PM_EXEC_STALL_FIN_AT_DISP / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "FIN_AT_DISP_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the ntc instruction is executing in the branch unit",
+ "MetricExpr": "PM_EXEC_STALL_BRU / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "BRU_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the ntc instruction is a simple fixed point instr that is executing in the lsu unit",
+ "MetricExpr": "PM_EXEC_STALL_SIMPLE_FX / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "SIMPLE_FX_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the ntc instruction is executing in the vsu unit",
+ "MetricExpr": "PM_EXEC_STALL_VSU / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "VSU_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the ntc instruction is waiting to be finished in one of the execution units",
+ "MetricExpr": "PM_EXEC_STALL_TRANSLATION / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "TRANSLATION_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the ntc instruction is a load or store that suffered a translation miss",
+ "MetricExpr": "PM_EXEC_STALL_DERAT_ONLY_MISS / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DERAT_ONLY_MISS_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the ntc instruction is recovering from a TLB miss",
+ "MetricExpr": "PM_EXEC_STALL_DERAT_DTLB_MISS / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DERAT_DTLB_MISS_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the ntc instruction is executing in the lsu unit",
+ "MetricExpr": "PM_EXEC_STALL_LSU / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "LSU_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the ntc instruction is a load that is executing in the lsu unit",
+ "MetricExpr": "PM_EXEC_STALL_LOAD / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "LOAD_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the ntc instruction is waiting for a load miss to resolve from either the local L2 or local L3",
+ "MetricExpr": "PM_EXEC_STALL_DMISS_L2L3 / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DMISS_L2L3_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the ntc instruction is waiting for a load miss to resolve from either the local L2 or local L3, with an RC dispatch conflict",
+ "MetricExpr": "PM_EXEC_STALL_DMISS_L2L3_CONFLICT / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DMISS_L2L3_CONFLICT_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the ntc instruction is waiting for a load miss to resolve from either the local L2 or local L3, without an RC dispatch conflict",
+ "MetricExpr": "PM_EXEC_STALL_DMISS_L2L3_NOCONFLICT / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DMISS_L2L3_NOCONFLICT_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the ntc instruction is waiting for a load miss to resolve from a source beyond the local L2 and local L3",
+ "MetricExpr": "PM_EXEC_STALL_DMISS_L3MISS / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DMISS_L3MISS_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the ntc instruction is waiting for a load miss to resolve from a neighbor chiplet's L2 or L3 in the same chip",
+ "MetricExpr": "PM_EXEC_STALL_DMISS_L21_L31 / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DMISS_L21_L31_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the ntc instruction is waiting for a load miss to resolve from local memory, L4 or OpenCapp chip",
+ "MetricExpr": "PM_EXEC_STALL_DMISS_LMEM / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DMISS_LMEM_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the ntc instruction is waiting for a load miss to resolve from a remote chip (cache, L4, memory or CAPP) in the same group",
+ "MetricExpr": "PM_EXEC_STALL_DMISS_OFF_CHIP / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DMISS_OFF_CHIP_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the ntc instruction is waiting for a load miss to resolve from a distant chip (cache, L4, memory or CAPP chip)",
+ "MetricExpr": "PM_EXEC_STALL_DMISS_OFF_NODE / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DMISS_OFF_NODE_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the ntc instruction is executing a TLBIEL instruction",
+ "MetricExpr": "PM_EXEC_STALL_TLBIEL / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "TLBIEL_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the ntc instruction is finishing a load after its data has been reloaded from a data source beyond the local L1, OR when the LSU is processing an L1-hit, OR when the NTF instruction merged with another load in the LMQ",
+ "MetricExpr": "PM_EXEC_STALL_LOAD_FINISH / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "LOAD_FINISH_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the ntc instruction is a store that is executing in the lsu unit",
+ "MetricExpr": "PM_EXEC_STALL_STORE / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "STORE_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the ntc instruction is in the store unit outside of handling store misses or other special store operations",
+ "MetricExpr": "PM_EXEC_STALL_STORE_PIPE / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "STORE_PIPE_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the ntc instruction is a store whose cache line was not resident in the L1 and had to wait for allocation of the missing line into the L1",
+ "MetricExpr": "PM_EXEC_STALL_STORE_MISS / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "STORE_MISS_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the ntc instruction is a TLBIE instruction waiting for a response from the L2",
+ "MetricExpr": "PM_EXEC_STALL_TLBIE / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "TLBIE_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the ntc instruction is executing a PTESYNC instruction",
+ "MetricExpr": "PM_EXEC_STALL_PTESYNC / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "PTESYNC_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the ntc instruction cannot complete because the thread was blocked",
+ "MetricExpr": "PM_CMPL_STALL / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "COMPLETION_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the ntc instruction cannot complete because it was interrupted by ANY exception",
+ "MetricExpr": "PM_CMPL_STALL_EXCEPTION / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "EXCEPTION_COMPLETION_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the ntc instruction is stuck at finish waiting for the non-speculative finish of either a stcx waiting for its result or a load waiting for non-critical sectors of data and ECC",
+ "MetricExpr": "PM_CMPL_STALL_MEM_ECC / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "MEM_ECC_COMPLETION_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the ntc instruction cannot complete the instruction is a stcx waiting for resolution from the nest",
+ "MetricExpr": "PM_CMPL_STALL_STCX / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "STCX_COMPLETION_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the ntc instruction is a LWSYNC instruction waiting to complete",
+ "MetricExpr": "PM_CMPL_STALL_LWSYNC / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "LWSYNC_COMPLETION_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the ntc instruction is a HWSYNC instruction stuck at finish waiting for a response from the L2",
+ "MetricExpr": "PM_CMPL_STALL_HWSYNC / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "HWSYNC_COMPLETION_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the ntc instruction required special handling before completion",
+ "MetricExpr": "PM_CMPL_STALL_SPECIAL / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "SPECIAL_COMPLETION_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Should equal 0. If not, disp_stall_translation or children are miscounting",
+ "MetricExpr": "DISPATCHED_TRANSLATION_CPI - (DISPATCHED_IERAT_ONLY_MISS_CPI + DISPATCHED_ITLB_MISS_CPI)",
+ "MetricGroup": "CPI",
+ "MetricName": "OTHER_DISPATCHED_TRANSLATION_CPI"
+ },
+ {
+ "BriefDescription": "Should equal 0. If not, disp_stall_ic_miss or children are miscounting",
+ "MetricExpr": "DISPATCHED_IC_MISS_CPI - (DISPATCHED_IC_L2_CPI + DISPATCHED_IC_L3_CPI + DISPATCHED_IC_L3MISS_CPI)",
+ "MetricGroup": "CPI",
+ "MetricName": "OTHER_DISPATCHED_IC_MISS_CPI"
+ },
+ {
+ "BriefDescription": "Should equal 0. If not, disp_stall_br_mpred_icmiss or children are miscounting",
+ "MetricExpr": "DISPATCHED_BR_MPRED_ICMISS_CPI - (DISPATCHED_BR_MPRED_IC_L2_CPI + DISPATCHED_BR_MPRED_IC_L3_CPI + DISPATCHED_BR_MPRED_IC_L3MISS_CPI)",
+ "MetricGroup": "CPI",
+ "MetricName": "OTHER_DISPATCHED_BR_MPRED_ICMISS_CPI"
+ },
+ {
+ "BriefDescription": "Should equal 0. If not, disp_stall_held_rename or children are miscounting",
+ "MetricExpr": "DISPATCHED_HELD_RENAME_CPI - (DISPATCHED_HELD_STF_MAPPER_CPI + DISPATCHED_HELD_XVFC_MAPPER_CPI)",
+ "MetricGroup": "CPI",
+ "MetricName": "OTHER_DISPATCHED_HELD_RENAME_CPI"
+ },
+ {
+ "BriefDescription": "Should equal 0. If not, disp_stall_held or children are miscounting",
+ "MetricExpr": "DISPATCHED_HELD_CPI - (DISP_HELD_STALL_SYNC_CPI + DISP_HELD_STALL_SCOREBOARD_CPI + DISP_HELD_STALL_ISSQ_FULL_CPI + DISPATCHED_HELD_RENAME_CPI + DISPATCHED_HELD_OTHER_CPI + DISPATCHED_HELD_HALT_CPI)",
+ "MetricGroup": "CPI",
+ "MetricName": "OTHER_DISPATCHED_HELD_CPI"
+ },
+ {
+ "BriefDescription": "Should equal 0. If not, disp_stall or children are miscounting",
+ "MetricExpr": "DISPATCHED_CPI - (DISPATCHED_FLUSH_CPI + DISPATCHED_TRANSLATION_CPI + DISPATCHED_IC_MISS_CPI + DISPATCHED_BR_MPRED_ICMISS_CPI + DISPATCHED_BR_MPRED_CPI + DISPATCHED_HELD_CPI)",
+ "MetricGroup": "CPI",
+ "MetricName": "OTHER_DISPATCHED_CPI"
+ },
+ {
+ "BriefDescription": "Should equal 0. If not, exec_stall_translation or children are miscounting",
+ "MetricExpr": "TRANSLATION_STALL_CPI - (DERAT_ONLY_MISS_STALL_CPI + DERAT_DTLB_MISS_STALL_CPI)",
+ "MetricGroup": "CPI",
+ "MetricName": "OTHER_TRANSLATION_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Should equal 0. If not, exec_stall_dmiss_l2l3 or children are miscounting",
+ "MetricExpr": "DMISS_L2L3_STALL_CPI - (DMISS_L2L3_CONFLICT_STALL_CPI + DMISS_L2L3_NOCONFLICT_STALL_CPI)",
+ "MetricGroup": "CPI",
+ "MetricName": "OTHER_DMISS_L2L3_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Should equal 0. If not, exec_stall_dmiss_l3miss or children are miscounting",
+ "MetricExpr": "DMISS_L3MISS_STALL_CPI - (DMISS_L21_L31_STALL_CPI + DMISS_LMEM_STALL_CPI + DMISS_OFF_CHIP_STALL_CPI + DMISS_OFF_NODE_STALL_CPI)",
+ "MetricGroup": "CPI",
+ "MetricName": "OTHER_DMISS_L3MISS_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Should equal 0. If not, exec_stall_load or children are miscounting",
+ "MetricExpr": "LOAD_STALL_CPI - (DMISS_L2L3_STALL_CPI + DMISS_L3MISS_STALL_CPI + TLBIEL_STALL_CPI + LOAD_FINISH_STALL_CPI)",
+ "MetricGroup": "CPI",
+ "MetricName": "OTHER_LOAD_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Should equal 0. If not, exec_stall_store or children are miscounting",
+ "MetricExpr": "STORE_STALL_CPI - (STORE_PIPE_STALL_CPI + STORE_MISS_STALL_CPI + TLBIE_STALL_CPI + PTESYNC_STALL_CPI)",
+ "MetricGroup": "CPI",
+ "MetricName": "OTHER_STORE_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Should equal 0. If not, exec_stall_lsu or children are miscounting",
+ "MetricExpr": "LSU_STALL_CPI - (LOAD_STALL_CPI + STORE_STALL_CPI)",
+ "MetricGroup": "CPI",
+ "MetricName": "OTHER_LSU_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Should equal 0. If not, cmpl_stall or children are miscounting",
+ "MetricExpr": "COMPLETION_STALL_CPI - (EXCEPTION_COMPLETION_STALL_CPI + MEM_ECC_COMPLETION_STALL_CPI + STCX_COMPLETION_STALL_CPI + LWSYNC_COMPLETION_STALL_CPI + HWSYNC_COMPLETION_STALL_CPI + SPECIAL_COMPLETION_STALL_CPI)",
+ "MetricGroup": "CPI",
+ "MetricName": "OTHER_COMPLETION_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Should equal 0. If not, exec_stall or children are miscounting",
+ "MetricExpr": "EXECUTION_STALL_CPI - (NTC_FLUSH_STALL_CPI + FIN_AT_DISP_STALL_CPI + BRU_STALL_CPI + SIMPLE_FX_STALL_CPI + VSU_STALL_CPI + TRANSLATION_STALL_CPI + LSU_STALL_CPI)",
+ "MetricGroup": "CPI",
+ "MetricName": "OTHER_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Should equal 0. If not, pm_cyc or children are miscounting",
+ "MetricExpr": "CYCLES_PER_INSTRUCTION - (DISPATCHED_CPI + ISSUE_STALL_CPI + EXECUTION_STALL_CPI + COMPLETION_STALL_CPI)",
+ "MetricGroup": "CPI",
+ "MetricName": "OTHER_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when dispatch was stalled because Fetch was being held, so there was nothing in the pipeline for this thread",
+ "MetricExpr": "PM_DISP_STALL_FETCH / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DISPATCHED_FETCH_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the ntc instruction was held at dispatch because of power management",
+ "MetricExpr": "PM_DISP_STALL_HELD_HALT_CYC / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DISPATCHED_HELD_HALT_CPI"
+ },
+ {
+ "BriefDescription": "Percentage of flushes per completed instruction",
+ "MetricExpr": "PM_FLUSH / PM_RUN_INST_CMPL * 100",
+ "MetricGroup": "Others",
+ "MetricName": "FLUSH_RATE",
+ "ScaleUnit": "1%"
+ },
+ {
+ "BriefDescription": "Percentage of flushes due to a branch mispredict per instruction",
+ "MetricExpr": "PM_FLUSH_MPRED / PM_RUN_INST_CMPL * 100",
+ "MetricGroup": "Others",
+ "MetricName": "BR_MPRED_FLUSH_RATE",
+ "ScaleUnit": "1%"
+ },
+ {
+ "BriefDescription": "Percentage of branch mispredictions per completed instruction",
+ "MetricExpr": "PM_BR_MPRED_CMPL / PM_RUN_INST_CMPL",
+ "MetricGroup": "Others",
+ "MetricName": "BRANCH_MISPREDICTION_RATE"
+ },
+ {
+ "BriefDescription": "Percentage of finished loads that missed in the L1",
+ "MetricExpr": "PM_LD_MISS_L1 / PM_LD_REF_L1 * 100",
+ "MetricGroup": "Others",
+ "MetricName": "L1_LD_MISS_RATIO",
+ "ScaleUnit": "1%"
+ },
+ {
+ "BriefDescription": "Percentage of completed instructions that were loads that missed the L1",
+ "MetricExpr": "PM_LD_MISS_L1 / PM_RUN_INST_CMPL * 100",
+ "MetricGroup": "Others",
+ "MetricName": "L1_LD_MISS_RATE",
+ "ScaleUnit": "1%"
+ },
+ {
+ "BriefDescription": "Percentage of instructions when the DPTEG required for the load/store instruction in execution was missing from the TLB",
+ "MetricExpr": "PM_DTLB_MISS / PM_RUN_INST_CMPL * 100",
+ "MetricGroup": "Others",
+ "MetricName": "DTLB_MISS_RATE",
+ "ScaleUnit": "1%"
+ },
+ {
+ "BriefDescription": "Average number of instruction dispatched per instruction completed",
+ "MetricExpr": "PM_INST_DISP / PM_RUN_INST_CMPL",
+ "MetricGroup": "General",
+ "MetricName": "DISPATCH_PER_INST_CMPL"
+ },
+ {
+ "BriefDescription": "Percentage of completed instructions that were a demand load that did not hit in the L1 or L2",
+ "MetricExpr": "PM_DATA_FROM_L2MISS / PM_RUN_INST_CMPL * 100",
+ "MetricGroup": "General",
+ "MetricName": "L2_LD_MISS_RATE",
+ "ScaleUnit": "1%"
+ },
+ {
+ "BriefDescription": "Percentage of completed instructions that were demand fetches that missed the L1 instruction cache",
+ "MetricExpr": "PM_L1_ICACHE_MISS / PM_RUN_INST_CMPL * 100",
+ "MetricGroup": "Instruction_Misses",
+ "MetricName": "L1_INST_MISS_RATE",
+ "ScaleUnit": "1%"
+ },
+ {
+ "BriefDescription": "Percentage of completed instructions that were demand fetches that reloaded from beyond the L3 instruction cache",
+ "MetricExpr": "PM_INST_FROM_L3MISS / PM_RUN_INST_CMPL * 100",
+ "MetricGroup": "General",
+ "MetricName": "L3_INST_MISS_RATE",
+ "ScaleUnit": "1%"
+ },
+ {
+ "BriefDescription": "Average number of completed instructions per cycle",
+ "MetricExpr": "PM_INST_CMPL / PM_CYC",
+ "MetricGroup": "General",
+ "MetricName": "IPC"
+ },
+ {
+ "BriefDescription": "Average number of cycles per completed instruction group",
+ "MetricExpr": "PM_CYC / PM_1PLUS_PPC_CMPL",
+ "MetricGroup": "General",
+ "MetricName": "CYCLES_PER_COMPLETED_INSTRUCTIONS_SET"
+ },
+ {
+ "BriefDescription": "Percentage of cycles when at least 1 instruction dispatched",
+ "MetricExpr": "PM_1PLUS_PPC_DISP / PM_RUN_CYC * 100",
+ "MetricGroup": "General",
+ "MetricName": "CYCLES_ATLEAST_ONE_INST_DISPATCHED",
+ "ScaleUnit": "1%"
+ },
+ {
+ "BriefDescription": "Rate of finished loads per completed instruction",
+ "MetricExpr": "PM_LD_REF_L1 / PM_RUN_INST_CMPL",
+ "MetricGroup": "General",
+ "MetricName": "LOADS_PER_INST"
+ },
+ {
+ "BriefDescription": "Rate of finished stores per completed instruction",
+ "MetricExpr": "PM_ST_FIN / PM_RUN_INST_CMPL",
+ "MetricGroup": "General",
+ "MetricName": "STORES_PER_INST"
+ },
+ {
+ "BriefDescription": "Percentage of demand loads that reloaded from beyond the L2 per completed instruction",
+ "MetricExpr": "PM_DATA_FROM_L2MISS / PM_RUN_INST_CMPL * 100",
+ "MetricGroup": "dL1_Reloads",
+ "MetricName": "DL1_RELOAD_FROM_L2_MISS_RATE",
+ "ScaleUnit": "1%"
+ },
+ {
+ "BriefDescription": "Percentage of demand loads that reloaded from beyond the L3 per completed instruction",
+ "MetricExpr": "PM_DATA_FROM_L3MISS / PM_RUN_INST_CMPL * 100",
+ "MetricGroup": "dL1_Reloads",
+ "MetricName": "DL1_RELOAD_FROM_L3_MISS_RATE",
+ "ScaleUnit": "1%"
+ },
+ {
+ "BriefDescription": "Percentage of DERAT misses with 4k page size per completed run instruction",
+ "MetricExpr": "PM_DERAT_MISS_4K / PM_RUN_INST_CMPL * 100",
+ "MetricGroup": "Translation",
+ "MetricName": "DERAT_4K_MISS_RATE",
+ "ScaleUnit": "1%"
+ },
+ {
+ "BriefDescription": "Percentage of DERAT misses with 64k page size per completed run instruction",
+ "MetricExpr": "PM_DERAT_MISS_64K / PM_RUN_INST_CMPL * 100",
+ "MetricGroup": "Translation",
+ "MetricName": "DERAT_64K_MISS_RATE",
+ "ScaleUnit": "1%"
+ },
+ {
+ "BriefDescription": "Average number of run cycles per completed run instruction",
+ "MetricExpr": "PM_RUN_CYC / PM_RUN_INST_CMPL",
+ "MetricGroup": "General",
+ "MetricName": "RUN_CPI"
+ },
+ {
+ "BriefDescription": "Total number of run cycles",
+ "MetricExpr": "PM_RUN_CYC",
+ "MetricGroup": "General",
+ "MetricName": "TOTAL_RUN_CYCLES"
+ },
+ {
+ "BriefDescription": "Percentage of DERAT misses per completed run instruction",
+ "MetricExpr": "PM_DERAT_MISS / PM_RUN_INST_CMPL * 100",
+ "MetricGroup": "Translation",
+ "MetricName": "DERAT_MISS_RATE",
+ "ScaleUnit": "1%"
+ },
+ {
+ "BriefDescription": "Average number of completed run instructions per run cycle",
+ "MetricExpr": "PM_RUN_INST_CMPL / PM_RUN_CYC",
+ "MetricGroup": "General",
+ "MetricName": "RUN_IPC"
+ },
+ {
+ "BriefDescription": "Average number of instruction completed per instruction group",
+ "MetricExpr": "PM_RUN_INST_CMPL / PM_1PLUS_PPC_CMPL",
+ "MetricGroup": "General",
+ "MetricName": "AVERAGE_COMPLETED_INSTRUCTION_SET_SIZE"
+ },
+ {
+ "BriefDescription": "Rate of finished instructions per completed instructions",
+ "MetricExpr": "PM_INST_FIN / PM_RUN_INST_CMPL",
+ "MetricGroup": "General",
+ "MetricName": "INST_FIN_PER_CMPL"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the ntf instruction is completing and the finish was overlooked",
+ "MetricExpr": "PM_EXEC_STALL_UNKNOWN / PM_RUN_INST_CMPL",
+ "MetricGroup": "General",
+ "MetricName": "EXEC_STALL_UNKOWN_CPI"
+ },
+ {
+ "BriefDescription": "Percentage of finished branches that were taken",
+ "MetricExpr": "PM_BR_TAKEN_CMPL / PM_BR_FIN * 100",
+ "MetricGroup": "General",
+ "MetricName": "TAKEN_BRANCHES",
+ "ScaleUnit": "1%"
+ },
+ {
+ "BriefDescription": "Percentage of completed instructions that were a demand load that did not hit in the L1, L2, or the L3",
+ "MetricExpr": "PM_DATA_FROM_L3MISS / PM_RUN_INST_CMPL * 100",
+ "MetricGroup": "General",
+ "MetricName": "L3_LD_MISS_RATE",
+ "ScaleUnit": "1%"
+ },
+ {
+ "BriefDescription": "Rate of finished branches per completed instruction",
+ "MetricExpr": "PM_BR_FIN / PM_RUN_INST_CMPL",
+ "MetricGroup": "General",
+ "MetricName": "BRANCHES_PER_INST"
+ },
+ {
+ "BriefDescription": "Rate of instructions finished in the LSU per completed instruction",
+ "MetricExpr": "PM_LSU_FIN / PM_RUN_INST_CMPL",
+ "MetricGroup": "General",
+ "MetricName": "LSU_PER_INST"
+ },
+ {
+ "BriefDescription": "Rate of instructions finished in the VSU per completed instruction",
+ "MetricExpr": "PM_VSU_FIN / PM_RUN_INST_CMPL",
+ "MetricGroup": "General",
+ "MetricName": "VSU_PER_INST"
+ },
+ {
+ "BriefDescription": "Rate of TLBIE instructions finished in the LSU per completed instruction",
+ "MetricExpr": "PM_TLBIE_FIN / PM_RUN_INST_CMPL",
+ "MetricGroup": "General",
+ "MetricName": "TLBIE_PER_INST"
+ },
+ {
+ "BriefDescription": "Rate of STCX instructions finshed per completed instruction",
+ "MetricExpr": "PM_STCX_FIN / PM_RUN_INST_CMPL",
+ "MetricGroup": "General",
+ "MetricName": "STXC_PER_INST"
+ },
+ {
+ "BriefDescription": "Rate of LARX instructions finshed per completed instruction",
+ "MetricExpr": "PM_LARX_FIN / PM_RUN_INST_CMPL",
+ "MetricGroup": "General",
+ "MetricName": "LARX_PER_INST"
+ },
+ {
+ "BriefDescription": "Rate of ptesync instructions finshed per completed instruction",
+ "MetricExpr": "PM_PTESYNC_FIN / PM_RUN_INST_CMPL",
+ "MetricGroup": "General",
+ "MetricName": "PTESYNC_PER_INST"
+ },
+ {
+ "BriefDescription": "Rate of simple fixed-point instructions finshed in the store unit per completed instruction",
+ "MetricExpr": "PM_FX_LSU_FIN / PM_RUN_INST_CMPL",
+ "MetricGroup": "General",
+ "MetricName": "FX_PER_INST"
+ },
+ {
+ "BriefDescription": "Percentage of demand load misses that reloaded the L1 cache",
+ "MetricExpr": "PM_LD_DEMAND_MISS_L1 / PM_LD_MISS_L1 * 100",
+ "MetricGroup": "General",
+ "MetricName": "DL1_MISS_RELOADS",
+ "ScaleUnit": "1%"
+ },
+ {
+ "BriefDescription": "Percentage of demand load misses that reloaded from beyond the local L2",
+ "MetricExpr": "PM_DATA_FROM_L2MISS / PM_LD_DEMAND_MISS_L1 * 100",
+ "MetricGroup": "dL1_Reloads",
+ "MetricName": "DL1_RELOAD_FROM_L2_MISS",
+ "ScaleUnit": "1%"
+ },
+ {
+ "BriefDescription": "Percentage of demand load misses that reloaded from beyond the local L3",
+ "MetricExpr": "PM_DATA_FROM_L3MISS / PM_LD_DEMAND_MISS_L1 * 100",
+ "MetricGroup": "dL1_Reloads",
+ "MetricName": "DL1_RELOAD_FROM_L3_MISS",
+ "ScaleUnit": "1%"
+ },
+ {
+ "BriefDescription": "Percentage of cycles stalled due to the ntc instruction waiting for a load miss to resolve from a source beyond the local L2 and local L3",
+ "MetricExpr": "DMISS_L3MISS_STALL_CPI / RUN_CPI * 100",
+ "MetricGroup": "General",
+ "MetricName": "DCACHE_MISS_CPI",
+ "ScaleUnit": "1%"
+ },
+ {
+ "BriefDescription": "Percentage of DERAT misses with 2M page size per completed run instruction",
+ "MetricExpr": "PM_DERAT_MISS_2M / PM_RUN_INST_CMPL * 100",
+ "MetricGroup": "Translation",
+ "MetricName": "DERAT_2M_MISS_RATE",
+ "ScaleUnit": "1%"
+ },
+ {
+ "BriefDescription": "Percentage of DERAT misses with 16M page size per completed run instruction",
+ "MetricExpr": "PM_DERAT_MISS_16M / PM_RUN_INST_CMPL * 100",
+ "MetricGroup": "Translation",
+ "MetricName": "DERAT_16M_MISS_RATE",
+ "ScaleUnit": "1%"
+ },
+ {
+ "BriefDescription": "DERAT miss ratio for 4K page size",
+ "MetricExpr": "PM_DERAT_MISS_4K / PM_DERAT_MISS",
+ "MetricGroup": "Translation",
+ "MetricName": "DERAT_4K_MISS_RATIO"
+ },
+ {
+ "BriefDescription": "DERAT miss ratio for 2M page size",
+ "MetricExpr": "PM_DERAT_MISS_2M / PM_DERAT_MISS",
+ "MetricGroup": "Translation",
+ "MetricName": "DERAT_2M_MISS_RATIO"
+ },
+ {
+ "BriefDescription": "DERAT miss ratio for 16M page size",
+ "MetricExpr": "PM_DERAT_MISS_16M / PM_DERAT_MISS",
+ "MetricGroup": "Translation",
+ "MetricName": "DERAT_16M_MISS_RATIO"
+ },
+ {
+ "BriefDescription": "DERAT miss ratio for 64K page size",
+ "MetricExpr": "PM_DERAT_MISS_64K / PM_DERAT_MISS",
+ "MetricGroup": "Translation",
+ "MetricName": "DERAT_64K_MISS_RATIO"
+ },
+ {
+ "BriefDescription": "Percentage of DERAT misses that resulted in TLB reloads",
+ "MetricExpr": "PM_DTLB_MISS / PM_DERAT_MISS * 100",
+ "MetricGroup": "Translation",
+ "MetricName": "DERAT_MISS_RELOAD",
+ "ScaleUnit": "1%"
+ },
+ {
+ "BriefDescription": "Percentage of ICache misses that were reloaded from beyond the local L3",
+ "MetricExpr": "PM_INST_FROM_L3MISS / PM_L1_ICACHE_MISS * 100",
+ "MetricGroup": "Instruction_Misses",
+ "MetricName": "INST_FROM_L3_MISS",
+ "ScaleUnit": "1%"
+ },
+ {
+ "BriefDescription": "Percentage of ICache reloads from the beyond the L3 per completed run instruction",
+ "MetricExpr": "PM_INST_FROM_L3MISS / PM_RUN_INST_CMPL * 100",
+ "MetricGroup": "Instruction_Misses",
+ "MetricName": "INST_FROM_L3_MISS_RATE",
+ "ScaleUnit": "1%"
+ }
+]
--
2.27.0
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