* Re: [PATCH] soc: fsl: guts: Fix a resource leak in the error handling path of 'fsl_guts_probe()'
From: Li Yang @ 2021-10-22 0:26 UTC (permalink / raw)
To: Christophe JAILLET
Cc: kernel-janitors, linuxppc-dev, lkml,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
In-Reply-To: <b12e8c5c5d6ab3061d9504de8fbaefcad6bbc385.1629321668.git.christophe.jaillet@wanadoo.fr>
On Wed, Aug 18, 2021 at 4:23 PM Christophe JAILLET
<christophe.jaillet@wanadoo.fr> wrote:
>
> If an error occurs after 'of_find_node_by_path()', the reference taken for
> 'root' will never be released and some memory will leak.
Thanks for finding this. This truly is a problem.
>
> Instead of adding an error handling path and modifying all the
> 'return -SOMETHING' into 'goto errorpath', use 'devm_add_action_or_reset()'
> to release the reference when needed.
>
> Simplify the remove function accordingly.
>
> As an extra benefit, the 'root' global variable can now be removed as well.
>
> Fixes: 3c0d64e867ed ("soc: fsl: guts: reuse machine name from device tree")
> Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
> ---
> Compile tested only
> ---
> drivers/soc/fsl/guts.c | 16 ++++++++++++++--
> 1 file changed, 14 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/soc/fsl/guts.c b/drivers/soc/fsl/guts.c
> index d5e9a5f2c087..4d9476c7b87c 100644
> --- a/drivers/soc/fsl/guts.c
> +++ b/drivers/soc/fsl/guts.c
> @@ -28,7 +28,6 @@ struct fsl_soc_die_attr {
> static struct guts *guts;
> static struct soc_device_attribute soc_dev_attr;
> static struct soc_device *soc_dev;
> -static struct device_node *root;
>
>
> /* SoC die attribute definition for QorIQ platform */
> @@ -136,14 +135,23 @@ static u32 fsl_guts_get_svr(void)
> return svr;
> }
>
> +static void fsl_guts_put_root(void *data)
> +{
> + struct device_node *root = data;
> +
> + of_node_put(root);
> +}
> +
> static int fsl_guts_probe(struct platform_device *pdev)
> {
> struct device_node *np = pdev->dev.of_node;
> struct device *dev = &pdev->dev;
> + struct device_node *root;
> struct resource *res;
> const struct fsl_soc_die_attr *soc_die;
> const char *machine;
> u32 svr;
> + int ret;
>
> /* Initialize guts */
> guts = devm_kzalloc(dev, sizeof(*guts), GFP_KERNEL);
> @@ -159,6 +167,10 @@ static int fsl_guts_probe(struct platform_device *pdev)
>
> /* Register soc device */
> root = of_find_node_by_path("/");
> + ret = devm_add_action_or_reset(dev, fsl_guts_put_root, root);
> + if (ret)
> + return ret;
We probably only need to hold the reference when we do get "machine"
from the device tree, otherwise we can put it directly.
Or maybe we just maintain a local copy of string machine which means
we can release the reference right away?
> +
> if (of_property_read_string(root, "model", &machine))
> of_property_read_string_index(root, "compatible", 0, &machine);
> if (machine)
> @@ -197,7 +209,7 @@ static int fsl_guts_probe(struct platform_device *pdev)
> static int fsl_guts_remove(struct platform_device *dev)
> {
> soc_device_unregister(soc_dev);
> - of_node_put(root);
> +
> return 0;
> }
>
> --
> 2.30.2
>
^ permalink raw reply
* Re: [PATCH 1/2] soc: fsl: guts: Make use of the helper function devm_platform_ioremap_resource()
From: Li Yang @ 2021-10-22 0:34 UTC (permalink / raw)
To: Cai Huoqing
Cc: linuxppc-dev, lkml,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
In-Reply-To: <20210908071631.660-1-caihuoqing@baidu.com>
On Wed, Sep 8, 2021 at 2:19 AM Cai Huoqing <caihuoqing@baidu.com> wrote:
>
> Use the devm_platform_ioremap_resource() helper instead of
> calling platform_get_resource() and devm_ioremap_resource()
> separately
>
> Signed-off-by: Cai Huoqing <caihuoqing@baidu.com>
Applied for next. Thanks.
> ---
> drivers/soc/fsl/guts.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/drivers/soc/fsl/guts.c b/drivers/soc/fsl/guts.c
> index d5e9a5f2c087..072473a16f4d 100644
> --- a/drivers/soc/fsl/guts.c
> +++ b/drivers/soc/fsl/guts.c
> @@ -140,7 +140,6 @@ static int fsl_guts_probe(struct platform_device *pdev)
> {
> struct device_node *np = pdev->dev.of_node;
> struct device *dev = &pdev->dev;
> - struct resource *res;
> const struct fsl_soc_die_attr *soc_die;
> const char *machine;
> u32 svr;
> @@ -152,8 +151,7 @@ static int fsl_guts_probe(struct platform_device *pdev)
>
> guts->little_endian = of_property_read_bool(np, "little-endian");
>
> - res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> - guts->regs = devm_ioremap_resource(dev, res);
> + guts->regs = devm_platform_ioremap_resource(pdev, 0);
> if (IS_ERR(guts->regs))
> return PTR_ERR(guts->regs);
>
> --
> 2.25.1
>
^ permalink raw reply
* Re: [PATCH 2/2] soc: fsl: rcpm: Make use of the helper function devm_platform_ioremap_resource()
From: Li Yang @ 2021-10-22 0:37 UTC (permalink / raw)
To: Cai Huoqing
Cc: linuxppc-dev, lkml,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
In-Reply-To: <20210908071631.660-2-caihuoqing@baidu.com>
On Wed, Sep 8, 2021 at 2:20 AM Cai Huoqing <caihuoqing@baidu.com> wrote:
>
> Use the devm_platform_ioremap_resource() helper instead of
> calling platform_get_resource() and devm_ioremap_resource()
> separately
>
> Signed-off-by: Cai Huoqing <caihuoqing@baidu.com>
Applied for next. Thanks.
> ---
> drivers/soc/fsl/rcpm.c | 7 +------
> 1 file changed, 1 insertion(+), 6 deletions(-)
>
> diff --git a/drivers/soc/fsl/rcpm.c b/drivers/soc/fsl/rcpm.c
> index 90d3f4060b0c..3d0cae30c769 100644
> --- a/drivers/soc/fsl/rcpm.c
> +++ b/drivers/soc/fsl/rcpm.c
> @@ -146,7 +146,6 @@ static const struct dev_pm_ops rcpm_pm_ops = {
> static int rcpm_probe(struct platform_device *pdev)
> {
> struct device *dev = &pdev->dev;
> - struct resource *r;
> struct rcpm *rcpm;
> int ret;
>
> @@ -154,11 +153,7 @@ static int rcpm_probe(struct platform_device *pdev)
> if (!rcpm)
> return -ENOMEM;
>
> - r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> - if (!r)
> - return -ENODEV;
> -
> - rcpm->ippdexpcr_base = devm_ioremap_resource(&pdev->dev, r);
> + rcpm->ippdexpcr_base = devm_platform_ioremap_resource(pdev, 0);
> if (IS_ERR(rcpm->ippdexpcr_base)) {
> ret = PTR_ERR(rcpm->ippdexpcr_base);
> return ret;
> --
> 2.25.1
>
^ permalink raw reply
* Re: [PATCH 00/13] block: add_disk() error handling stragglers
From: Geoff Levand @ 2021-10-22 3:10 UTC (permalink / raw)
To: Luis Chamberlain
Cc: nvdimm, vigneshr, linux-nvme, paulus, miquel.raynal, ira.weiny,
hch, dave.jiang, sagi, minchan, vishal.l.verma, ngupta,
linux-block, kbusch, dan.j.williams, axboe, linux-kernel, jim,
senozhatsky, richard, linux-mtd, linuxppc-dev
In-Reply-To: <YW2duaTqf3qUbTIm@bombadil.infradead.org>
Hi Luis,
On 10/18/21 9:15 AM, Luis Chamberlain wrote:
> On Sun, Oct 17, 2021 at 08:26:33AM -0700, Geoff Levand wrote:
>> Hi Luis,
>>
>> On 10/15/21 4:52 PM, Luis Chamberlain wrote:
>>> This patch set consists of al the straggler drivers for which we have
>>> have no patch reviews done for yet. I'd like to ask for folks to please
>>> consider chiming in, specially if you're the maintainer for the driver.
>>> Additionally if you can specify if you'll take the patch in yourself or
>>> if you want Jens to take it, that'd be great too.
>>
>> Do you have a git repo with the patch set applied that I can use to test with?
>
> Sure, although the second to last patch is in a state of flux given
> the ataflop driver currently is broken and so we're seeing how to fix
> that first:
>
> https://git.kernel.org/pub/scm/linux/kernel/git/mcgrof/linux-next.git/log/?h=20211011-for-axboe-add-disk-error-handling
That branch has so many changes applied on top of the base v5.15-rc4
that the patches I need to apply to test on PS3 with don't apply.
Do you have something closer to say v5.15-rc5? Preferred would be
just your add_disk() error handling patches plus what they depend
on.
Thanks.
-Geoff
^ permalink raw reply
* Re: [PATCH V2] powerpc/perf: Enable PMU counters post partition migration if PMU is active
From: Madhavan Srinivasan @ 2021-10-22 3:33 UTC (permalink / raw)
To: Nathan Lynch, Nicholas Piggin, Athira Rajeev, mpe
Cc: kjain, linuxppc-dev, rnsastry
In-Reply-To: <87ilxqxoxy.fsf@linux.ibm.com>
On 10/21/21 11:03 PM, Nathan Lynch wrote:
> Nicholas Piggin <npiggin@gmail.com> writes:
>> Excerpts from Athira Rajeev's message of July 11, 2021 10:25 pm:
>>> During Live Partition Migration (LPM), it is observed that perf
>>> counter values reports zero post migration completion. However
>>> 'perf stat' with workload continues to show counts post migration
>>> since PMU gets disabled/enabled during sched switches. But incase
>>> of system/cpu wide monitoring, zero counts were reported with 'perf
>>> stat' after migration completion.
>>>
>>> Example:
>>> ./perf stat -e r1001e -I 1000
>>> time counts unit events
>>> 1.001010437 22,137,414 r1001e
>>> 2.002495447 15,455,821 r1001e
>>> <<>> As seen in next below logs, the counter values shows zero
>>> after migration is completed.
>>> <<>>
>>> 86.142535370 129,392,333,440 r1001e
>>> 87.144714617 0 r1001e
>>> 88.146526636 0 r1001e
>>> 89.148085029 0 r1001e
>>>
>>> Here PMU is enabled during start of perf session and counter
>>> values are read at intervals. Counters are only disabled at the
>>> end of session. The powerpc mobility code presently does not handle
>>> disabling and enabling back of PMU counters during partition
>>> migration. Also since the PMU register values are not saved/restored
>>> during migration, PMU registers like Monitor Mode Control Register 0
>>> (MMCR0), Monitor Mode Control Register 1 (MMCR1) will not contain
>>> the value it was programmed with. Hence PMU counters will not be
>>> enabled correctly post migration.
>>>
>>> Fix this in mobility code by handling disabling and enabling of
>>> PMU in all cpu's before and after migration. Patch introduces two
>>> functions 'mobility_pmu_disable' and 'mobility_pmu_enable'.
>>> mobility_pmu_disable() is called before the processor threads goes
>>> to suspend state so as to disable the PMU counters. And disable is
>>> done only if there are any active events running on that cpu.
>>> mobility_pmu_enable() is called after the processor threads are
>>> back online to enable back the PMU counters.
>>>
>>> Since the performance Monitor counters ( PMCs) are not
>>> saved/restored during LPM, results in PMC value being zero and the
>>> 'event->hw.prev_count' being non-zero value. This causes problem
>> Interesting. Are they defined to not be migrated, or may not be
>> migrated?
> PAPR may be silent on this... at least I haven't found anything yet. But
> I'm not very familiar with perf counters.
IIUC, from the internal discussion with pHYP, migration of counters is
OS thing.
> How much assurance do we have that hardware events we've programmed on
> the source can be reliably re-enabled on the destination, with the same
> semantics? Aren't there some model-specific counters that don't make
> sense to handle this way?
migration to same generation processor/model should be ok
but not to the different generation/model (but it is a case
to handle). That said, this patch is to fix the issue of large
value seen when migrating.
>
>
>>> diff --git a/arch/powerpc/include/asm/rtas.h b/arch/powerpc/include/asm/rtas.h
>>> index 9dc97d2..cea72d7 100644
>>> --- a/arch/powerpc/include/asm/rtas.h
>>> +++ b/arch/powerpc/include/asm/rtas.h
>>> @@ -380,5 +380,13 @@ static inline void rtas_initialize(void) { }
>>> static inline void read_24x7_sys_info(void) { }
>>> #endif
>>>
>>> +#ifdef CONFIG_PPC_PERF_CTRS
>>> +void mobility_pmu_disable(void);
>>> +void mobility_pmu_enable(void);
>>> +#else
>>> +static inline void mobility_pmu_disable(void) { }
>>> +static inline void mobility_pmu_enable(void) { }
>>> +#endif
>>> +
>>> #endif /* __KERNEL__ */
>>> #endif /* _POWERPC_RTAS_H */
>> It's not implemented in rtas, maybe consider putting this into a perf
>> header?
> +1
>
^ permalink raw reply
* Re: [GIT PULL] Please pull powerpc/linux.git powerpc-5.15-5 tag
From: pr-tracker-bot @ 2021-10-22 5:10 UTC (permalink / raw)
To: Michael Ellerman; +Cc: nathanl, linuxppc-dev, Linus Torvalds, linux-kernel
In-Reply-To: <877de6d34y.fsf@mpe.ellerman.id.au>
The pull request you sent on Thu, 21 Oct 2021 22:32:45 +1100:
> https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git tags/powerpc-5.15-5
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/0a3221b65874b5089f1742de59ef89f032b9f2ea
Thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/prtracker.html
^ permalink raw reply
* Re: [PATCH V2] powerpc/perf: Enable PMU counters post partition migration if PMU is active
From: Nicholas Piggin @ 2021-10-22 5:11 UTC (permalink / raw)
To: Athira Rajeev, Michael Ellerman, Nathan Lynch
Cc: kjain, maddy, linuxppc-dev, rnsastry
In-Reply-To: <874k99di81.fsf@mpe.ellerman.id.au>
Excerpts from Michael Ellerman's message of October 22, 2021 10:19 am:
> Nathan Lynch <nathanl@linux.ibm.com> writes:
>> Athira Rajeev <atrajeev@linux.vnet.ibm.com> writes:
>>> During Live Partition Migration (LPM), it is observed that perf
>>> counter values reports zero post migration completion. However
>>> 'perf stat' with workload continues to show counts post migration
>>> since PMU gets disabled/enabled during sched switches. But incase
>>> of system/cpu wide monitoring, zero counts were reported with 'perf
>>> stat' after migration completion.
>>>
>>> Example:
>>> ./perf stat -e r1001e -I 1000
>>> time counts unit events
>>> 1.001010437 22,137,414 r1001e
>>> 2.002495447 15,455,821 r1001e
>>> <<>> As seen in next below logs, the counter values shows zero
>>> after migration is completed.
>>> <<>>
>>> 86.142535370 129,392,333,440 r1001e
>>> 87.144714617 0 r1001e
>>> 88.146526636 0 r1001e
>>> 89.148085029 0 r1001e
>>
>> Confirmed in my environment:
>>
>> 51.099987985 300,338 cache-misses
>> 52.101839374 296,586 cache-misses
>> 53.116089796 263,150 cache-misses
>> 54.117949249 232,290 cache-misses
>> 55.602029375 68,700,421,711 cache-misses
>> 56.610073969 0 cache-misses
>> 57.614732000 0 cache-misses
>>
>> I wonder what it means that there is a very unlikely huge value before
>> the counter stops working -- I believe your example has this phenomenon
>> too.
>
> AFAICS the patch is not reading the PMC values before the migration, so
My suggested change I think should take care of that.
Thanks,
Nick
^ permalink raw reply
* [PATCH v2] powerpc: flexible GPR range save/restore macros
From: Nicholas Piggin @ 2021-10-22 6:13 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Nicholas Piggin
Introduce macros that operate on a (start, end) range of GPRs, which
reduces lines of code and need to do mental arithmetic while reading the
code.
Reviewed-by: Segher Boessenkool <segher@kernel.crashing.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
Since v1:
- Removed unused OP_REG_IDX macro
- Commented OP_REG macro
arch/powerpc/boot/crt0.S | 31 +++++++------
arch/powerpc/crypto/md5-asm.S | 10 ++---
arch/powerpc/crypto/sha1-powerpc-asm.S | 6 +--
arch/powerpc/include/asm/ppc_asm.h | 43 ++++++++++++-------
arch/powerpc/kernel/entry_32.S | 23 ++++------
arch/powerpc/kernel/exceptions-64e.S | 14 ++----
arch/powerpc/kernel/exceptions-64s.S | 6 +--
arch/powerpc/kernel/head_32.h | 3 +-
arch/powerpc/kernel/head_booke.h | 3 +-
arch/powerpc/kernel/interrupt_64.S | 34 ++++++---------
arch/powerpc/kernel/optprobes_head.S | 4 +-
arch/powerpc/kernel/tm.S | 15 ++-----
.../powerpc/kernel/trace/ftrace_64_mprofile.S | 15 +++----
arch/powerpc/kvm/book3s_hv_rmhandlers.S | 5 +--
.../lib/test_emulate_step_exec_instr.S | 8 ++--
15 files changed, 94 insertions(+), 126 deletions(-)
diff --git a/arch/powerpc/boot/crt0.S b/arch/powerpc/boot/crt0.S
index 1d83966f5ef6..e8f10a599659 100644
--- a/arch/powerpc/boot/crt0.S
+++ b/arch/powerpc/boot/crt0.S
@@ -226,16 +226,19 @@ p_base: mflr r10 /* r10 now points to runtime addr of p_base */
#ifdef __powerpc64__
#define PROM_FRAME_SIZE 512
-#define SAVE_GPR(n, base) std n,8*(n)(base)
-#define REST_GPR(n, base) ld n,8*(n)(base)
-#define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
-#define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
-#define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
-#define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
-#define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
-#define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
-#define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
-#define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
+
+.macro OP_REGS op, width, start, end, base, offset
+ .Lreg=\start
+ .rept (\end - \start + 1)
+ \op .Lreg,\offset+\width*.Lreg(\base)
+ .Lreg=.Lreg+1
+ .endr
+.endm
+
+#define SAVE_GPRS(start, end, base) OP_REGS std, 8, start, end, base, 0
+#define REST_GPRS(start, end, base) OP_REGS ld, 8, start, end, base, 0
+#define SAVE_GPR(n, base) SAVE_GPRS(n, n, base)
+#define REST_GPR(n, base) REST_GPRS(n, n, base)
/* prom handles the jump into and return from firmware. The prom args pointer
is loaded in r3. */
@@ -246,9 +249,7 @@ prom:
stdu r1,-PROM_FRAME_SIZE(r1) /* Save SP and create stack space */
SAVE_GPR(2, r1)
- SAVE_GPR(13, r1)
- SAVE_8GPRS(14, r1)
- SAVE_10GPRS(22, r1)
+ SAVE_GPRS(13, 31, r1)
mfcr r10
std r10,8*32(r1)
mfmsr r10
@@ -283,9 +284,7 @@ prom:
/* Restore other registers */
REST_GPR(2, r1)
- REST_GPR(13, r1)
- REST_8GPRS(14, r1)
- REST_10GPRS(22, r1)
+ REST_GPRS(13, 31, r1)
ld r10,8*32(r1)
mtcr r10
diff --git a/arch/powerpc/crypto/md5-asm.S b/arch/powerpc/crypto/md5-asm.S
index 948d100a2934..fa6bc440cf4a 100644
--- a/arch/powerpc/crypto/md5-asm.S
+++ b/arch/powerpc/crypto/md5-asm.S
@@ -38,15 +38,11 @@
#define INITIALIZE \
PPC_STLU r1,-INT_FRAME_SIZE(r1); \
- SAVE_8GPRS(14, r1); /* push registers onto stack */ \
- SAVE_4GPRS(22, r1); \
- SAVE_GPR(26, r1)
+ SAVE_GPRS(14, 26, r1) /* push registers onto stack */
#define FINALIZE \
- REST_8GPRS(14, r1); /* pop registers from stack */ \
- REST_4GPRS(22, r1); \
- REST_GPR(26, r1); \
- addi r1,r1,INT_FRAME_SIZE;
+ REST_GPRS(14, 26, r1); /* pop registers from stack */ \
+ addi r1,r1,INT_FRAME_SIZE
#ifdef __BIG_ENDIAN__
#define LOAD_DATA(reg, off) \
diff --git a/arch/powerpc/crypto/sha1-powerpc-asm.S b/arch/powerpc/crypto/sha1-powerpc-asm.S
index 23e248beff71..f0d5ed557ab1 100644
--- a/arch/powerpc/crypto/sha1-powerpc-asm.S
+++ b/arch/powerpc/crypto/sha1-powerpc-asm.S
@@ -125,8 +125,7 @@
_GLOBAL(powerpc_sha_transform)
PPC_STLU r1,-INT_FRAME_SIZE(r1)
- SAVE_8GPRS(14, r1)
- SAVE_10GPRS(22, r1)
+ SAVE_GPRS(14, 31, r1)
/* Load up A - E */
lwz RA(0),0(r3) /* A */
@@ -184,7 +183,6 @@ _GLOBAL(powerpc_sha_transform)
stw RD(0),12(r3)
stw RE(0),16(r3)
- REST_8GPRS(14, r1)
- REST_10GPRS(22, r1)
+ REST_GPRS(14, 31, r1)
addi r1,r1,INT_FRAME_SIZE
blr
diff --git a/arch/powerpc/include/asm/ppc_asm.h b/arch/powerpc/include/asm/ppc_asm.h
index 1c538a9a11e0..fe6cb940d136 100644
--- a/arch/powerpc/include/asm/ppc_asm.h
+++ b/arch/powerpc/include/asm/ppc_asm.h
@@ -16,30 +16,41 @@
#define SZL (BITS_PER_LONG/8)
+/*
+ * This expands to a sequence of operations with reg incrementing from
+ * start to end inclusive, of this form:
+ *
+ * op reg, (offset + (width * reg))(base)
+ *
+ * Note that offset is not the offset of the first operation unless start
+ * is zero (or width is zero).
+ */
+.macro OP_REGS op, width, start, end, base, offset
+ .Lreg=\start
+ .rept (\end - \start + 1)
+ \op .Lreg, \offset + \width * .Lreg(\base)
+ .Lreg=.Lreg+1
+ .endr
+.endm
+
/*
* Macros for storing registers into and loading registers from
* exception frames.
*/
#ifdef __powerpc64__
-#define SAVE_GPR(n, base) std n,GPR0+8*(n)(base)
-#define REST_GPR(n, base) ld n,GPR0+8*(n)(base)
-#define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)
-#define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base)
+#define SAVE_GPRS(start, end, base) OP_REGS std, 8, start, end, base, GPR0
+#define REST_GPRS(start, end, base) OP_REGS ld, 8, start, end, base, GPR0
+#define SAVE_NVGPRS(base) SAVE_GPRS(14, 31, base)
+#define REST_NVGPRS(base) REST_GPRS(14, 31, base)
#else
-#define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base)
-#define REST_GPR(n, base) lwz n,GPR0+4*(n)(base)
-#define SAVE_NVGPRS(base) stmw 13, GPR0+4*13(base)
-#define REST_NVGPRS(base) lmw 13, GPR0+4*13(base)
+#define SAVE_GPRS(start, end, base) OP_REGS stw, 4, start, end, base, GPR0
+#define REST_GPRS(start, end, base) OP_REGS lwz, 4, start, end, base, GPR0
+#define SAVE_NVGPRS(base) stmw 13, GPR0+4*13(base)
+#define REST_NVGPRS(base) lmw 13, GPR0+4*13(base)
#endif
-#define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
-#define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
-#define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
-#define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
-#define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
-#define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
-#define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
-#define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
+#define SAVE_GPR(n, base) SAVE_GPRS(n, n, base)
+#define REST_GPR(n, base) REST_GPRS(n, n, base)
#define SAVE_FPR(n, base) stfd n,8*TS_FPRWIDTH*(n)(base)
#define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base)
diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S
index 61fdd53cdd9a..c62dd9815965 100644
--- a/arch/powerpc/kernel/entry_32.S
+++ b/arch/powerpc/kernel/entry_32.S
@@ -90,8 +90,7 @@ transfer_to_syscall:
stw r12,8(r1)
stw r2,_TRAP(r1)
SAVE_GPR(0, r1)
- SAVE_4GPRS(3, r1)
- SAVE_2GPRS(7, r1)
+ SAVE_GPRS(3, 8, r1)
addi r2,r10,-THREAD
SAVE_NVGPRS(r1)
@@ -139,7 +138,7 @@ syscall_exit_finish:
mtxer r5
lwz r0,GPR0(r1)
lwz r3,GPR3(r1)
- REST_8GPRS(4,r1)
+ REST_GPRS(4, 11, r1)
lwz r12,GPR12(r1)
b 1b
@@ -232,9 +231,9 @@ fast_exception_return:
beq 3f /* if not, we've got problems */
#endif
-2: REST_4GPRS(3, r11)
+2: REST_GPRS(3, 6, r11)
lwz r10,_CCR(r11)
- REST_2GPRS(1, r11)
+ REST_GPRS(1, 2, r11)
mtcr r10
lwz r10,_LINK(r11)
mtlr r10
@@ -298,16 +297,14 @@ ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
* the reliable stack unwinder later on. Clear it.
*/
stw r0,8(r1)
- REST_4GPRS(7, r1)
- REST_2GPRS(11, r1)
+ REST_GPRS(7, 12, r1)
mtcr r3
mtlr r4
mtctr r5
mtspr SPRN_XER,r6
- REST_4GPRS(2, r1)
- REST_GPR(6, r1)
+ REST_GPRS(2, 6, r1)
REST_GPR(0, r1)
REST_GPR(1, r1)
rfi
@@ -341,8 +338,7 @@ ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
lwz r6,_CCR(r1)
li r0,0
- REST_4GPRS(7, r1)
- REST_2GPRS(11, r1)
+ REST_GPRS(7, 12, r1)
mtlr r3
mtctr r4
@@ -354,7 +350,7 @@ ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
*/
stw r0,8(r1)
- REST_4GPRS(2, r1)
+ REST_GPRS(2, 5, r1)
bne- cr1,1f /* emulate stack store */
mtcr r6
@@ -430,8 +426,7 @@ _ASM_NOKPROBE_SYMBOL(interrupt_return)
bne interrupt_return; \
lwz r0,GPR0(r1); \
lwz r2,GPR2(r1); \
- REST_4GPRS(3, r1); \
- REST_2GPRS(7, r1); \
+ REST_GPRS(3, 8, r1); \
lwz r10,_XER(r1); \
lwz r11,_CTR(r1); \
mtspr SPRN_XER,r10; \
diff --git a/arch/powerpc/kernel/exceptions-64e.S b/arch/powerpc/kernel/exceptions-64e.S
index 711c66b76df1..67dc4e3179a0 100644
--- a/arch/powerpc/kernel/exceptions-64e.S
+++ b/arch/powerpc/kernel/exceptions-64e.S
@@ -198,8 +198,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
stdcx. r0,0,r1 /* to clear the reservation */
- REST_4GPRS(2, r1)
- REST_4GPRS(6, r1)
+ REST_GPRS(2, 9, r1)
ld r10,_CTR(r1)
ld r11,_XER(r1)
@@ -375,9 +374,7 @@ ret_from_mc_except:
exc_##n##_common: \
std r0,GPR0(r1); /* save r0 in stackframe */ \
std r2,GPR2(r1); /* save r2 in stackframe */ \
- SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
- SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
- std r9,GPR9(r1); /* save r9 in stackframe */ \
+ SAVE_GPRS(3, 9, r1); /* save r3 - r9 in stackframe */ \
std r10,_NIP(r1); /* save SRR0 to stackframe */ \
std r11,_MSR(r1); /* save SRR1 to stackframe */ \
beq 2f; /* if from kernel mode */ \
@@ -1061,9 +1058,7 @@ bad_stack_book3e:
std r11,_ESR(r1)
std r0,GPR0(r1); /* save r0 in stackframe */ \
std r2,GPR2(r1); /* save r2 in stackframe */ \
- SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
- SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
- std r9,GPR9(r1); /* save r9 in stackframe */ \
+ SAVE_GPRS(3, 9, r1); /* save r3 - r9 in stackframe */ \
ld r3,PACA_EXGEN+EX_R10(r13);/* get back r10 */ \
ld r4,PACA_EXGEN+EX_R11(r13);/* get back r11 */ \
mfspr r5,SPRN_SPRG_GEN_SCRATCH;/* get back r13 XXX can be wrong */ \
@@ -1077,8 +1072,7 @@ bad_stack_book3e:
std r10,_LINK(r1)
std r11,_CTR(r1)
std r12,_XER(r1)
- SAVE_10GPRS(14,r1)
- SAVE_8GPRS(24,r1)
+ SAVE_GPRS(14, 31, r1)
lhz r12,PACA_TRAP_SAVE(r13)
std r12,_TRAP(r1)
addi r11,r1,INT_FRAME_SIZE
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index eaf1f72131a1..277eccf0f086 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -574,8 +574,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
ld r10,IAREA+EX_CTR(r13)
std r10,_CTR(r1)
std r2,GPR2(r1) /* save r2 in stackframe */
- SAVE_4GPRS(3, r1) /* save r3 - r6 in stackframe */
- SAVE_2GPRS(7, r1) /* save r7, r8 in stackframe */
+ SAVE_GPRS(3, 8, r1) /* save r3 - r8 in stackframe */
mflr r9 /* Get LR, later save to stack */
ld r2,PACATOC(r13) /* get kernel TOC into r2 */
std r9,_LINK(r1)
@@ -693,8 +692,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
mtlr r9
ld r9,_CCR(r1)
mtcr r9
- REST_8GPRS(2, r1)
- REST_4GPRS(10, r1)
+ REST_GPRS(2, 13, r1)
REST_GPR(0, r1)
/* restore original r1. */
ld r1,GPR1(r1)
diff --git a/arch/powerpc/kernel/head_32.h b/arch/powerpc/kernel/head_32.h
index 6b1ec9e3541b..25887303651a 100644
--- a/arch/powerpc/kernel/head_32.h
+++ b/arch/powerpc/kernel/head_32.h
@@ -115,8 +115,7 @@ _ASM_NOKPROBE_SYMBOL(\name\()_virt)
stw r10,8(r1)
li r10, \trapno
stw r10,_TRAP(r1)
- SAVE_4GPRS(3, r1)
- SAVE_2GPRS(7, r1)
+ SAVE_GPRS(3, 8, r1)
SAVE_NVGPRS(r1)
stw r2,GPR2(r1)
stw r12,_NIP(r1)
diff --git a/arch/powerpc/kernel/head_booke.h b/arch/powerpc/kernel/head_booke.h
index e5503420b6c6..0ae26396639d 100644
--- a/arch/powerpc/kernel/head_booke.h
+++ b/arch/powerpc/kernel/head_booke.h
@@ -87,8 +87,7 @@ END_BTB_FLUSH_SECTION
stw r10, 8(r1)
li r10, \trapno
stw r10,_TRAP(r1)
- SAVE_4GPRS(3, r1)
- SAVE_2GPRS(7, r1)
+ SAVE_GPRS(3, 8, r1)
SAVE_NVGPRS(r1)
stw r2,GPR2(r1)
stw r12,_NIP(r1)
diff --git a/arch/powerpc/kernel/interrupt_64.S b/arch/powerpc/kernel/interrupt_64.S
index ec950b08a8dc..2ad223597ca2 100644
--- a/arch/powerpc/kernel/interrupt_64.S
+++ b/arch/powerpc/kernel/interrupt_64.S
@@ -162,10 +162,9 @@ END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
* The value of AMR only matters while we're in the kernel.
*/
mtcr r2
- ld r2,GPR2(r1)
- ld r3,GPR3(r1)
- ld r13,GPR13(r1)
- ld r1,GPR1(r1)
+ REST_GPRS(2, 3, r1)
+ REST_GPR(13, r1)
+ REST_GPR(1, r1)
RFSCV_TO_USER
b . /* prevent speculative execution */
@@ -183,9 +182,8 @@ END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
mtctr r3
mtlr r4
mtspr SPRN_XER,r5
- REST_10GPRS(2, r1)
- REST_2GPRS(12, r1)
- ld r1,GPR1(r1)
+ REST_GPRS(2, 13, r1)
+ REST_GPR(1, r1)
RFI_TO_USER
.Lsyscall_vectored_\name\()_rst_end:
@@ -374,10 +372,9 @@ END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
* The value of AMR only matters while we're in the kernel.
*/
mtcr r2
- ld r2,GPR2(r1)
- ld r3,GPR3(r1)
- ld r13,GPR13(r1)
- ld r1,GPR1(r1)
+ REST_GPRS(2, 3, r1)
+ REST_GPR(13, r1)
+ REST_GPR(1, r1)
RFI_TO_USER
b . /* prevent speculative execution */
@@ -388,8 +385,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
mtctr r3
mtspr SPRN_XER,r4
ld r0,GPR0(r1)
- REST_8GPRS(4, r1)
- ld r12,GPR12(r1)
+ REST_GPRS(4, 12, r1)
b .Lsyscall_restore_regs_cont
.Lsyscall_rst_end:
@@ -518,17 +514,14 @@ ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
ld r6,_XER(r1)
li r0,0
- REST_4GPRS(7, r1)
- REST_2GPRS(11, r1)
- REST_GPR(13, r1)
+ REST_GPRS(7, 13, r1)
mtcr r3
mtlr r4
mtctr r5
mtspr SPRN_XER,r6
- REST_4GPRS(2, r1)
- REST_GPR(6, r1)
+ REST_GPRS(2, 6, r1)
REST_GPR(0, r1)
REST_GPR(1, r1)
.ifc \srr,srr
@@ -625,8 +618,7 @@ ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
ld r6,_CCR(r1)
li r0,0
- REST_4GPRS(7, r1)
- REST_2GPRS(11, r1)
+ REST_GPRS(7, 12, r1)
mtlr r3
mtctr r4
@@ -638,7 +630,7 @@ ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
*/
std r0,STACK_FRAME_OVERHEAD-16(r1)
- REST_4GPRS(2, r1)
+ REST_GPRS(2, 5, r1)
bne- cr1,1f /* emulate stack store */
mtcr r6
diff --git a/arch/powerpc/kernel/optprobes_head.S b/arch/powerpc/kernel/optprobes_head.S
index 19ea3312403c..5c7f0b4b784b 100644
--- a/arch/powerpc/kernel/optprobes_head.S
+++ b/arch/powerpc/kernel/optprobes_head.S
@@ -10,8 +10,8 @@
#include <asm/asm-offsets.h>
#ifdef CONFIG_PPC64
-#define SAVE_30GPRS(base) SAVE_10GPRS(2,base); SAVE_10GPRS(12,base); SAVE_10GPRS(22,base)
-#define REST_30GPRS(base) REST_10GPRS(2,base); REST_10GPRS(12,base); REST_10GPRS(22,base)
+#define SAVE_30GPRS(base) SAVE_GPRS(2, 31, base)
+#define REST_30GPRS(base) REST_GPRS(2, 31, base)
#define TEMPLATE_FOR_IMM_LOAD_INSNS nop; nop; nop; nop; nop
#else
#define SAVE_30GPRS(base) stmw r2, GPR2(base)
diff --git a/arch/powerpc/kernel/tm.S b/arch/powerpc/kernel/tm.S
index 2b91f233b05d..3beecc32940b 100644
--- a/arch/powerpc/kernel/tm.S
+++ b/arch/powerpc/kernel/tm.S
@@ -226,11 +226,8 @@ _GLOBAL(tm_reclaim)
/* Sync the userland GPRs 2-12, 14-31 to thread->regs: */
SAVE_GPR(0, r7) /* user r0 */
- SAVE_GPR(2, r7) /* user r2 */
- SAVE_4GPRS(3, r7) /* user r3-r6 */
- SAVE_GPR(8, r7) /* user r8 */
- SAVE_GPR(9, r7) /* user r9 */
- SAVE_GPR(10, r7) /* user r10 */
+ SAVE_GPRS(2, 6, r7) /* user r2-r6 */
+ SAVE_GPRS(8, 10, r7) /* user r8-r10 */
ld r3, GPR1(r1) /* user r1 */
ld r4, GPR7(r1) /* user r7 */
ld r5, GPR11(r1) /* user r11 */
@@ -445,12 +442,8 @@ restore_gprs:
ld r6, THREAD_TM_PPR(r3)
REST_GPR(0, r7) /* GPR0 */
- REST_2GPRS(2, r7) /* GPR2-3 */
- REST_GPR(4, r7) /* GPR4 */
- REST_4GPRS(8, r7) /* GPR8-11 */
- REST_2GPRS(12, r7) /* GPR12-13 */
-
- REST_NVGPRS(r7) /* GPR14-31 */
+ REST_GPRS(2, 4, r7) /* GPR2-4 */
+ REST_GPRS(8, 31, r7) /* GPR8-31 */
/* Load up PPR and DSCR here so we don't run with user values for long */
mtspr SPRN_DSCR, r5
diff --git a/arch/powerpc/kernel/trace/ftrace_64_mprofile.S b/arch/powerpc/kernel/trace/ftrace_64_mprofile.S
index f9fd5f743eba..d636fc755f60 100644
--- a/arch/powerpc/kernel/trace/ftrace_64_mprofile.S
+++ b/arch/powerpc/kernel/trace/ftrace_64_mprofile.S
@@ -41,15 +41,14 @@ _GLOBAL(ftrace_regs_caller)
/* Save all gprs to pt_regs */
SAVE_GPR(0, r1)
- SAVE_10GPRS(2, r1)
+ SAVE_GPRS(2, 11, r1)
/* Ok to continue? */
lbz r3, PACA_FTRACE_ENABLED(r13)
cmpdi r3, 0
beq ftrace_no_trace
- SAVE_10GPRS(12, r1)
- SAVE_10GPRS(22, r1)
+ SAVE_GPRS(12, 31, r1)
/* Save previous stack pointer (r1) */
addi r8, r1, SWITCH_FRAME_SIZE
@@ -108,10 +107,8 @@ ftrace_regs_call:
#endif
/* Restore gprs */
- REST_GPR(0,r1)
- REST_10GPRS(2,r1)
- REST_10GPRS(12,r1)
- REST_10GPRS(22,r1)
+ REST_GPR(0, r1)
+ REST_GPRS(2, 31, r1)
/* Restore possibly modified LR */
ld r0, _LINK(r1)
@@ -157,7 +154,7 @@ _GLOBAL(ftrace_caller)
stdu r1, -SWITCH_FRAME_SIZE(r1)
/* Save all gprs to pt_regs */
- SAVE_8GPRS(3, r1)
+ SAVE_GPRS(3, 10, r1)
lbz r3, PACA_FTRACE_ENABLED(r13)
cmpdi r3, 0
@@ -194,7 +191,7 @@ ftrace_call:
mtctr r3
/* Restore gprs */
- REST_8GPRS(3,r1)
+ REST_GPRS(3, 10, r1)
/* Restore callee's TOC */
ld r2, 24(r1)
diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
index eb776d0c5d8e..28be10db895d 100644
--- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S
+++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
@@ -2711,8 +2711,7 @@ kvmppc_bad_host_intr:
std r0, GPR0(r1)
std r9, GPR1(r1)
std r2, GPR2(r1)
- SAVE_4GPRS(3, r1)
- SAVE_2GPRS(7, r1)
+ SAVE_GPRS(3, 8, r1)
srdi r0, r12, 32
clrldi r12, r12, 32
std r0, _CCR(r1)
@@ -2735,7 +2734,7 @@ kvmppc_bad_host_intr:
ld r9, HSTATE_SCRATCH2(r13)
ld r12, HSTATE_SCRATCH0(r13)
GET_SCRATCH0(r0)
- SAVE_4GPRS(9, r1)
+ SAVE_GPRS(9, 12, r1)
std r0, GPR13(r1)
SAVE_NVGPRS(r1)
ld r5, HSTATE_CFAR(r13)
diff --git a/arch/powerpc/lib/test_emulate_step_exec_instr.S b/arch/powerpc/lib/test_emulate_step_exec_instr.S
index 9ef941d958d8..5473f9d03df3 100644
--- a/arch/powerpc/lib/test_emulate_step_exec_instr.S
+++ b/arch/powerpc/lib/test_emulate_step_exec_instr.S
@@ -37,7 +37,7 @@ _GLOBAL(exec_instr)
* The stack pointer (GPR1) and the thread pointer (GPR13) are not
* saved as these should not be modified anyway.
*/
- SAVE_2GPRS(2, r1)
+ SAVE_GPRS(2, 3, r1)
SAVE_NVGPRS(r1)
/*
@@ -75,8 +75,7 @@ _GLOBAL(exec_instr)
/* Load GPRs from pt_regs */
REST_GPR(0, r31)
- REST_10GPRS(2, r31)
- REST_GPR(12, r31)
+ REST_GPRS(2, 12, r31)
REST_NVGPRS(r31)
/* Placeholder for the test instruction */
@@ -99,8 +98,7 @@ _GLOBAL(exec_instr)
subi r3, r3, GPR0
SAVE_GPR(0, r3)
SAVE_GPR(2, r3)
- SAVE_8GPRS(4, r3)
- SAVE_GPR(12, r3)
+ SAVE_GPRS(4, 12, r3)
SAVE_NVGPRS(r3)
/* Save resulting LR to pt_regs */
--
2.23.0
^ permalink raw reply related
* [PATCH v2] perf vendor events power10: Add metric events json file for power10 platform
From: Kajol Jain @ 2021-10-22 6:25 UTC (permalink / raw)
To: acme
Cc: atrajeev, rnsastry, linuxppc-dev, linux-kernel, linux-perf-users,
maddy, pc, kjain, jolsa
Add pmu metric json file for power10 platform.
Signed-off-by: Kajol Jain <kjain@linux.ibm.com>
---
Changelog v1 -> v2:
- Did some nit changes in BriefDescription field
as suggested by Paul A. Clarke
- Link to the v1 patch: https://lkml.org/lkml/2021/10/6/131
.../arch/powerpc/power10/metrics.json | 676 ++++++++++++++++++
1 file changed, 676 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/powerpc/power10/metrics.json
diff --git a/tools/perf/pmu-events/arch/powerpc/power10/metrics.json b/tools/perf/pmu-events/arch/powerpc/power10/metrics.json
new file mode 100644
index 000000000000..8adab5cd9934
--- /dev/null
+++ b/tools/perf/pmu-events/arch/powerpc/power10/metrics.json
@@ -0,0 +1,676 @@
+[
+ {
+ "BriefDescription": "Percentage of cycles that are run cycles",
+ "MetricExpr": "PM_RUN_CYC / PM_CYC * 100",
+ "MetricGroup": "General",
+ "MetricName": "RUN_CYCLES_RATE",
+ "ScaleUnit": "1%"
+ },
+ {
+ "BriefDescription": "Average cycles per completed instruction",
+ "MetricExpr": "PM_CYC / PM_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "CYCLES_PER_INSTRUCTION"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when dispatch was stalled for any reason",
+ "MetricExpr": "PM_DISP_STALL_CYC / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DISPATCHED_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when dispatch was stalled because there was a flush",
+ "MetricExpr": "PM_DISP_STALL_FLUSH / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DISPATCHED_FLUSH_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when dispatch was stalled because the MMU was handling a translation miss",
+ "MetricExpr": "PM_DISP_STALL_TRANSLATION / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DISPATCHED_TRANSLATION_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when dispatch was stalled waiting to resolve an instruction ERAT miss",
+ "MetricExpr": "PM_DISP_STALL_IERAT_ONLY_MISS / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DISPATCHED_IERAT_ONLY_MISS_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when dispatch was stalled waiting to resolve an instruction TLB miss",
+ "MetricExpr": "PM_DISP_STALL_ITLB_MISS / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DISPATCHED_ITLB_MISS_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when dispatch was stalled due to an icache miss",
+ "MetricExpr": "PM_DISP_STALL_IC_MISS / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DISPATCHED_IC_MISS_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when dispatch was stalled while the instruction was fetched from the local L2",
+ "MetricExpr": "PM_DISP_STALL_IC_L2 / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DISPATCHED_IC_L2_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when dispatch was stalled while the instruction was fetched from the local L3",
+ "MetricExpr": "PM_DISP_STALL_IC_L3 / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DISPATCHED_IC_L3_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when dispatch was stalled while the instruction was fetched from any source beyond the local L3",
+ "MetricExpr": "PM_DISP_STALL_IC_L3MISS / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DISPATCHED_IC_L3MISS_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when dispatch was stalled due to an icache miss after a branch mispredict",
+ "MetricExpr": "PM_DISP_STALL_BR_MPRED_ICMISS / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DISPATCHED_BR_MPRED_ICMISS_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when dispatch was stalled while instruction was fetched from the local L2 after suffering a branch mispredict",
+ "MetricExpr": "PM_DISP_STALL_BR_MPRED_IC_L2 / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DISPATCHED_BR_MPRED_IC_L2_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when dispatch was stalled while instruction was fetched from the local L3 after suffering a branch mispredict",
+ "MetricExpr": "PM_DISP_STALL_BR_MPRED_IC_L3 / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DISPATCHED_BR_MPRED_IC_L3_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when dispatch was stalled while instruction was fetched from any source beyond the local L3 after suffering a branch mispredict",
+ "MetricExpr": "PM_DISP_STALL_BR_MPRED_IC_L3MISS / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DISPATCHED_BR_MPRED_IC_L3MISS_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when dispatch was stalled due to a branch mispredict",
+ "MetricExpr": "PM_DISP_STALL_BR_MPRED / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DISPATCHED_BR_MPRED_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the NTC instruction was held at dispatch for any reason",
+ "MetricExpr": "PM_DISP_STALL_HELD_CYC / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DISPATCHED_HELD_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the NTC instruction was held at dispatch because of a synchronizing instruction that requires the ICT to be empty before dispatch",
+ "MetricExpr": "PM_DISP_STALL_HELD_SYNC_CYC / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DISP_HELD_STALL_SYNC_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the NTC instruction was held at dispatch while waiting on the scoreboard",
+ "MetricExpr": "PM_DISP_STALL_HELD_SCOREBOARD_CYC / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DISP_HELD_STALL_SCOREBOARD_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the NTC instruction was held at dispatch due to issue queue full",
+ "MetricExpr": "PM_DISP_STALL_HELD_ISSQ_FULL_CYC / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DISP_HELD_STALL_ISSQ_FULL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the NTC instruction was held at dispatch because the mapper/SRB was full",
+ "MetricExpr": "PM_DISP_STALL_HELD_RENAME_CYC / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DISPATCHED_HELD_RENAME_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the NTC instruction was held at dispatch because the STF mapper/SRB was full",
+ "MetricExpr": "PM_DISP_STALL_HELD_STF_MAPPER_CYC / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DISPATCHED_HELD_STF_MAPPER_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the NTC instruction was held at dispatch because the XVFC mapper/SRB was full",
+ "MetricExpr": "PM_DISP_STALL_HELD_XVFC_MAPPER_CYC / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DISPATCHED_HELD_XVFC_MAPPER_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the NTC instruction was held at dispatch for any other reason",
+ "MetricExpr": "PM_DISP_STALL_HELD_OTHER_CYC / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DISPATCHED_HELD_OTHER_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the NTC instruction has been dispatched but not issued for any reason",
+ "MetricExpr": "PM_ISSUE_STALL / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "ISSUE_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the NTC instruction is waiting to be finished in one of the execution units",
+ "MetricExpr": "PM_EXEC_STALL / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "EXECUTION_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction spent executing an NTC instruction that gets flushed some time after dispatch",
+ "MetricExpr": "PM_EXEC_STALL_NTC_FLUSH / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "NTC_FLUSH_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the NTF instruction finishes at dispatch",
+ "MetricExpr": "PM_EXEC_STALL_FIN_AT_DISP / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "FIN_AT_DISP_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the NTC instruction is executing in the branch unit",
+ "MetricExpr": "PM_EXEC_STALL_BRU / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "BRU_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the NTC instruction is a simple fixed point instruction that is executing in the LSU",
+ "MetricExpr": "PM_EXEC_STALL_SIMPLE_FX / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "SIMPLE_FX_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the NTC instruction is executing in the VSU",
+ "MetricExpr": "PM_EXEC_STALL_VSU / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "VSU_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the NTC instruction is waiting to be finished in one of the execution units",
+ "MetricExpr": "PM_EXEC_STALL_TRANSLATION / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "TRANSLATION_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the NTC instruction is a load or store that suffered a translation miss",
+ "MetricExpr": "PM_EXEC_STALL_DERAT_ONLY_MISS / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DERAT_ONLY_MISS_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the NTC instruction is recovering from a TLB miss",
+ "MetricExpr": "PM_EXEC_STALL_DERAT_DTLB_MISS / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DERAT_DTLB_MISS_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the NTC instruction is executing in the LSU",
+ "MetricExpr": "PM_EXEC_STALL_LSU / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "LSU_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the NTC instruction is a load that is executing in the LSU",
+ "MetricExpr": "PM_EXEC_STALL_LOAD / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "LOAD_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the NTC instruction is waiting for a load miss to resolve from either the local L2 or local L3",
+ "MetricExpr": "PM_EXEC_STALL_DMISS_L2L3 / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DMISS_L2L3_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the NTC instruction is waiting for a load miss to resolve from either the local L2 or local L3, with an RC dispatch conflict",
+ "MetricExpr": "PM_EXEC_STALL_DMISS_L2L3_CONFLICT / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DMISS_L2L3_CONFLICT_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the NTC instruction is waiting for a load miss to resolve from either the local L2 or local L3, without an RC dispatch conflict",
+ "MetricExpr": "PM_EXEC_STALL_DMISS_L2L3_NOCONFLICT / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DMISS_L2L3_NOCONFLICT_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the NTC instruction is waiting for a load miss to resolve from a source beyond the local L2 and local L3",
+ "MetricExpr": "PM_EXEC_STALL_DMISS_L3MISS / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DMISS_L3MISS_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the NTC instruction is waiting for a load miss to resolve from a neighbor chiplet's L2 or L3 in the same chip",
+ "MetricExpr": "PM_EXEC_STALL_DMISS_L21_L31 / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DMISS_L21_L31_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the NTC instruction is waiting for a load miss to resolve from L4, local memory or OpenCapp chip",
+ "MetricExpr": "PM_EXEC_STALL_DMISS_LMEM / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DMISS_LMEM_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the NTC instruction is waiting for a load miss to resolve from a remote chip (cache, L4, memory or OpenCapp) in the same group",
+ "MetricExpr": "PM_EXEC_STALL_DMISS_OFF_CHIP / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DMISS_OFF_CHIP_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the NTC instruction is waiting for a load miss to resolve from a distant chip (cache, L4, memory or OpenCapp chip)",
+ "MetricExpr": "PM_EXEC_STALL_DMISS_OFF_NODE / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DMISS_OFF_NODE_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the NTC instruction is executing a TLBIEL instruction",
+ "MetricExpr": "PM_EXEC_STALL_TLBIEL / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "TLBIEL_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the NTC instruction is finishing a load after its data has been reloaded from a data source beyond the local L1, OR when the LSU is processing an L1-hit, OR when the NTF instruction merged with another load in the LMQ",
+ "MetricExpr": "PM_EXEC_STALL_LOAD_FINISH / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "LOAD_FINISH_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the NTC instruction is a store that is executing in the LSU",
+ "MetricExpr": "PM_EXEC_STALL_STORE / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "STORE_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the NTC instruction is in the store unit outside of handling store misses or other special store operations",
+ "MetricExpr": "PM_EXEC_STALL_STORE_PIPE / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "STORE_PIPE_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the NTC instruction is a store whose cache line was not resident in the L1 and had to wait for allocation of the missing line into the L1",
+ "MetricExpr": "PM_EXEC_STALL_STORE_MISS / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "STORE_MISS_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the NTC instruction is a TLBIE instruction waiting for a response from the L2",
+ "MetricExpr": "PM_EXEC_STALL_TLBIE / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "TLBIE_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the NTC instruction is executing a PTESYNC instruction",
+ "MetricExpr": "PM_EXEC_STALL_PTESYNC / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "PTESYNC_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the NTC instruction cannot complete because the thread was blocked",
+ "MetricExpr": "PM_CMPL_STALL / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "COMPLETION_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the NTC instruction cannot complete because it was interrupted by ANY exception",
+ "MetricExpr": "PM_CMPL_STALL_EXCEPTION / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "EXCEPTION_COMPLETION_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the NTC instruction is stuck at finish waiting for the non-speculative finish of either a STCX instruction waiting for its result or a load waiting for non-critical sectors of data and ECC",
+ "MetricExpr": "PM_CMPL_STALL_MEM_ECC / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "MEM_ECC_COMPLETION_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the NTC instruction cannot complete the instruction is a STCX instruction waiting for resolution from the nest",
+ "MetricExpr": "PM_CMPL_STALL_STCX / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "STCX_COMPLETION_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the NTC instruction is a LWSYNC instruction waiting to complete",
+ "MetricExpr": "PM_CMPL_STALL_LWSYNC / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "LWSYNC_COMPLETION_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the NTC instruction is a HWSYNC instruction stuck at finish waiting for a response from the L2",
+ "MetricExpr": "PM_CMPL_STALL_HWSYNC / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "HWSYNC_COMPLETION_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the NTC instruction required special handling before completion",
+ "MetricExpr": "PM_CMPL_STALL_SPECIAL / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "SPECIAL_COMPLETION_STALL_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when dispatch was stalled because fetch was being held, so there was nothing in the pipeline for this thread",
+ "MetricExpr": "PM_DISP_STALL_FETCH / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DISPATCHED_FETCH_CPI"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the NTC instruction was held at dispatch because of power management",
+ "MetricExpr": "PM_DISP_STALL_HELD_HALT_CYC / PM_RUN_INST_CMPL",
+ "MetricGroup": "CPI",
+ "MetricName": "DISPATCHED_HELD_HALT_CPI"
+ },
+ {
+ "BriefDescription": "Percentage of flushes per completed run instruction",
+ "MetricExpr": "PM_FLUSH / PM_RUN_INST_CMPL * 100",
+ "MetricGroup": "Others",
+ "MetricName": "FLUSH_RATE",
+ "ScaleUnit": "1%"
+ },
+ {
+ "BriefDescription": "Percentage of flushes due to a branch mispredict per instruction",
+ "MetricExpr": "PM_FLUSH_MPRED / PM_RUN_INST_CMPL * 100",
+ "MetricGroup": "Others",
+ "MetricName": "BR_MPRED_FLUSH_RATE",
+ "ScaleUnit": "1%"
+ },
+ {
+ "BriefDescription": "Percentage of branch mispredictions per completed run instruction",
+ "MetricExpr": "PM_BR_MPRED_CMPL / PM_RUN_INST_CMPL",
+ "MetricGroup": "Others",
+ "MetricName": "BRANCH_MISPREDICTION_RATE"
+ },
+ {
+ "BriefDescription": "Percentage of finished loads that missed in the L1",
+ "MetricExpr": "PM_LD_MISS_L1 / PM_LD_REF_L1 * 100",
+ "MetricGroup": "Others",
+ "MetricName": "L1_LD_MISS_RATIO",
+ "ScaleUnit": "1%"
+ },
+ {
+ "BriefDescription": "Percentage of completed run instructions that were loads that missed the L1",
+ "MetricExpr": "PM_LD_MISS_L1 / PM_RUN_INST_CMPL * 100",
+ "MetricGroup": "Others",
+ "MetricName": "L1_LD_MISS_RATE",
+ "ScaleUnit": "1%"
+ },
+ {
+ "BriefDescription": "Percentage of instructions when the DPTEG required for the load/store instruction in execution was missing from the TLB",
+ "MetricExpr": "PM_DTLB_MISS / PM_RUN_INST_CMPL * 100",
+ "MetricGroup": "Others",
+ "MetricName": "DTLB_MISS_RATE",
+ "ScaleUnit": "1%"
+ },
+ {
+ "BriefDescription": "Average number of instructions dispatched per instruction completed",
+ "MetricExpr": "PM_INST_DISP / PM_RUN_INST_CMPL",
+ "MetricGroup": "General",
+ "MetricName": "DISPATCH_PER_INST_CMPL"
+ },
+ {
+ "BriefDescription": "Percentage of completed run instructions that were a demand load that did not hit in the L1 or L2",
+ "MetricExpr": "PM_DATA_FROM_L2MISS / PM_RUN_INST_CMPL * 100",
+ "MetricGroup": "General",
+ "MetricName": "L2_LD_MISS_RATE",
+ "ScaleUnit": "1%"
+ },
+ {
+ "BriefDescription": "Percentage of completed run instructions that were demand fetches that missed the L1 instruction cache",
+ "MetricExpr": "PM_L1_ICACHE_MISS / PM_RUN_INST_CMPL * 100",
+ "MetricGroup": "Instruction_Misses",
+ "MetricName": "L1_INST_MISS_RATE",
+ "ScaleUnit": "1%"
+ },
+ {
+ "BriefDescription": "Percentage of completed run instructions that were demand fetches that reloaded from beyond the L3 instruction cache",
+ "MetricExpr": "PM_INST_FROM_L3MISS / PM_RUN_INST_CMPL * 100",
+ "MetricGroup": "General",
+ "MetricName": "L3_INST_MISS_RATE",
+ "ScaleUnit": "1%"
+ },
+ {
+ "BriefDescription": "Average number of completed instructions per cycle",
+ "MetricExpr": "PM_INST_CMPL / PM_CYC",
+ "MetricGroup": "General",
+ "MetricName": "IPC"
+ },
+ {
+ "BriefDescription": "Average number of cycles per completed instruction group",
+ "MetricExpr": "PM_CYC / PM_1PLUS_PPC_CMPL",
+ "MetricGroup": "General",
+ "MetricName": "CYCLES_PER_COMPLETED_INSTRUCTIONS_SET"
+ },
+ {
+ "BriefDescription": "Percentage of cycles when at least 1 instruction dispatched",
+ "MetricExpr": "PM_1PLUS_PPC_DISP / PM_RUN_CYC * 100",
+ "MetricGroup": "General",
+ "MetricName": "CYCLES_ATLEAST_ONE_INST_DISPATCHED",
+ "ScaleUnit": "1%"
+ },
+ {
+ "BriefDescription": "Average number of finished loads per completed run instruction",
+ "MetricExpr": "PM_LD_REF_L1 / PM_RUN_INST_CMPL",
+ "MetricGroup": "General",
+ "MetricName": "LOADS_PER_INST"
+ },
+ {
+ "BriefDescription": "Average number of finished stores per completed run instruction",
+ "MetricExpr": "PM_ST_FIN / PM_RUN_INST_CMPL",
+ "MetricGroup": "General",
+ "MetricName": "STORES_PER_INST"
+ },
+ {
+ "BriefDescription": "Percentage of demand loads that reloaded from beyond the L2 per completed run instruction",
+ "MetricExpr": "PM_DATA_FROM_L2MISS / PM_RUN_INST_CMPL * 100",
+ "MetricGroup": "dL1_Reloads",
+ "MetricName": "DL1_RELOAD_FROM_L2_MISS_RATE",
+ "ScaleUnit": "1%"
+ },
+ {
+ "BriefDescription": "Percentage of demand loads that reloaded from beyond the L3 per completed run instruction",
+ "MetricExpr": "PM_DATA_FROM_L3MISS / PM_RUN_INST_CMPL * 100",
+ "MetricGroup": "dL1_Reloads",
+ "MetricName": "DL1_RELOAD_FROM_L3_MISS_RATE",
+ "ScaleUnit": "1%"
+ },
+ {
+ "BriefDescription": "Percentage of DERAT misses with 4k page size per completed run instruction",
+ "MetricExpr": "PM_DERAT_MISS_4K / PM_RUN_INST_CMPL * 100",
+ "MetricGroup": "Translation",
+ "MetricName": "DERAT_4K_MISS_RATE",
+ "ScaleUnit": "1%"
+ },
+ {
+ "BriefDescription": "Percentage of DERAT misses with 64k page size per completed run instruction",
+ "MetricExpr": "PM_DERAT_MISS_64K / PM_RUN_INST_CMPL * 100",
+ "MetricGroup": "Translation",
+ "MetricName": "DERAT_64K_MISS_RATE",
+ "ScaleUnit": "1%"
+ },
+ {
+ "BriefDescription": "Average number of run cycles per completed run instruction",
+ "MetricExpr": "PM_RUN_CYC / PM_RUN_INST_CMPL",
+ "MetricGroup": "General",
+ "MetricName": "RUN_CPI"
+ },
+ {
+ "BriefDescription": "Percentage of DERAT misses per completed run instruction",
+ "MetricExpr": "PM_DERAT_MISS / PM_RUN_INST_CMPL * 100",
+ "MetricGroup": "Translation",
+ "MetricName": "DERAT_MISS_RATE",
+ "ScaleUnit": "1%"
+ },
+ {
+ "BriefDescription": "Average number of completed run instructions per run cycle",
+ "MetricExpr": "PM_RUN_INST_CMPL / PM_RUN_CYC",
+ "MetricGroup": "General",
+ "MetricName": "RUN_IPC"
+ },
+ {
+ "BriefDescription": "Average number of instructions completed per instruction group",
+ "MetricExpr": "PM_RUN_INST_CMPL / PM_1PLUS_PPC_CMPL",
+ "MetricGroup": "General",
+ "MetricName": "AVERAGE_COMPLETED_INSTRUCTION_SET_SIZE"
+ },
+ {
+ "BriefDescription": "Average number of finished instructions per completed run instructions",
+ "MetricExpr": "PM_INST_FIN / PM_RUN_INST_CMPL",
+ "MetricGroup": "General",
+ "MetricName": "INST_FIN_PER_CMPL"
+ },
+ {
+ "BriefDescription": "Average cycles per instruction when the NTF instruction is completing and the finish was overlooked",
+ "MetricExpr": "PM_EXEC_STALL_UNKNOWN / PM_RUN_INST_CMPL",
+ "MetricGroup": "General",
+ "MetricName": "EXEC_STALL_UNKOWN_CPI"
+ },
+ {
+ "BriefDescription": "Percentage of finished branches that were taken",
+ "MetricExpr": "PM_BR_TAKEN_CMPL / PM_BR_FIN * 100",
+ "MetricGroup": "General",
+ "MetricName": "TAKEN_BRANCHES",
+ "ScaleUnit": "1%"
+ },
+ {
+ "BriefDescription": "Percentage of completed run instructions that were a demand load that did not hit in the L1, L2, or the L3",
+ "MetricExpr": "PM_DATA_FROM_L3MISS / PM_RUN_INST_CMPL * 100",
+ "MetricGroup": "General",
+ "MetricName": "L3_LD_MISS_RATE",
+ "ScaleUnit": "1%"
+ },
+ {
+ "BriefDescription": "Average number of finished branches per completed run instruction",
+ "MetricExpr": "PM_BR_FIN / PM_RUN_INST_CMPL",
+ "MetricGroup": "General",
+ "MetricName": "BRANCHES_PER_INST"
+ },
+ {
+ "BriefDescription": "Average number of instructions finished in the LSU per completed run instruction",
+ "MetricExpr": "PM_LSU_FIN / PM_RUN_INST_CMPL",
+ "MetricGroup": "General",
+ "MetricName": "LSU_PER_INST"
+ },
+ {
+ "BriefDescription": "Average number of instructions finished in the VSU per completed run instruction",
+ "MetricExpr": "PM_VSU_FIN / PM_RUN_INST_CMPL",
+ "MetricGroup": "General",
+ "MetricName": "VSU_PER_INST"
+ },
+ {
+ "BriefDescription": "Average number of TLBIE instructions finished in the LSU per completed run instruction",
+ "MetricExpr": "PM_TLBIE_FIN / PM_RUN_INST_CMPL",
+ "MetricGroup": "General",
+ "MetricName": "TLBIE_PER_INST"
+ },
+ {
+ "BriefDescription": "Average number of STCX instructions finshed per completed run instruction",
+ "MetricExpr": "PM_STCX_FIN / PM_RUN_INST_CMPL",
+ "MetricGroup": "General",
+ "MetricName": "STXC_PER_INST"
+ },
+ {
+ "BriefDescription": "Average number of LARX instructions finshed per completed run instruction",
+ "MetricExpr": "PM_LARX_FIN / PM_RUN_INST_CMPL",
+ "MetricGroup": "General",
+ "MetricName": "LARX_PER_INST"
+ },
+ {
+ "BriefDescription": "Average number of PTESYNC instructions finshed per completed run instruction",
+ "MetricExpr": "PM_PTESYNC_FIN / PM_RUN_INST_CMPL",
+ "MetricGroup": "General",
+ "MetricName": "PTESYNC_PER_INST"
+ },
+ {
+ "BriefDescription": "Average number of simple fixed-point instructions finshed in the store unit per completed run instruction",
+ "MetricExpr": "PM_FX_LSU_FIN / PM_RUN_INST_CMPL",
+ "MetricGroup": "General",
+ "MetricName": "FX_PER_INST"
+ },
+ {
+ "BriefDescription": "Percentage of demand load misses that reloaded the L1 cache",
+ "MetricExpr": "PM_LD_DEMAND_MISS_L1 / PM_LD_MISS_L1 * 100",
+ "MetricGroup": "General",
+ "MetricName": "DL1_MISS_RELOADS",
+ "ScaleUnit": "1%"
+ },
+ {
+ "BriefDescription": "Percentage of demand load misses that reloaded from beyond the local L2",
+ "MetricExpr": "PM_DATA_FROM_L2MISS / PM_LD_DEMAND_MISS_L1 * 100",
+ "MetricGroup": "dL1_Reloads",
+ "MetricName": "DL1_RELOAD_FROM_L2_MISS",
+ "ScaleUnit": "1%"
+ },
+ {
+ "BriefDescription": "Percentage of demand load misses that reloaded from beyond the local L3",
+ "MetricExpr": "PM_DATA_FROM_L3MISS / PM_LD_DEMAND_MISS_L1 * 100",
+ "MetricGroup": "dL1_Reloads",
+ "MetricName": "DL1_RELOAD_FROM_L3_MISS",
+ "ScaleUnit": "1%"
+ },
+ {
+ "BriefDescription": "Percentage of cycles stalled due to the NTC instruction waiting for a load miss to resolve from a source beyond the local L2 and local L3",
+ "MetricExpr": "DMISS_L3MISS_STALL_CPI / RUN_CPI * 100",
+ "MetricGroup": "General",
+ "MetricName": "DCACHE_MISS_CPI",
+ "ScaleUnit": "1%"
+ },
+ {
+ "BriefDescription": "Percentage of DERAT misses with 2M page size per completed run instruction",
+ "MetricExpr": "PM_DERAT_MISS_2M / PM_RUN_INST_CMPL * 100",
+ "MetricGroup": "Translation",
+ "MetricName": "DERAT_2M_MISS_RATE",
+ "ScaleUnit": "1%"
+ },
+ {
+ "BriefDescription": "Percentage of DERAT misses with 16M page size per completed run instruction",
+ "MetricExpr": "PM_DERAT_MISS_16M / PM_RUN_INST_CMPL * 100",
+ "MetricGroup": "Translation",
+ "MetricName": "DERAT_16M_MISS_RATE",
+ "ScaleUnit": "1%"
+ },
+ {
+ "BriefDescription": "DERAT miss ratio for 4K page size",
+ "MetricExpr": "PM_DERAT_MISS_4K / PM_DERAT_MISS",
+ "MetricGroup": "Translation",
+ "MetricName": "DERAT_4K_MISS_RATIO"
+ },
+ {
+ "BriefDescription": "DERAT miss ratio for 2M page size",
+ "MetricExpr": "PM_DERAT_MISS_2M / PM_DERAT_MISS",
+ "MetricGroup": "Translation",
+ "MetricName": "DERAT_2M_MISS_RATIO"
+ },
+ {
+ "BriefDescription": "DERAT miss ratio for 16M page size",
+ "MetricExpr": "PM_DERAT_MISS_16M / PM_DERAT_MISS",
+ "MetricGroup": "Translation",
+ "MetricName": "DERAT_16M_MISS_RATIO"
+ },
+ {
+ "BriefDescription": "DERAT miss ratio for 64K page size",
+ "MetricExpr": "PM_DERAT_MISS_64K / PM_DERAT_MISS",
+ "MetricGroup": "Translation",
+ "MetricName": "DERAT_64K_MISS_RATIO"
+ },
+ {
+ "BriefDescription": "Percentage of DERAT misses that resulted in TLB reloads",
+ "MetricExpr": "PM_DTLB_MISS / PM_DERAT_MISS * 100",
+ "MetricGroup": "Translation",
+ "MetricName": "DERAT_MISS_RELOAD",
+ "ScaleUnit": "1%"
+ },
+ {
+ "BriefDescription": "Percentage of icache misses that were reloaded from beyond the local L3",
+ "MetricExpr": "PM_INST_FROM_L3MISS / PM_L1_ICACHE_MISS * 100",
+ "MetricGroup": "Instruction_Misses",
+ "MetricName": "INST_FROM_L3_MISS",
+ "ScaleUnit": "1%"
+ },
+ {
+ "BriefDescription": "Percentage of icache reloads from the beyond the L3 per completed run instruction",
+ "MetricExpr": "PM_INST_FROM_L3MISS / PM_RUN_INST_CMPL * 100",
+ "MetricGroup": "Instruction_Misses",
+ "MetricName": "INST_FROM_L3_MISS_RATE",
+ "ScaleUnit": "1%"
+ }
+]
--
2.26.2
^ permalink raw reply related
* [PATCH 0/5] xen: cleanup detection of non-essential pv devices
From: Juergen Gross @ 2021-10-22 6:47 UTC (permalink / raw)
To: xen-devel, linux-input, linux-kernel, dri-devel, linux-fbdev,
linuxppc-dev
Cc: Juergen Gross, alsa-devel, Stefano Stabellini,
Oleksandr Andrushchenko, David Airlie, Greg Kroah-Hartman,
Dmitry Torokhov, Takashi Iwai, Jaroslav Kysela, Daniel Vetter,
Boris Ostrovsky, Jiri Slaby
Today the non-essential pv devices are hard coded in the xenbus driver
and this list is lacking multiple entries.
This series reworks the detection logic of non-essential devices by
adding a flag for that purpose to struct xenbus_driver.
Juergen Gross (5):
xen: add "not_essential" flag to struct xenbus_driver
xen: flag xen_drm_front to be not essential for system boot
xen: flag hvc_xen to be not essential for system boot
xen: flag pvcalls-front to be not essential for system boot
xen: flag xen_snd_front to be not essential for system boot
drivers/gpu/drm/xen/xen_drm_front.c | 1 +
drivers/input/misc/xen-kbdfront.c | 1 +
drivers/tty/hvc/hvc_xen.c | 1 +
drivers/video/fbdev/xen-fbfront.c | 1 +
drivers/xen/pvcalls-front.c | 1 +
drivers/xen/xenbus/xenbus_probe_frontend.c | 14 +++-----------
include/xen/xenbus.h | 1 +
sound/xen/xen_snd_front.c | 1 +
8 files changed, 10 insertions(+), 11 deletions(-)
--
2.26.2
^ permalink raw reply
* [PATCH 3/5] xen: flag hvc_xen to be not essential for system boot
From: Juergen Gross @ 2021-10-22 6:47 UTC (permalink / raw)
To: xen-devel, linuxppc-dev, linux-kernel
Cc: Juergen Gross, Greg Kroah-Hartman, Jiri Slaby
In-Reply-To: <20211022064800.14978-1-jgross@suse.com>
The Xen pv console driver is not essential for boot. Set the respective
flag.
Signed-off-by: Juergen Gross <jgross@suse.com>
---
drivers/tty/hvc/hvc_xen.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/tty/hvc/hvc_xen.c b/drivers/tty/hvc/hvc_xen.c
index f0bf01ea069a..71e0dd2c0ce5 100644
--- a/drivers/tty/hvc/hvc_xen.c
+++ b/drivers/tty/hvc/hvc_xen.c
@@ -522,6 +522,7 @@ static struct xenbus_driver xencons_driver = {
.remove = xencons_remove,
.resume = xencons_resume,
.otherend_changed = xencons_backend_changed,
+ .not_essential = true,
};
#endif /* CONFIG_HVC_XEN_FRONTEND */
--
2.26.2
^ permalink raw reply related
* Re: [PATCH v3 13/18] powerpc/64e: remove mmu_linear_psize
From: Christophe Leroy @ 2021-10-22 6:49 UTC (permalink / raw)
To: Nicholas Piggin, linuxppc-dev
In-Reply-To: <20211021223013.2641952-14-npiggin@gmail.com>
Le 22/10/2021 à 00:30, Nicholas Piggin a écrit :
> mmu_linear_psize is only set at boot once on 64e, is not necessarily
> the correct size of the linear map pages, and is never used anywhere.
> Remove it.
mmu_linear_psize is defined as a macro in:
arch/powerpc/include/asm/book3s/32/mmu-hash.h, line 152 (as a macro)
arch/powerpc/include/asm/nohash/32/mmu-40x.h, line 66 (as a macro)
arch/powerpc/include/asm/nohash/32/mmu-44x.h, line 150 (as a macro)
arch/powerpc/include/asm/nohash/32/mmu-8xx.h, line 173 (as a macro)
Is that needed at all or should is be cleaned, if nothing else than 64s
uses it ?
Otherwise, why not do the same with 64e and define it as a macro ? Maybe
that would help minimising the amount of ifdefs.
>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> ---
> arch/powerpc/mm/nohash/tlb.c | 9 ---------
> 1 file changed, 9 deletions(-)
>
> diff --git a/arch/powerpc/mm/nohash/tlb.c b/arch/powerpc/mm/nohash/tlb.c
> index 5872f69141d5..8c1523ae7f7f 100644
> --- a/arch/powerpc/mm/nohash/tlb.c
> +++ b/arch/powerpc/mm/nohash/tlb.c
> @@ -150,7 +150,6 @@ static inline int mmu_get_tsize(int psize)
> */
> #ifdef CONFIG_PPC64
>
> -int mmu_linear_psize; /* Page size used for the linear mapping */
> int mmu_pte_psize; /* Page size used for PTE pages */
> int mmu_vmemmap_psize; /* Page size used for the virtual mem map */
> int book3e_htw_mode; /* HW tablewalk? Value is PPC_HTW_* */
> @@ -655,14 +654,6 @@ static void early_init_this_mmu(void)
>
> static void __init early_init_mmu_global(void)
> {
> - /* XXX This will have to be decided at runtime, but right
> - * now our boot and TLB miss code hard wires it. Ideally
> - * we should find out a suitable page size and patch the
> - * TLB miss code (either that or use the PACA to store
> - * the value we want)
> - */
> - mmu_linear_psize = MMU_PAGE_1G;
> -
> /* XXX This should be decided at runtime based on supported
> * page sizes in the TLB, but for now let's assume 16M is
> * always there and a good fit (which it probably is)
>
^ permalink raw reply
* Re: [PATCH v3 15/18] powerpc/64s: Make hash MMU support configurable
From: Christophe Leroy @ 2021-10-22 7:02 UTC (permalink / raw)
To: Nicholas Piggin, linuxppc-dev
In-Reply-To: <20211021223013.2641952-16-npiggin@gmail.com>
Le 22/10/2021 à 00:30, Nicholas Piggin a écrit :
> This adds Kconfig selection which allows 64s hash MMU support to be
> disabled. It can be disabled if radix support is enabled, the minimum
> supported CPU type is POWER9 (or higher), and KVM is not selected.
>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> ---
> arch/powerpc/Kconfig | 3 ++-
> arch/powerpc/include/asm/mmu.h | 16 ++++++++++---
> arch/powerpc/kernel/dt_cpu_ftrs.c | 14 ++++++++----
> arch/powerpc/kvm/Kconfig | 1 +
> arch/powerpc/mm/init_64.c | 15 +++++++++---
> arch/powerpc/platforms/Kconfig.cputype | 29 ++++++++++++++++++++++--
> arch/powerpc/platforms/cell/Kconfig | 1 +
> arch/powerpc/platforms/maple/Kconfig | 1 +
> arch/powerpc/platforms/microwatt/Kconfig | 2 +-
> arch/powerpc/platforms/pasemi/Kconfig | 1 +
> arch/powerpc/platforms/powermac/Kconfig | 1 +
> arch/powerpc/platforms/powernv/Kconfig | 2 +-
> 12 files changed, 71 insertions(+), 15 deletions(-)
>
> diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platforms/Kconfig.cputype
> index a208997ade88..1cf254a5d5d4 100644
> --- a/arch/powerpc/platforms/Kconfig.cputype
> +++ b/arch/powerpc/platforms/Kconfig.cputype
> @@ -364,6 +371,17 @@ config SPE
>
> If in doubt, say Y here.
>
> +config PPC_64S_HASH_MMU
> + bool "Hash MMU Support"
> + depends on PPC_BOOK3S_64
> + select PPC_MM_SLICES
> + default y
> + help
> + Enable support for the Power ISA Hash style MMU. This is implemented
> + by all IBM Power and other Book3S CPUs.
> +
> + If you're unsure, say Y.
> +
> config PPC_RADIX_MMU
> bool "Radix MMU Support"
> depends on PPC_BOOK3S_64
> @@ -374,9 +392,10 @@ config PPC_RADIX_MMU
> is only implemented by IBM Power9 CPUs, if you don't have one of them
> you can probably disable this.
>
> -config PPC_RADIX_MMU_DEFAULT
> +config PPC_RADIX_MMU_DEFAULT_OPTION
> bool "Default to using the Radix MMU when possible"
> depends on PPC_RADIX_MMU
> + depends on PPC_64S_HASH_MMU
> default y
> help
> When the hardware supports the Radix MMU, default to using it unless
> @@ -387,6 +406,12 @@ config PPC_RADIX_MMU_DEFAULT
>
> If you're unsure, say Y.
>
> +config PPC_RADIX_MMU_DEFAULT
> + bool
> + depends on PPC_BOOK3S_64
> + depends on PPC_RADIX_MMU_DEFAULT_OPTION || !PPC_64S_HASH_MMU
> + default y
> +
Why do you need that PPC_RADIX_MMU_DEFAULT_OPTION ?
What about
config PPC_RADIX_MMU_DEFAULT
bool "Default to using the Radix MMU when possible" if PPC_64S_HASH_MMU
depends on PPC_RADIX_MMU
depends on PPC_BOOK3S_64
default y
> config PPC_HAVE_KUEP
> bool
>
> diff --git a/arch/powerpc/platforms/cell/Kconfig b/arch/powerpc/platforms/cell/Kconfig
> index db4465c51b56..faa894714a2a 100644
> --- a/arch/powerpc/platforms/cell/Kconfig
> +++ b/arch/powerpc/platforms/cell/Kconfig
> @@ -8,6 +8,7 @@ config PPC_CELL_COMMON
> select PPC_DCR_MMIO
> select PPC_INDIRECT_PIO
> select PPC_INDIRECT_MMIO
> + select PPC_64S_HASH_MMU
Is this one (and the others) needed ?
Because it PPC_64S_HASH_MMU is 'default y', selection shouldn't be
needed I think.
Did you check with savedefconfig ?
> select PPC_HASH_MMU_NATIVE
> select PPC_RTAS
> select IRQ_EDGE_EOI_HANDLER
> diff --git a/arch/powerpc/platforms/maple/Kconfig b/arch/powerpc/platforms/maple/Kconfig
> index 7fd84311ade5..4c058cc57c90 100644
> --- a/arch/powerpc/platforms/maple/Kconfig
> +++ b/arch/powerpc/platforms/maple/Kconfig
> @@ -9,6 +9,7 @@ config PPC_MAPLE
> select GENERIC_TBSYNC
> select PPC_UDBG_16550
> select PPC_970_NAP
> + select PPC_64S_HASH_MMU
> select PPC_HASH_MMU_NATIVE
> select PPC_RTAS
> select MMIO_NVRAM
> diff --git a/arch/powerpc/platforms/microwatt/Kconfig b/arch/powerpc/platforms/microwatt/Kconfig
> index 62b51e37fc05..823192e9d38a 100644
> --- a/arch/powerpc/platforms/microwatt/Kconfig
> +++ b/arch/powerpc/platforms/microwatt/Kconfig
> @@ -5,7 +5,7 @@ config PPC_MICROWATT
> select PPC_XICS
> select PPC_ICS_NATIVE
> select PPC_ICP_NATIVE
> - select PPC_HASH_MMU_NATIVE
> + select PPC_HASH_MMU_NATIVE if PPC_64S_HASH_MMU
> select PPC_UDBG_16550
> select ARCH_RANDOM
> help
> diff --git a/arch/powerpc/platforms/pasemi/Kconfig b/arch/powerpc/platforms/pasemi/Kconfig
> index bc7137353a7f..85ae18ddd911 100644
> --- a/arch/powerpc/platforms/pasemi/Kconfig
> +++ b/arch/powerpc/platforms/pasemi/Kconfig
> @@ -5,6 +5,7 @@ config PPC_PASEMI
> select MPIC
> select FORCE_PCI
> select PPC_UDBG_16550
> + select PPC_64S_HASH_MMU
> select PPC_HASH_MMU_NATIVE
> select MPIC_BROKEN_REGREAD
> help
> diff --git a/arch/powerpc/platforms/powermac/Kconfig b/arch/powerpc/platforms/powermac/Kconfig
> index 2b56df145b82..130707ec9f99 100644
> --- a/arch/powerpc/platforms/powermac/Kconfig
> +++ b/arch/powerpc/platforms/powermac/Kconfig
> @@ -6,6 +6,7 @@ config PPC_PMAC
> select FORCE_PCI
> select PPC_INDIRECT_PCI if PPC32
> select PPC_MPC106 if PPC32
> + select PPC_64S_HASH_MMU if PPC64
> select PPC_HASH_MMU_NATIVE
> select ZONE_DMA if PPC32
> default y
> diff --git a/arch/powerpc/platforms/powernv/Kconfig b/arch/powerpc/platforms/powernv/Kconfig
> index cd754e116184..161dfe024085 100644
> --- a/arch/powerpc/platforms/powernv/Kconfig
> +++ b/arch/powerpc/platforms/powernv/Kconfig
> @@ -2,7 +2,7 @@
> config PPC_POWERNV
> depends on PPC64 && PPC_BOOK3S
> bool "IBM PowerNV (Non-Virtualized) platform support"
> - select PPC_HASH_MMU_NATIVE
> + select PPC_HASH_MMU_NATIVE if PPC_64S_HASH_MMU
> select PPC_XICS
> select PPC_ICP_NATIVE
> select PPC_XIVE_NATIVE
>
^ permalink raw reply
* Re: [PATCH v3 16/18] powerpc/64s: Move hash MMU support code under CONFIG_PPC_64S_HASH_MMU
From: Christophe Leroy @ 2021-10-22 7:18 UTC (permalink / raw)
To: Nicholas Piggin, linuxppc-dev
In-Reply-To: <20211021223013.2641952-17-npiggin@gmail.com>
Le 22/10/2021 à 00:30, Nicholas Piggin a écrit :
> Compiling out hash support code when CONFIG_PPC_64S_HASH_MMU=n saves
> 128kB kernel image size (90kB text) on powernv_defconfig minus KVM,
> 350kB on pseries_defconfig minus KVM, 40kB on a tiny config.
>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> ---
> arch/powerpc/Kconfig | 2 +-
> arch/powerpc/include/asm/book3s/64/mmu.h | 19 +++++++++--
> .../include/asm/book3s/64/tlbflush-hash.h | 7 ++++
> arch/powerpc/include/asm/book3s/pgtable.h | 4 +++
> arch/powerpc/include/asm/mmu_context.h | 2 ++
> arch/powerpc/include/asm/paca.h | 8 +++++
> arch/powerpc/kernel/asm-offsets.c | 2 ++
> arch/powerpc/kernel/entry_64.S | 4 +--
> arch/powerpc/kernel/exceptions-64s.S | 16 +++++++++
> arch/powerpc/kernel/mce.c | 2 +-
> arch/powerpc/kernel/mce_power.c | 10 ++++--
> arch/powerpc/kernel/paca.c | 18 ++++------
> arch/powerpc/kernel/process.c | 13 +++----
> arch/powerpc/kernel/prom.c | 2 ++
> arch/powerpc/kernel/setup_64.c | 5 +++
> arch/powerpc/kexec/core_64.c | 4 +--
> arch/powerpc/kexec/ranges.c | 4 +++
> arch/powerpc/mm/book3s64/Makefile | 15 ++++----
> arch/powerpc/mm/book3s64/hugetlbpage.c | 2 ++
> arch/powerpc/mm/book3s64/mmu_context.c | 34 +++++++++++++++----
> arch/powerpc/mm/book3s64/pgtable.c | 2 +-
> arch/powerpc/mm/book3s64/radix_pgtable.c | 4 +++
> arch/powerpc/mm/copro_fault.c | 2 ++
> arch/powerpc/mm/ptdump/Makefile | 2 +-
> arch/powerpc/platforms/powernv/idle.c | 2 ++
> arch/powerpc/platforms/powernv/setup.c | 2 ++
> arch/powerpc/platforms/pseries/lpar.c | 11 ++++--
> arch/powerpc/platforms/pseries/lparcfg.c | 2 +-
> arch/powerpc/platforms/pseries/mobility.c | 6 ++++
> arch/powerpc/platforms/pseries/ras.c | 2 ++
> arch/powerpc/platforms/pseries/reconfig.c | 2 ++
> arch/powerpc/platforms/pseries/setup.c | 6 ++--
> arch/powerpc/xmon/xmon.c | 8 +++--
> drivers/misc/lkdtm/Makefile | 2 +-
> drivers/misc/lkdtm/core.c | 2 +-
> 35 files changed, 177 insertions(+), 51 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/book3s/64/mmu.h b/arch/powerpc/include/asm/book3s/64/mmu.h
> index c02f42d1031e..d94ebae386b6 100644
> --- a/arch/powerpc/include/asm/book3s/64/mmu.h
> +++ b/arch/powerpc/include/asm/book3s/64/mmu.h
> @@ -233,7 +245,8 @@ static inline void setup_initial_memory_limit(phys_addr_t first_memblock_base,
> * know which translations we will pick. Hence go with hash
> * restrictions.
> */
> - return hash__setup_initial_memory_limit(first_memblock_base,
> + if (!radix_enabled())
> + return hash__setup_initial_memory_limit(first_memblock_base,
> first_memblock_size);
It is a void function, using return is not correct.
> }
>
> @@ -255,6 +268,7 @@ static inline void radix_init_pseries(void) { }
> void cleanup_cpu_mmu_context(void);
> #endif
>
> +#ifdef CONFIG_PPC_64S_HASH_MMU
> static inline int get_user_context(mm_context_t *ctx, unsigned long ea)
> {
> int index = ea >> MAX_EA_BITS_PER_CONTEXT;
> @@ -274,6 +288,7 @@ static inline unsigned long get_user_vsid(mm_context_t *ctx,
>
> return get_vsid(context, ea, ssize);
> }
> +#endif
>
> #endif /* __ASSEMBLY__ */
> #endif /* _ASM_POWERPC_BOOK3S_64_MMU_H_ */
> diff --git a/arch/powerpc/include/asm/book3s/64/tlbflush-hash.h b/arch/powerpc/include/asm/book3s/64/tlbflush-hash.h
> index 3b95769739c7..06f4bd09eecf 100644
> --- a/arch/powerpc/include/asm/book3s/64/tlbflush-hash.h
> +++ b/arch/powerpc/include/asm/book3s/64/tlbflush-hash.h
> @@ -112,8 +112,15 @@ static inline void hash__flush_tlb_kernel_range(unsigned long start,
>
> struct mmu_gather;
> extern void hash__tlb_flush(struct mmu_gather *tlb);
> +extern void flush_tlb_pmd_range(struct mm_struct *mm, pmd_t *pmd,
> + unsigned long addr);
'extern' is superflous
> +
> +#ifdef CONFIG_PPC_64S_HASH_MMU
> /* Private function for use by PCI IO mapping code */
> extern void __flush_hash_table_range(unsigned long start, unsigned long end);
> extern void flush_tlb_pmd_range(struct mm_struct *mm, pmd_t *pmd,
> unsigned long addr);
> +#else
> +static inline void __flush_hash_table_range(unsigned long start, unsigned long end) { }
> +#endif
> #endif /* _ASM_POWERPC_BOOK3S_64_TLBFLUSH_HASH_H */
> diff --git a/arch/powerpc/mm/book3s64/mmu_context.c b/arch/powerpc/mm/book3s64/mmu_context.c
> index c10fc8a72fb3..ae8d6c91dcd9 100644
> --- a/arch/powerpc/mm/book3s64/mmu_context.c
> +++ b/arch/powerpc/mm/book3s64/mmu_context.c
> @@ -31,6 +31,7 @@ static int alloc_context_id(int min_id, int max_id)
> return ida_alloc_range(&mmu_context_ida, min_id, max_id, GFP_KERNEL);
> }
>
> +#ifdef CONFIG_PPC_64S_HASH_MMU
> void hash__reserve_context_id(int id)
> {
> int result = ida_alloc_range(&mmu_context_ida, id, id, GFP_KERNEL);
> @@ -50,7 +51,9 @@ int hash__alloc_context_id(void)
> return alloc_context_id(MIN_USER_CONTEXT, max);
> }
> EXPORT_SYMBOL_GPL(hash__alloc_context_id);
> +#endif
>
> +#ifdef CONFIG_PPC_64S_HASH_MMU
> static int realloc_context_ids(mm_context_t *ctx)
> {
> int i, id;
> @@ -144,12 +147,21 @@ static int hash__init_new_context(struct mm_struct *mm)
> return index;
> }
>
> +void slb_setup_new_exec(void);
Include arch/powerpc/mm/book3s64/internal.h instead
> +
> void hash__setup_new_exec(void)
> {
> slice_setup_new_exec();
>
> slb_setup_new_exec();
> }
> +#else
> +static inline int hash__init_new_context(struct mm_struct *mm)
> +{
> + BUILD_BUG();
> + return 0;
> +}
> +#endif
>
> static int radix__init_new_context(struct mm_struct *mm)
> {
> diff --git a/arch/powerpc/mm/book3s64/pgtable.c b/arch/powerpc/mm/book3s64/pgtable.c
> index 7d556b5513e4..57d2d797c4f6 100644
> --- a/arch/powerpc/mm/book3s64/pgtable.c
> +++ b/arch/powerpc/mm/book3s64/pgtable.c
> @@ -535,7 +535,7 @@ static int __init pgtable_debugfs_setup(void)
> }
> arch_initcall(pgtable_debugfs_setup);
>
> -#ifdef CONFIG_ZONE_DEVICE
> +#if defined(CONFIG_ZONE_DEVICE) && defined(ARCH_HAS_MEMREMAP_COMPAT_ALIGN)
Patch 12 does
select ARCH_HAS_MEMREMAP_COMPAT_ALIGN if PPC_BOOK3S_64
So this change is not needed
> /*
> * Override the generic version in mm/memremap.c.
> *
> diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
> index dd8241c009e5..30f764476c30 100644
> --- a/arch/powerpc/xmon/xmon.c
> +++ b/arch/powerpc/xmon/xmon.c
> @@ -1160,9 +1160,11 @@ cmds(struct pt_regs *excp)
> show_tasks();
> break;
> #ifdef CONFIG_PPC_BOOK3S
> +#if defined(CONFIG_PPC32) || defined(CONFIG_PPC_64S_HASH_MMU)
I think you'll get a build failure here.
dump_segments() is defined only with CONFIG_PPC_BOOK3S_64 and
CONFIG_PPC_BOOK3S_32, see
https://elixir.bootlin.com/linux/v5.15-rc5/source/arch/powerpc/xmon/xmon.c#L3745
and
https://elixir.bootlin.com/linux/v5.15-rc5/source/arch/powerpc/xmon/xmon.c#L3784
> case 'u':
> dump_segments();
> break;
> +#endif
> #elif defined(CONFIG_44x)
> case 'u':
> dump_tlb_44x();
^ permalink raw reply
* Re: [PATCH v3 18/18] powerpc/microwatt: Don't select the hash MMU code
From: Christophe Leroy @ 2021-10-22 7:18 UTC (permalink / raw)
To: Nicholas Piggin, linuxppc-dev
In-Reply-To: <20211021223013.2641952-19-npiggin@gmail.com>
Le 22/10/2021 à 00:30, Nicholas Piggin a écrit :
> Microwatt is radix-only, so it does not require hash MMU support.
>
> This saves 20kB compressed dtbImage and 56kB vmlinux size.
I think patch 17 and 18 should be squashed together.
>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> ---
> arch/powerpc/configs/microwatt_defconfig | 2 +-
> arch/powerpc/platforms/microwatt/Kconfig | 1 -
> 2 files changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/arch/powerpc/configs/microwatt_defconfig b/arch/powerpc/configs/microwatt_defconfig
> index 6e62966730d3..de1dcff05734 100644
> --- a/arch/powerpc/configs/microwatt_defconfig
> +++ b/arch/powerpc/configs/microwatt_defconfig
> @@ -16,6 +16,7 @@ CONFIG_EMBEDDED=y
> # CONFIG_SLAB_MERGE_DEFAULT is not set
> CONFIG_PPC64=y
> CONFIG_POWER9_CPU=y
> +# CONFIG_PPC_64S_HASH_MMU is not set
> # CONFIG_PPC_KUEP is not set
> # CONFIG_PPC_KUAP is not set
> CONFIG_CPU_LITTLE_ENDIAN=y
> @@ -27,7 +28,6 @@ CONFIG_PPC_MICROWATT=y
> # CONFIG_PPC_OF_BOOT_TRAMPOLINE is not set
> CONFIG_CPU_FREQ=y
> CONFIG_HZ_100=y
> -# CONFIG_PPC_MEM_KEYS is not set
> # CONFIG_SECCOMP is not set
> # CONFIG_MQ_IOSCHED_KYBER is not set
> # CONFIG_COREDUMP is not set
> diff --git a/arch/powerpc/platforms/microwatt/Kconfig b/arch/powerpc/platforms/microwatt/Kconfig
> index 823192e9d38a..5e320f49583a 100644
> --- a/arch/powerpc/platforms/microwatt/Kconfig
> +++ b/arch/powerpc/platforms/microwatt/Kconfig
> @@ -5,7 +5,6 @@ config PPC_MICROWATT
> select PPC_XICS
> select PPC_ICS_NATIVE
> select PPC_ICP_NATIVE
> - select PPC_HASH_MMU_NATIVE if PPC_64S_HASH_MMU
> select PPC_UDBG_16550
> select ARCH_RANDOM
> help
>
^ permalink raw reply
* Re: [PATCH 0/5] xen: cleanup detection of non-essential pv devices
From: Jan Beulich @ 2021-10-22 7:24 UTC (permalink / raw)
To: Juergen Gross
Cc: alsa-devel, Stefano Stabellini, Oleksandr Andrushchenko,
David Airlie, Greg Kroah-Hartman, Dmitry Torokhov, Takashi Iwai,
dri-devel, Jaroslav Kysela, linuxppc-dev, linux-fbdev,
Daniel Vetter, linux-input, xen-devel, Boris Ostrovsky,
Jiri Slaby, linux-kernel
In-Reply-To: <20211022064800.14978-1-jgross@suse.com>
On 22.10.2021 08:47, Juergen Gross wrote:
> Today the non-essential pv devices are hard coded in the xenbus driver
> and this list is lacking multiple entries.
>
> This series reworks the detection logic of non-essential devices by
> adding a flag for that purpose to struct xenbus_driver.
I'm wondering whether it wouldn't better be the other way around: The
(hopefully few) essential ones get flagged, thus also making it more
prominent during patch review that a flag gets added (and justification
provided), instead of having to spot the lack of a flag getting set.
Jan
^ permalink raw reply
* Re: [PATCH 0/5] xen: cleanup detection of non-essential pv devices
From: Juergen Gross @ 2021-10-22 7:34 UTC (permalink / raw)
To: Jan Beulich
Cc: alsa-devel, Stefano Stabellini, Oleksandr Andrushchenko,
David Airlie, Greg Kroah-Hartman, Dmitry Torokhov, Takashi Iwai,
dri-devel, Jaroslav Kysela, linuxppc-dev, linux-fbdev,
Daniel Vetter, linux-input, xen-devel, Boris Ostrovsky,
Jiri Slaby, linux-kernel
In-Reply-To: <c4f534f1-8f07-085e-6a10-edbeb884d1a4@suse.com>
[-- Attachment #1.1.1: Type: text/plain, Size: 1184 bytes --]
On 22.10.21 09:24, Jan Beulich wrote:
> On 22.10.2021 08:47, Juergen Gross wrote:
>> Today the non-essential pv devices are hard coded in the xenbus driver
>> and this list is lacking multiple entries.
>>
>> This series reworks the detection logic of non-essential devices by
>> adding a flag for that purpose to struct xenbus_driver.
>
> I'm wondering whether it wouldn't better be the other way around: The
> (hopefully few) essential ones get flagged, thus also making it more
> prominent during patch review that a flag gets added (and justification
> provided), instead of having to spot the lack of a flag getting set.
Not flagging a non-essential one is less problematic than not flagging
an essential driver IMO.
For some drivers I'm on the edge, BTW. The pv 9pfs driver ought to be
non-essential in most cases, but there might be use cases where it is
needed, so I didn't set its non_essential flag.
Same applies to pv-usb and maybe pv-scsi, while pv-tpm probably really
is essential.
With the current series I'm ending up with 6 non-essential drivers and
6 essential ones, so either way needs the same number of drivers
modified.
Juergen
[-- Attachment #1.1.2: OpenPGP public key --]
[-- Type: application/pgp-keys, Size: 3135 bytes --]
[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 495 bytes --]
^ permalink raw reply
* Re: [PATCH v2] powerpc: flexible GPR range save/restore macros
From: Christophe Leroy @ 2021-10-22 7:45 UTC (permalink / raw)
To: Nicholas Piggin, linuxppc-dev
In-Reply-To: <20211022061322.2671178-1-npiggin@gmail.com>
Le 22/10/2021 à 08:13, Nicholas Piggin a écrit :
> Introduce macros that operate on a (start, end) range of GPRs, which
> reduces lines of code and need to do mental arithmetic while reading the
> code.
>
> Reviewed-by: Segher Boessenkool <segher@kernel.crashing.org>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
> ---
> Since v1:
> - Removed unused OP_REG_IDX macro
> - Commented OP_REG macro
>
> arch/powerpc/boot/crt0.S | 31 +++++++------
> arch/powerpc/crypto/md5-asm.S | 10 ++---
> arch/powerpc/crypto/sha1-powerpc-asm.S | 6 +--
> arch/powerpc/include/asm/ppc_asm.h | 43 ++++++++++++-------
> arch/powerpc/kernel/entry_32.S | 23 ++++------
> arch/powerpc/kernel/exceptions-64e.S | 14 ++----
> arch/powerpc/kernel/exceptions-64s.S | 6 +--
> arch/powerpc/kernel/head_32.h | 3 +-
> arch/powerpc/kernel/head_booke.h | 3 +-
> arch/powerpc/kernel/interrupt_64.S | 34 ++++++---------
> arch/powerpc/kernel/optprobes_head.S | 4 +-
> arch/powerpc/kernel/tm.S | 15 ++-----
> .../powerpc/kernel/trace/ftrace_64_mprofile.S | 15 +++----
> arch/powerpc/kvm/book3s_hv_rmhandlers.S | 5 +--
> .../lib/test_emulate_step_exec_instr.S | 8 ++--
> 15 files changed, 94 insertions(+), 126 deletions(-)
>
> diff --git a/arch/powerpc/boot/crt0.S b/arch/powerpc/boot/crt0.S
> index 1d83966f5ef6..e8f10a599659 100644
> --- a/arch/powerpc/boot/crt0.S
> +++ b/arch/powerpc/boot/crt0.S
> @@ -226,16 +226,19 @@ p_base: mflr r10 /* r10 now points to runtime addr of p_base */
> #ifdef __powerpc64__
>
> #define PROM_FRAME_SIZE 512
> -#define SAVE_GPR(n, base) std n,8*(n)(base)
> -#define REST_GPR(n, base) ld n,8*(n)(base)
> -#define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
> -#define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
> -#define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
> -#define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
> -#define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
> -#define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
> -#define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
> -#define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
> +
> +.macro OP_REGS op, width, start, end, base, offset
> + .Lreg=\start
> + .rept (\end - \start + 1)
> + \op .Lreg,\offset+\width*.Lreg(\base)
> + .Lreg=.Lreg+1
> + .endr
> +.endm
> +
> +#define SAVE_GPRS(start, end, base) OP_REGS std, 8, start, end, base, 0
> +#define REST_GPRS(start, end, base) OP_REGS ld, 8, start, end, base, 0
> +#define SAVE_GPR(n, base) SAVE_GPRS(n, n, base)
> +#define REST_GPR(n, base) REST_GPRS(n, n, base)
>
> /* prom handles the jump into and return from firmware. The prom args pointer
> is loaded in r3. */
> @@ -246,9 +249,7 @@ prom:
> stdu r1,-PROM_FRAME_SIZE(r1) /* Save SP and create stack space */
>
> SAVE_GPR(2, r1)
> - SAVE_GPR(13, r1)
> - SAVE_8GPRS(14, r1)
> - SAVE_10GPRS(22, r1)
> + SAVE_GPRS(13, 31, r1)
> mfcr r10
> std r10,8*32(r1)
> mfmsr r10
> @@ -283,9 +284,7 @@ prom:
>
> /* Restore other registers */
> REST_GPR(2, r1)
> - REST_GPR(13, r1)
> - REST_8GPRS(14, r1)
> - REST_10GPRS(22, r1)
> + REST_GPRS(13, 31, r1)
> ld r10,8*32(r1)
> mtcr r10
>
> diff --git a/arch/powerpc/crypto/md5-asm.S b/arch/powerpc/crypto/md5-asm.S
> index 948d100a2934..fa6bc440cf4a 100644
> --- a/arch/powerpc/crypto/md5-asm.S
> +++ b/arch/powerpc/crypto/md5-asm.S
> @@ -38,15 +38,11 @@
>
> #define INITIALIZE \
> PPC_STLU r1,-INT_FRAME_SIZE(r1); \
> - SAVE_8GPRS(14, r1); /* push registers onto stack */ \
> - SAVE_4GPRS(22, r1); \
> - SAVE_GPR(26, r1)
> + SAVE_GPRS(14, 26, r1) /* push registers onto stack */
>
> #define FINALIZE \
> - REST_8GPRS(14, r1); /* pop registers from stack */ \
> - REST_4GPRS(22, r1); \
> - REST_GPR(26, r1); \
> - addi r1,r1,INT_FRAME_SIZE;
> + REST_GPRS(14, 26, r1); /* pop registers from stack */ \
> + addi r1,r1,INT_FRAME_SIZE
>
> #ifdef __BIG_ENDIAN__
> #define LOAD_DATA(reg, off) \
> diff --git a/arch/powerpc/crypto/sha1-powerpc-asm.S b/arch/powerpc/crypto/sha1-powerpc-asm.S
> index 23e248beff71..f0d5ed557ab1 100644
> --- a/arch/powerpc/crypto/sha1-powerpc-asm.S
> +++ b/arch/powerpc/crypto/sha1-powerpc-asm.S
> @@ -125,8 +125,7 @@
>
> _GLOBAL(powerpc_sha_transform)
> PPC_STLU r1,-INT_FRAME_SIZE(r1)
> - SAVE_8GPRS(14, r1)
> - SAVE_10GPRS(22, r1)
> + SAVE_GPRS(14, 31, r1)
>
> /* Load up A - E */
> lwz RA(0),0(r3) /* A */
> @@ -184,7 +183,6 @@ _GLOBAL(powerpc_sha_transform)
> stw RD(0),12(r3)
> stw RE(0),16(r3)
>
> - REST_8GPRS(14, r1)
> - REST_10GPRS(22, r1)
> + REST_GPRS(14, 31, r1)
> addi r1,r1,INT_FRAME_SIZE
> blr
> diff --git a/arch/powerpc/include/asm/ppc_asm.h b/arch/powerpc/include/asm/ppc_asm.h
> index 1c538a9a11e0..fe6cb940d136 100644
> --- a/arch/powerpc/include/asm/ppc_asm.h
> +++ b/arch/powerpc/include/asm/ppc_asm.h
> @@ -16,30 +16,41 @@
>
> #define SZL (BITS_PER_LONG/8)
>
> +/*
> + * This expands to a sequence of operations with reg incrementing from
> + * start to end inclusive, of this form:
> + *
> + * op reg, (offset + (width * reg))(base)
> + *
> + * Note that offset is not the offset of the first operation unless start
> + * is zero (or width is zero).
> + */
> +.macro OP_REGS op, width, start, end, base, offset
> + .Lreg=\start
> + .rept (\end - \start + 1)
> + \op .Lreg, \offset + \width * .Lreg(\base)
> + .Lreg=.Lreg+1
> + .endr
> +.endm
> +
> /*
> * Macros for storing registers into and loading registers from
> * exception frames.
> */
> #ifdef __powerpc64__
> -#define SAVE_GPR(n, base) std n,GPR0+8*(n)(base)
> -#define REST_GPR(n, base) ld n,GPR0+8*(n)(base)
> -#define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)
> -#define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base)
> +#define SAVE_GPRS(start, end, base) OP_REGS std, 8, start, end, base, GPR0
> +#define REST_GPRS(start, end, base) OP_REGS ld, 8, start, end, base, GPR0
> +#define SAVE_NVGPRS(base) SAVE_GPRS(14, 31, base)
> +#define REST_NVGPRS(base) REST_GPRS(14, 31, base)
> #else
> -#define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base)
> -#define REST_GPR(n, base) lwz n,GPR0+4*(n)(base)
> -#define SAVE_NVGPRS(base) stmw 13, GPR0+4*13(base)
> -#define REST_NVGPRS(base) lmw 13, GPR0+4*13(base)
> +#define SAVE_GPRS(start, end, base) OP_REGS stw, 4, start, end, base, GPR0
> +#define REST_GPRS(start, end, base) OP_REGS lwz, 4, start, end, base, GPR0
> +#define SAVE_NVGPRS(base) stmw 13, GPR0+4*13(base)
> +#define REST_NVGPRS(base) lmw 13, GPR0+4*13(base)
> #endif
>
> -#define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
> -#define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
> -#define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
> -#define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
> -#define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
> -#define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
> -#define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
> -#define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
> +#define SAVE_GPR(n, base) SAVE_GPRS(n, n, base)
> +#define REST_GPR(n, base) REST_GPRS(n, n, base)
>
> #define SAVE_FPR(n, base) stfd n,8*TS_FPRWIDTH*(n)(base)
> #define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base)
> diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S
> index 61fdd53cdd9a..c62dd9815965 100644
> --- a/arch/powerpc/kernel/entry_32.S
> +++ b/arch/powerpc/kernel/entry_32.S
> @@ -90,8 +90,7 @@ transfer_to_syscall:
> stw r12,8(r1)
> stw r2,_TRAP(r1)
> SAVE_GPR(0, r1)
> - SAVE_4GPRS(3, r1)
> - SAVE_2GPRS(7, r1)
> + SAVE_GPRS(3, 8, r1)
> addi r2,r10,-THREAD
> SAVE_NVGPRS(r1)
>
> @@ -139,7 +138,7 @@ syscall_exit_finish:
> mtxer r5
> lwz r0,GPR0(r1)
> lwz r3,GPR3(r1)
> - REST_8GPRS(4,r1)
> + REST_GPRS(4, 11, r1)
> lwz r12,GPR12(r1)
> b 1b
>
> @@ -232,9 +231,9 @@ fast_exception_return:
> beq 3f /* if not, we've got problems */
> #endif
>
> -2: REST_4GPRS(3, r11)
> +2: REST_GPRS(3, 6, r11)
> lwz r10,_CCR(r11)
> - REST_2GPRS(1, r11)
> + REST_GPRS(1, 2, r11)
> mtcr r10
> lwz r10,_LINK(r11)
> mtlr r10
> @@ -298,16 +297,14 @@ ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
> * the reliable stack unwinder later on. Clear it.
> */
> stw r0,8(r1)
> - REST_4GPRS(7, r1)
> - REST_2GPRS(11, r1)
> + REST_GPRS(7, 12, r1)
>
> mtcr r3
> mtlr r4
> mtctr r5
> mtspr SPRN_XER,r6
>
> - REST_4GPRS(2, r1)
> - REST_GPR(6, r1)
> + REST_GPRS(2, 6, r1)
> REST_GPR(0, r1)
> REST_GPR(1, r1)
> rfi
> @@ -341,8 +338,7 @@ ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
> lwz r6,_CCR(r1)
> li r0,0
>
> - REST_4GPRS(7, r1)
> - REST_2GPRS(11, r1)
> + REST_GPRS(7, 12, r1)
>
> mtlr r3
> mtctr r4
> @@ -354,7 +350,7 @@ ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
> */
> stw r0,8(r1)
>
> - REST_4GPRS(2, r1)
> + REST_GPRS(2, 5, r1)
>
> bne- cr1,1f /* emulate stack store */
> mtcr r6
> @@ -430,8 +426,7 @@ _ASM_NOKPROBE_SYMBOL(interrupt_return)
> bne interrupt_return; \
> lwz r0,GPR0(r1); \
> lwz r2,GPR2(r1); \
> - REST_4GPRS(3, r1); \
> - REST_2GPRS(7, r1); \
> + REST_GPRS(3, 8, r1); \
> lwz r10,_XER(r1); \
> lwz r11,_CTR(r1); \
> mtspr SPRN_XER,r10; \
> diff --git a/arch/powerpc/kernel/exceptions-64e.S b/arch/powerpc/kernel/exceptions-64e.S
> index 711c66b76df1..67dc4e3179a0 100644
> --- a/arch/powerpc/kernel/exceptions-64e.S
> +++ b/arch/powerpc/kernel/exceptions-64e.S
> @@ -198,8 +198,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
>
> stdcx. r0,0,r1 /* to clear the reservation */
>
> - REST_4GPRS(2, r1)
> - REST_4GPRS(6, r1)
> + REST_GPRS(2, 9, r1)
>
> ld r10,_CTR(r1)
> ld r11,_XER(r1)
> @@ -375,9 +374,7 @@ ret_from_mc_except:
> exc_##n##_common: \
> std r0,GPR0(r1); /* save r0 in stackframe */ \
> std r2,GPR2(r1); /* save r2 in stackframe */ \
> - SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
> - SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
> - std r9,GPR9(r1); /* save r9 in stackframe */ \
> + SAVE_GPRS(3, 9, r1); /* save r3 - r9 in stackframe */ \
> std r10,_NIP(r1); /* save SRR0 to stackframe */ \
> std r11,_MSR(r1); /* save SRR1 to stackframe */ \
> beq 2f; /* if from kernel mode */ \
> @@ -1061,9 +1058,7 @@ bad_stack_book3e:
> std r11,_ESR(r1)
> std r0,GPR0(r1); /* save r0 in stackframe */ \
> std r2,GPR2(r1); /* save r2 in stackframe */ \
> - SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
> - SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
> - std r9,GPR9(r1); /* save r9 in stackframe */ \
> + SAVE_GPRS(3, 9, r1); /* save r3 - r9 in stackframe */ \
> ld r3,PACA_EXGEN+EX_R10(r13);/* get back r10 */ \
> ld r4,PACA_EXGEN+EX_R11(r13);/* get back r11 */ \
> mfspr r5,SPRN_SPRG_GEN_SCRATCH;/* get back r13 XXX can be wrong */ \
> @@ -1077,8 +1072,7 @@ bad_stack_book3e:
> std r10,_LINK(r1)
> std r11,_CTR(r1)
> std r12,_XER(r1)
> - SAVE_10GPRS(14,r1)
> - SAVE_8GPRS(24,r1)
> + SAVE_GPRS(14, 31, r1)
> lhz r12,PACA_TRAP_SAVE(r13)
> std r12,_TRAP(r1)
> addi r11,r1,INT_FRAME_SIZE
> diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
> index eaf1f72131a1..277eccf0f086 100644
> --- a/arch/powerpc/kernel/exceptions-64s.S
> +++ b/arch/powerpc/kernel/exceptions-64s.S
> @@ -574,8 +574,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
> ld r10,IAREA+EX_CTR(r13)
> std r10,_CTR(r1)
> std r2,GPR2(r1) /* save r2 in stackframe */
> - SAVE_4GPRS(3, r1) /* save r3 - r6 in stackframe */
> - SAVE_2GPRS(7, r1) /* save r7, r8 in stackframe */
> + SAVE_GPRS(3, 8, r1) /* save r3 - r8 in stackframe */
> mflr r9 /* Get LR, later save to stack */
> ld r2,PACATOC(r13) /* get kernel TOC into r2 */
> std r9,_LINK(r1)
> @@ -693,8 +692,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
> mtlr r9
> ld r9,_CCR(r1)
> mtcr r9
> - REST_8GPRS(2, r1)
> - REST_4GPRS(10, r1)
> + REST_GPRS(2, 13, r1)
> REST_GPR(0, r1)
> /* restore original r1. */
> ld r1,GPR1(r1)
> diff --git a/arch/powerpc/kernel/head_32.h b/arch/powerpc/kernel/head_32.h
> index 6b1ec9e3541b..25887303651a 100644
> --- a/arch/powerpc/kernel/head_32.h
> +++ b/arch/powerpc/kernel/head_32.h
> @@ -115,8 +115,7 @@ _ASM_NOKPROBE_SYMBOL(\name\()_virt)
> stw r10,8(r1)
> li r10, \trapno
> stw r10,_TRAP(r1)
> - SAVE_4GPRS(3, r1)
> - SAVE_2GPRS(7, r1)
> + SAVE_GPRS(3, 8, r1)
> SAVE_NVGPRS(r1)
> stw r2,GPR2(r1)
> stw r12,_NIP(r1)
> diff --git a/arch/powerpc/kernel/head_booke.h b/arch/powerpc/kernel/head_booke.h
> index e5503420b6c6..0ae26396639d 100644
> --- a/arch/powerpc/kernel/head_booke.h
> +++ b/arch/powerpc/kernel/head_booke.h
> @@ -87,8 +87,7 @@ END_BTB_FLUSH_SECTION
> stw r10, 8(r1)
> li r10, \trapno
> stw r10,_TRAP(r1)
> - SAVE_4GPRS(3, r1)
> - SAVE_2GPRS(7, r1)
> + SAVE_GPRS(3, 8, r1)
> SAVE_NVGPRS(r1)
> stw r2,GPR2(r1)
> stw r12,_NIP(r1)
> diff --git a/arch/powerpc/kernel/interrupt_64.S b/arch/powerpc/kernel/interrupt_64.S
> index ec950b08a8dc..2ad223597ca2 100644
> --- a/arch/powerpc/kernel/interrupt_64.S
> +++ b/arch/powerpc/kernel/interrupt_64.S
> @@ -162,10 +162,9 @@ END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
> * The value of AMR only matters while we're in the kernel.
> */
> mtcr r2
> - ld r2,GPR2(r1)
> - ld r3,GPR3(r1)
> - ld r13,GPR13(r1)
> - ld r1,GPR1(r1)
> + REST_GPRS(2, 3, r1)
> + REST_GPR(13, r1)
> + REST_GPR(1, r1)
> RFSCV_TO_USER
> b . /* prevent speculative execution */
>
> @@ -183,9 +182,8 @@ END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
> mtctr r3
> mtlr r4
> mtspr SPRN_XER,r5
> - REST_10GPRS(2, r1)
> - REST_2GPRS(12, r1)
> - ld r1,GPR1(r1)
> + REST_GPRS(2, 13, r1)
> + REST_GPR(1, r1)
> RFI_TO_USER
> .Lsyscall_vectored_\name\()_rst_end:
>
> @@ -374,10 +372,9 @@ END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
> * The value of AMR only matters while we're in the kernel.
> */
> mtcr r2
> - ld r2,GPR2(r1)
> - ld r3,GPR3(r1)
> - ld r13,GPR13(r1)
> - ld r1,GPR1(r1)
> + REST_GPRS(2, 3, r1)
> + REST_GPR(13, r1)
> + REST_GPR(1, r1)
> RFI_TO_USER
> b . /* prevent speculative execution */
>
> @@ -388,8 +385,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
> mtctr r3
> mtspr SPRN_XER,r4
> ld r0,GPR0(r1)
> - REST_8GPRS(4, r1)
> - ld r12,GPR12(r1)
> + REST_GPRS(4, 12, r1)
> b .Lsyscall_restore_regs_cont
> .Lsyscall_rst_end:
>
> @@ -518,17 +514,14 @@ ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
> ld r6,_XER(r1)
> li r0,0
>
> - REST_4GPRS(7, r1)
> - REST_2GPRS(11, r1)
> - REST_GPR(13, r1)
> + REST_GPRS(7, 13, r1)
>
> mtcr r3
> mtlr r4
> mtctr r5
> mtspr SPRN_XER,r6
>
> - REST_4GPRS(2, r1)
> - REST_GPR(6, r1)
> + REST_GPRS(2, 6, r1)
> REST_GPR(0, r1)
> REST_GPR(1, r1)
> .ifc \srr,srr
> @@ -625,8 +618,7 @@ ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
> ld r6,_CCR(r1)
> li r0,0
>
> - REST_4GPRS(7, r1)
> - REST_2GPRS(11, r1)
> + REST_GPRS(7, 12, r1)
>
> mtlr r3
> mtctr r4
> @@ -638,7 +630,7 @@ ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
> */
> std r0,STACK_FRAME_OVERHEAD-16(r1)
>
> - REST_4GPRS(2, r1)
> + REST_GPRS(2, 5, r1)
>
> bne- cr1,1f /* emulate stack store */
> mtcr r6
> diff --git a/arch/powerpc/kernel/optprobes_head.S b/arch/powerpc/kernel/optprobes_head.S
> index 19ea3312403c..5c7f0b4b784b 100644
> --- a/arch/powerpc/kernel/optprobes_head.S
> +++ b/arch/powerpc/kernel/optprobes_head.S
> @@ -10,8 +10,8 @@
> #include <asm/asm-offsets.h>
>
> #ifdef CONFIG_PPC64
> -#define SAVE_30GPRS(base) SAVE_10GPRS(2,base); SAVE_10GPRS(12,base); SAVE_10GPRS(22,base)
> -#define REST_30GPRS(base) REST_10GPRS(2,base); REST_10GPRS(12,base); REST_10GPRS(22,base)
> +#define SAVE_30GPRS(base) SAVE_GPRS(2, 31, base)
> +#define REST_30GPRS(base) REST_GPRS(2, 31, base)
> #define TEMPLATE_FOR_IMM_LOAD_INSNS nop; nop; nop; nop; nop
> #else
> #define SAVE_30GPRS(base) stmw r2, GPR2(base)
> diff --git a/arch/powerpc/kernel/tm.S b/arch/powerpc/kernel/tm.S
> index 2b91f233b05d..3beecc32940b 100644
> --- a/arch/powerpc/kernel/tm.S
> +++ b/arch/powerpc/kernel/tm.S
> @@ -226,11 +226,8 @@ _GLOBAL(tm_reclaim)
>
> /* Sync the userland GPRs 2-12, 14-31 to thread->regs: */
> SAVE_GPR(0, r7) /* user r0 */
> - SAVE_GPR(2, r7) /* user r2 */
> - SAVE_4GPRS(3, r7) /* user r3-r6 */
> - SAVE_GPR(8, r7) /* user r8 */
> - SAVE_GPR(9, r7) /* user r9 */
> - SAVE_GPR(10, r7) /* user r10 */
> + SAVE_GPRS(2, 6, r7) /* user r2-r6 */
> + SAVE_GPRS(8, 10, r7) /* user r8-r10 */
> ld r3, GPR1(r1) /* user r1 */
> ld r4, GPR7(r1) /* user r7 */
> ld r5, GPR11(r1) /* user r11 */
> @@ -445,12 +442,8 @@ restore_gprs:
> ld r6, THREAD_TM_PPR(r3)
>
> REST_GPR(0, r7) /* GPR0 */
> - REST_2GPRS(2, r7) /* GPR2-3 */
> - REST_GPR(4, r7) /* GPR4 */
> - REST_4GPRS(8, r7) /* GPR8-11 */
> - REST_2GPRS(12, r7) /* GPR12-13 */
> -
> - REST_NVGPRS(r7) /* GPR14-31 */
> + REST_GPRS(2, 4, r7) /* GPR2-4 */
> + REST_GPRS(8, 31, r7) /* GPR8-31 */
>
> /* Load up PPR and DSCR here so we don't run with user values for long */
> mtspr SPRN_DSCR, r5
> diff --git a/arch/powerpc/kernel/trace/ftrace_64_mprofile.S b/arch/powerpc/kernel/trace/ftrace_64_mprofile.S
> index f9fd5f743eba..d636fc755f60 100644
> --- a/arch/powerpc/kernel/trace/ftrace_64_mprofile.S
> +++ b/arch/powerpc/kernel/trace/ftrace_64_mprofile.S
> @@ -41,15 +41,14 @@ _GLOBAL(ftrace_regs_caller)
>
> /* Save all gprs to pt_regs */
> SAVE_GPR(0, r1)
> - SAVE_10GPRS(2, r1)
> + SAVE_GPRS(2, 11, r1)
>
> /* Ok to continue? */
> lbz r3, PACA_FTRACE_ENABLED(r13)
> cmpdi r3, 0
> beq ftrace_no_trace
>
> - SAVE_10GPRS(12, r1)
> - SAVE_10GPRS(22, r1)
> + SAVE_GPRS(12, 31, r1)
>
> /* Save previous stack pointer (r1) */
> addi r8, r1, SWITCH_FRAME_SIZE
> @@ -108,10 +107,8 @@ ftrace_regs_call:
> #endif
>
> /* Restore gprs */
> - REST_GPR(0,r1)
> - REST_10GPRS(2,r1)
> - REST_10GPRS(12,r1)
> - REST_10GPRS(22,r1)
> + REST_GPR(0, r1)
> + REST_GPRS(2, 31, r1)
>
> /* Restore possibly modified LR */
> ld r0, _LINK(r1)
> @@ -157,7 +154,7 @@ _GLOBAL(ftrace_caller)
> stdu r1, -SWITCH_FRAME_SIZE(r1)
>
> /* Save all gprs to pt_regs */
> - SAVE_8GPRS(3, r1)
> + SAVE_GPRS(3, 10, r1)
>
> lbz r3, PACA_FTRACE_ENABLED(r13)
> cmpdi r3, 0
> @@ -194,7 +191,7 @@ ftrace_call:
> mtctr r3
>
> /* Restore gprs */
> - REST_8GPRS(3,r1)
> + REST_GPRS(3, 10, r1)
>
> /* Restore callee's TOC */
> ld r2, 24(r1)
> diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
> index eb776d0c5d8e..28be10db895d 100644
> --- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S
> +++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
> @@ -2711,8 +2711,7 @@ kvmppc_bad_host_intr:
> std r0, GPR0(r1)
> std r9, GPR1(r1)
> std r2, GPR2(r1)
> - SAVE_4GPRS(3, r1)
> - SAVE_2GPRS(7, r1)
> + SAVE_GPRS(3, 8, r1)
> srdi r0, r12, 32
> clrldi r12, r12, 32
> std r0, _CCR(r1)
> @@ -2735,7 +2734,7 @@ kvmppc_bad_host_intr:
> ld r9, HSTATE_SCRATCH2(r13)
> ld r12, HSTATE_SCRATCH0(r13)
> GET_SCRATCH0(r0)
> - SAVE_4GPRS(9, r1)
> + SAVE_GPRS(9, 12, r1)
> std r0, GPR13(r1)
> SAVE_NVGPRS(r1)
> ld r5, HSTATE_CFAR(r13)
> diff --git a/arch/powerpc/lib/test_emulate_step_exec_instr.S b/arch/powerpc/lib/test_emulate_step_exec_instr.S
> index 9ef941d958d8..5473f9d03df3 100644
> --- a/arch/powerpc/lib/test_emulate_step_exec_instr.S
> +++ b/arch/powerpc/lib/test_emulate_step_exec_instr.S
> @@ -37,7 +37,7 @@ _GLOBAL(exec_instr)
> * The stack pointer (GPR1) and the thread pointer (GPR13) are not
> * saved as these should not be modified anyway.
> */
> - SAVE_2GPRS(2, r1)
> + SAVE_GPRS(2, 3, r1)
> SAVE_NVGPRS(r1)
>
> /*
> @@ -75,8 +75,7 @@ _GLOBAL(exec_instr)
>
> /* Load GPRs from pt_regs */
> REST_GPR(0, r31)
> - REST_10GPRS(2, r31)
> - REST_GPR(12, r31)
> + REST_GPRS(2, 12, r31)
> REST_NVGPRS(r31)
>
> /* Placeholder for the test instruction */
> @@ -99,8 +98,7 @@ _GLOBAL(exec_instr)
> subi r3, r3, GPR0
> SAVE_GPR(0, r3)
> SAVE_GPR(2, r3)
> - SAVE_8GPRS(4, r3)
> - SAVE_GPR(12, r3)
> + SAVE_GPRS(4, 12, r3)
> SAVE_NVGPRS(r3)
>
> /* Save resulting LR to pt_regs */
>
^ permalink raw reply
* Re: [PATCH v3 13/18] powerpc/64e: remove mmu_linear_psize
From: Nicholas Piggin @ 2021-10-22 9:21 UTC (permalink / raw)
To: Christophe Leroy, linuxppc-dev
In-Reply-To: <8e03d7e9-b56a-0d87-3852-b9c5099e1273@csgroup.eu>
Excerpts from Christophe Leroy's message of October 22, 2021 4:49 pm:
>
>
> Le 22/10/2021 à 00:30, Nicholas Piggin a écrit :
>> mmu_linear_psize is only set at boot once on 64e, is not necessarily
>> the correct size of the linear map pages, and is never used anywhere.
>> Remove it.
>
> mmu_linear_psize is defined as a macro in:
>
> arch/powerpc/include/asm/book3s/32/mmu-hash.h, line 152 (as a macro)
> arch/powerpc/include/asm/nohash/32/mmu-40x.h, line 66 (as a macro)
> arch/powerpc/include/asm/nohash/32/mmu-44x.h, line 150 (as a macro)
> arch/powerpc/include/asm/nohash/32/mmu-8xx.h, line 173 (as a macro)
>
> Is that needed at all or should is be cleaned, if nothing else than 64s
> uses it ?
>
> Otherwise, why not do the same with 64e and define it as a macro ? Maybe
> that would help minimising the amount of ifdefs.
I prefer to remove it entirely, to avoid situations like 64e where it
was being used without understanding what the value really was.
32e can come in a later cleanup to avoid making this series any bigger.
Thanks,
Nick
^ permalink raw reply
* Re: [PATCH v3 15/18] powerpc/64s: Make hash MMU support configurable
From: Nicholas Piggin @ 2021-10-22 9:30 UTC (permalink / raw)
To: Christophe Leroy, linuxppc-dev
In-Reply-To: <7e10f779-e968-e723-cdbc-4510acdf64a8@csgroup.eu>
Excerpts from Christophe Leroy's message of October 22, 2021 5:02 pm:
>
>
> Le 22/10/2021 à 00:30, Nicholas Piggin a écrit :
>> This adds Kconfig selection which allows 64s hash MMU support to be
>> disabled. It can be disabled if radix support is enabled, the minimum
>> supported CPU type is POWER9 (or higher), and KVM is not selected.
>>
>> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
>> ---
>> arch/powerpc/Kconfig | 3 ++-
>> arch/powerpc/include/asm/mmu.h | 16 ++++++++++---
>> arch/powerpc/kernel/dt_cpu_ftrs.c | 14 ++++++++----
>> arch/powerpc/kvm/Kconfig | 1 +
>> arch/powerpc/mm/init_64.c | 15 +++++++++---
>> arch/powerpc/platforms/Kconfig.cputype | 29 ++++++++++++++++++++++--
>> arch/powerpc/platforms/cell/Kconfig | 1 +
>> arch/powerpc/platforms/maple/Kconfig | 1 +
>> arch/powerpc/platforms/microwatt/Kconfig | 2 +-
>> arch/powerpc/platforms/pasemi/Kconfig | 1 +
>> arch/powerpc/platforms/powermac/Kconfig | 1 +
>> arch/powerpc/platforms/powernv/Kconfig | 2 +-
>> 12 files changed, 71 insertions(+), 15 deletions(-)
>>
>
>> diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platforms/Kconfig.cputype
>> index a208997ade88..1cf254a5d5d4 100644
>> --- a/arch/powerpc/platforms/Kconfig.cputype
>> +++ b/arch/powerpc/platforms/Kconfig.cputype
>
>> @@ -364,6 +371,17 @@ config SPE
>>
>> If in doubt, say Y here.
>>
>> +config PPC_64S_HASH_MMU
>> + bool "Hash MMU Support"
>> + depends on PPC_BOOK3S_64
>> + select PPC_MM_SLICES
>> + default y
>> + help
>> + Enable support for the Power ISA Hash style MMU. This is implemented
>> + by all IBM Power and other Book3S CPUs.
>> +
>> + If you're unsure, say Y.
>> +
>> config PPC_RADIX_MMU
>> bool "Radix MMU Support"
>> depends on PPC_BOOK3S_64
>> @@ -374,9 +392,10 @@ config PPC_RADIX_MMU
>> is only implemented by IBM Power9 CPUs, if you don't have one of them
>> you can probably disable this.
>>
>> -config PPC_RADIX_MMU_DEFAULT
>> +config PPC_RADIX_MMU_DEFAULT_OPTION
>> bool "Default to using the Radix MMU when possible"
>> depends on PPC_RADIX_MMU
>> + depends on PPC_64S_HASH_MMU
>> default y
>> help
>> When the hardware supports the Radix MMU, default to using it unless
>> @@ -387,6 +406,12 @@ config PPC_RADIX_MMU_DEFAULT
>>
>> If you're unsure, say Y.
>>
>> +config PPC_RADIX_MMU_DEFAULT
>> + bool
>> + depends on PPC_BOOK3S_64
>> + depends on PPC_RADIX_MMU_DEFAULT_OPTION || !PPC_64S_HASH_MMU
>> + default y
>> +
>
> Why do you need that PPC_RADIX_MMU_DEFAULT_OPTION ?
>
> What about
>
> config PPC_RADIX_MMU_DEFAULT
> bool "Default to using the Radix MMU when possible" if PPC_64S_HASH_MMU
> depends on PPC_RADIX_MMU
> depends on PPC_BOOK3S_64
> default y
That's what I was trying to do I guess, I forget about the if clause on
the bool option.
>> diff --git a/arch/powerpc/platforms/cell/Kconfig b/arch/powerpc/platforms/cell/Kconfig
>> index db4465c51b56..faa894714a2a 100644
>> --- a/arch/powerpc/platforms/cell/Kconfig
>> +++ b/arch/powerpc/platforms/cell/Kconfig
>> @@ -8,6 +8,7 @@ config PPC_CELL_COMMON
>> select PPC_DCR_MMIO
>> select PPC_INDIRECT_PIO
>> select PPC_INDIRECT_MMIO
>> + select PPC_64S_HASH_MMU
>
> Is this one (and the others) needed ?
>
> Because it PPC_64S_HASH_MMU is 'default y', selection shouldn't be
> needed I think.
>
> Did you check with savedefconfig ?
The platform ones maybe aren't needed but it's because the cpu type
support selects hash (I don't want it to be configurable even if it
defaults to y). But it probably makes better sense to select this with
CPU type support rather than platform.
Thanks,
Nick
^ permalink raw reply
* Re: [PATCH v3 16/18] powerpc/64s: Move hash MMU support code under CONFIG_PPC_64S_HASH_MMU
From: Nicholas Piggin @ 2021-10-22 9:34 UTC (permalink / raw)
To: Christophe Leroy, linuxppc-dev
In-Reply-To: <cfd73dd0-a7a2-b8b3-34d8-5a225758b056@csgroup.eu>
Excerpts from Christophe Leroy's message of October 22, 2021 5:18 pm:
>
>
> Le 22/10/2021 à 00:30, Nicholas Piggin a écrit :
>> Compiling out hash support code when CONFIG_PPC_64S_HASH_MMU=n saves
>> 128kB kernel image size (90kB text) on powernv_defconfig minus KVM,
>> 350kB on pseries_defconfig minus KVM, 40kB on a tiny config.
>>
>> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
>> ---
>> arch/powerpc/Kconfig | 2 +-
>> arch/powerpc/include/asm/book3s/64/mmu.h | 19 +++++++++--
>> .../include/asm/book3s/64/tlbflush-hash.h | 7 ++++
>> arch/powerpc/include/asm/book3s/pgtable.h | 4 +++
>> arch/powerpc/include/asm/mmu_context.h | 2 ++
>> arch/powerpc/include/asm/paca.h | 8 +++++
>> arch/powerpc/kernel/asm-offsets.c | 2 ++
>> arch/powerpc/kernel/entry_64.S | 4 +--
>> arch/powerpc/kernel/exceptions-64s.S | 16 +++++++++
>> arch/powerpc/kernel/mce.c | 2 +-
>> arch/powerpc/kernel/mce_power.c | 10 ++++--
>> arch/powerpc/kernel/paca.c | 18 ++++------
>> arch/powerpc/kernel/process.c | 13 +++----
>> arch/powerpc/kernel/prom.c | 2 ++
>> arch/powerpc/kernel/setup_64.c | 5 +++
>> arch/powerpc/kexec/core_64.c | 4 +--
>> arch/powerpc/kexec/ranges.c | 4 +++
>> arch/powerpc/mm/book3s64/Makefile | 15 ++++----
>> arch/powerpc/mm/book3s64/hugetlbpage.c | 2 ++
>> arch/powerpc/mm/book3s64/mmu_context.c | 34 +++++++++++++++----
>> arch/powerpc/mm/book3s64/pgtable.c | 2 +-
>> arch/powerpc/mm/book3s64/radix_pgtable.c | 4 +++
>> arch/powerpc/mm/copro_fault.c | 2 ++
>> arch/powerpc/mm/ptdump/Makefile | 2 +-
>> arch/powerpc/platforms/powernv/idle.c | 2 ++
>> arch/powerpc/platforms/powernv/setup.c | 2 ++
>> arch/powerpc/platforms/pseries/lpar.c | 11 ++++--
>> arch/powerpc/platforms/pseries/lparcfg.c | 2 +-
>> arch/powerpc/platforms/pseries/mobility.c | 6 ++++
>> arch/powerpc/platforms/pseries/ras.c | 2 ++
>> arch/powerpc/platforms/pseries/reconfig.c | 2 ++
>> arch/powerpc/platforms/pseries/setup.c | 6 ++--
>> arch/powerpc/xmon/xmon.c | 8 +++--
>> drivers/misc/lkdtm/Makefile | 2 +-
>> drivers/misc/lkdtm/core.c | 2 +-
>> 35 files changed, 177 insertions(+), 51 deletions(-)
>>
>
>> diff --git a/arch/powerpc/include/asm/book3s/64/mmu.h b/arch/powerpc/include/asm/book3s/64/mmu.h
>> index c02f42d1031e..d94ebae386b6 100644
>> --- a/arch/powerpc/include/asm/book3s/64/mmu.h
>> +++ b/arch/powerpc/include/asm/book3s/64/mmu.h
>> @@ -233,7 +245,8 @@ static inline void setup_initial_memory_limit(phys_addr_t first_memblock_base,
>> * know which translations we will pick. Hence go with hash
>> * restrictions.
>> */
>> - return hash__setup_initial_memory_limit(first_memblock_base,
>> + if (!radix_enabled())
>> + return hash__setup_initial_memory_limit(first_memblock_base,
>> first_memblock_size);
>
> It is a void function, using return is not correct.
I guess for this case I can fix as I go.
>> @@ -112,8 +112,15 @@ static inline void hash__flush_tlb_kernel_range(unsigned long start,
>>
>> struct mmu_gather;
>> extern void hash__tlb_flush(struct mmu_gather *tlb);
>> +extern void flush_tlb_pmd_range(struct mm_struct *mm, pmd_t *pmd,
>> + unsigned long addr);
>
> 'extern' is superflous
Ditto.
>> @@ -144,12 +147,21 @@ static int hash__init_new_context(struct mm_struct *mm)
>> return index;
>> }
>>
>> +void slb_setup_new_exec(void);
>
> Include arch/powerpc/mm/book3s64/internal.h instead
Will do.
>> diff --git a/arch/powerpc/mm/book3s64/pgtable.c b/arch/powerpc/mm/book3s64/pgtable.c
>> index 7d556b5513e4..57d2d797c4f6 100644
>> --- a/arch/powerpc/mm/book3s64/pgtable.c
>> +++ b/arch/powerpc/mm/book3s64/pgtable.c
>> @@ -535,7 +535,7 @@ static int __init pgtable_debugfs_setup(void)
>> }
>> arch_initcall(pgtable_debugfs_setup);
>>
>> -#ifdef CONFIG_ZONE_DEVICE
>> +#if defined(CONFIG_ZONE_DEVICE) && defined(ARCH_HAS_MEMREMAP_COMPAT_ALIGN)
>
> Patch 12 does
>
> select ARCH_HAS_MEMREMAP_COMPAT_ALIGN if PPC_BOOK3S_64
Ah, I meant to change that to PPC_64S_HASH_MMU.
>
> So this change is not needed
>
>> /*
>> * Override the generic version in mm/memremap.c.
>> *
>
>> diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
>> index dd8241c009e5..30f764476c30 100644
>> --- a/arch/powerpc/xmon/xmon.c
>> +++ b/arch/powerpc/xmon/xmon.c
>> @@ -1160,9 +1160,11 @@ cmds(struct pt_regs *excp)
>> show_tasks();
>> break;
>> #ifdef CONFIG_PPC_BOOK3S
>> +#if defined(CONFIG_PPC32) || defined(CONFIG_PPC_64S_HASH_MMU)
>
> I think you'll get a build failure here.
>
> dump_segments() is defined only with CONFIG_PPC_BOOK3S_64 and
> CONFIG_PPC_BOOK3S_32, see
>
> https://elixir.bootlin.com/linux/v5.15-rc5/source/arch/powerpc/xmon/xmon.c#L3745
>
> and
>
> https://elixir.bootlin.com/linux/v5.15-rc5/source/arch/powerpc/xmon/xmon.c#L3784
AFAIKS it is okay because it still has ifdef BOOK3S?
Thanks,
Nick
^ permalink raw reply
* Re: [PATCH v3 18/18] powerpc/microwatt: Don't select the hash MMU code
From: Nicholas Piggin @ 2021-10-22 9:34 UTC (permalink / raw)
To: Christophe Leroy, linuxppc-dev
In-Reply-To: <85899425-a0cb-7163-7c9c-5ed39a64f8c1@csgroup.eu>
Excerpts from Christophe Leroy's message of October 22, 2021 5:18 pm:
>
>
> Le 22/10/2021 à 00:30, Nicholas Piggin a écrit :
>> Microwatt is radix-only, so it does not require hash MMU support.
>>
>> This saves 20kB compressed dtbImage and 56kB vmlinux size.
>
> I think patch 17 and 18 should be squashed together.
Okay will do. Thanks for the reviews.
Thanks,
Nick
^ permalink raw reply
* Re: [PATCH v3 16/18] powerpc/64s: Move hash MMU support code under CONFIG_PPC_64S_HASH_MMU
From: Christophe Leroy @ 2021-10-22 9:39 UTC (permalink / raw)
To: Nicholas Piggin, linuxppc-dev
In-Reply-To: <1634895021.4d2890ma8z.astroid@bobo.none>
Le 22/10/2021 à 11:34, Nicholas Piggin a écrit :
> Excerpts from Christophe Leroy's message of October 22, 2021 5:18 pm:
>>
>>
>> Le 22/10/2021 à 00:30, Nicholas Piggin a écrit :
>>> diff --git a/arch/powerpc/mm/book3s64/pgtable.c b/arch/powerpc/mm/book3s64/pgtable.c
>>> index 7d556b5513e4..57d2d797c4f6 100644
>>> --- a/arch/powerpc/mm/book3s64/pgtable.c
>>> +++ b/arch/powerpc/mm/book3s64/pgtable.c
>>> @@ -535,7 +535,7 @@ static int __init pgtable_debugfs_setup(void)
>>> }
>>> arch_initcall(pgtable_debugfs_setup);
>>>
>>> -#ifdef CONFIG_ZONE_DEVICE
>>> +#if defined(CONFIG_ZONE_DEVICE) && defined(ARCH_HAS_MEMREMAP_COMPAT_ALIGN)
>>
>> Patch 12 does
>>
>> select ARCH_HAS_MEMREMAP_COMPAT_ALIGN if PPC_BOOK3S_64
>
> Ah, I meant to change that to PPC_64S_HASH_MMU.
You did it later yes.
What I meant is that as you are in book3s64/pgtable.c, you are sure that
ARCH_HAS_MEMREMAP_COMPAT_ALIGN is selected so you don't need to check.
>
>>
>> So this change is not needed
>>
>>> /*
>>> * Override the generic version in mm/memremap.c.
>>> *
>>
>>> diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
>>> index dd8241c009e5..30f764476c30 100644
>>> --- a/arch/powerpc/xmon/xmon.c
>>> +++ b/arch/powerpc/xmon/xmon.c
>>> @@ -1160,9 +1160,11 @@ cmds(struct pt_regs *excp)
>>> show_tasks();
>>> break;
>>> #ifdef CONFIG_PPC_BOOK3S
>>> +#if defined(CONFIG_PPC32) || defined(CONFIG_PPC_64S_HASH_MMU)
>>
>> I think you'll get a build failure here.
>>
>> dump_segments() is defined only with CONFIG_PPC_BOOK3S_64 and
>> CONFIG_PPC_BOOK3S_32, see
>>
>> https://elixir.bootlin.com/linux/v5.15-rc5/source/arch/powerpc/xmon/xmon.c#L3745
>>
>> and
>>
>> https://elixir.bootlin.com/linux/v5.15-rc5/source/arch/powerpc/xmon/xmon.c#L3784
>
> AFAIKS it is okay because it still has ifdef BOOK3S?
>
Ah, I missed it.
But why keep a double ifdef ? instead of just :
#if defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_PPC_64S_HASH_MMU)
^ permalink raw reply
* [powerpc:next-test] BUILD SUCCESS 2974d421aac1374d3269fe4f1fba2068aa33134d
From: kernel test robot @ 2021-10-22 9:41 UTC (permalink / raw)
To: Michael Ellerman; +Cc: linuxppc-dev
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next-test
branch HEAD: 2974d421aac1374d3269fe4f1fba2068aa33134d powerpc/32: Don't use a struct based type for pte_t
elapsed time: 1247m
configs tested: 103
configs skipped: 3
The following configs have been built successfully.
More configs may be tested in the coming days.
gcc tested configs:
arm defconfig
arm64 allyesconfig
arm64 defconfig
arm allyesconfig
arm allmodconfig
i386 randconfig-c001-20211021
arm hackkit_defconfig
sh se7343_defconfig
arm neponset_defconfig
sh sh7710voipgw_defconfig
m68k stmark2_defconfig
arm qcom_defconfig
mips omega2p_defconfig
arm am200epdkit_defconfig
arm assabet_defconfig
sh sh7785lcr_defconfig
arc nsimosci_hs_defconfig
mips ip28_defconfig
mips malta_kvm_defconfig
parisc generic-32bit_defconfig
arm iop32x_defconfig
arm moxart_defconfig
arc haps_hs_smp_defconfig
sh se7751_defconfig
mips rb532_defconfig
openrisc simple_smp_defconfig
arm randconfig-c002-20211021
ia64 allmodconfig
ia64 defconfig
ia64 allyesconfig
m68k allmodconfig
m68k defconfig
m68k allyesconfig
nios2 defconfig
arc allyesconfig
nds32 allnoconfig
nds32 defconfig
nios2 allyesconfig
csky defconfig
alpha defconfig
alpha allyesconfig
xtensa allyesconfig
h8300 allyesconfig
arc defconfig
sh allmodconfig
parisc defconfig
s390 allyesconfig
s390 allmodconfig
parisc allyesconfig
s390 defconfig
i386 allyesconfig
sparc allyesconfig
sparc defconfig
i386 defconfig
i386 debian-10.3
mips allyesconfig
mips allmodconfig
powerpc allyesconfig
powerpc allmodconfig
powerpc allnoconfig
x86_64 randconfig-a013-20211021
x86_64 randconfig-a015-20211021
x86_64 randconfig-a011-20211021
x86_64 randconfig-a014-20211021
x86_64 randconfig-a016-20211021
x86_64 randconfig-a012-20211021
i386 randconfig-a012-20211021
i386 randconfig-a013-20211021
i386 randconfig-a011-20211021
i386 randconfig-a016-20211021
i386 randconfig-a015-20211021
i386 randconfig-a014-20211021
arc randconfig-r043-20211021
riscv randconfig-r042-20211021
s390 randconfig-r044-20211021
riscv nommu_k210_defconfig
riscv allyesconfig
riscv nommu_virt_defconfig
riscv allnoconfig
riscv defconfig
riscv rv32_defconfig
riscv allmodconfig
um x86_64_defconfig
um i386_defconfig
x86_64 allyesconfig
x86_64 rhel-8.3-kselftests
x86_64 defconfig
x86_64 rhel-8.3
x86_64 kexec
clang tested configs:
x86_64 randconfig-a002-20211021
x86_64 randconfig-a004-20211021
x86_64 randconfig-a005-20211021
x86_64 randconfig-a001-20211021
x86_64 randconfig-a006-20211021
x86_64 randconfig-a003-20211021
i386 randconfig-a004-20211021
i386 randconfig-a003-20211021
i386 randconfig-a002-20211021
i386 randconfig-a005-20211021
i386 randconfig-a001-20211021
i386 randconfig-a006-20211021
hexagon randconfig-r045-20211021
hexagon randconfig-r041-20211021
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
^ permalink raw reply
* Re: [PATCH v3 16/18] powerpc/64s: Move hash MMU support code under CONFIG_PPC_64S_HASH_MMU
From: Nicholas Piggin @ 2021-10-22 9:44 UTC (permalink / raw)
To: Christophe Leroy, linuxppc-dev
In-Reply-To: <1634895021.4d2890ma8z.astroid@bobo.none>
Excerpts from Nicholas Piggin's message of October 22, 2021 7:34 pm:
> Excerpts from Christophe Leroy's message of October 22, 2021 5:18 pm:
>>
>>
>> Le 22/10/2021 à 00:30, Nicholas Piggin a écrit :
>>> Compiling out hash support code when CONFIG_PPC_64S_HASH_MMU=n saves
>>> 128kB kernel image size (90kB text) on powernv_defconfig minus KVM,
>>> 350kB on pseries_defconfig minus KVM, 40kB on a tiny config.
>>>
>>> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
>>> ---
>>> arch/powerpc/Kconfig | 2 +-
>>> arch/powerpc/include/asm/book3s/64/mmu.h | 19 +++++++++--
>>> .../include/asm/book3s/64/tlbflush-hash.h | 7 ++++
>>> arch/powerpc/include/asm/book3s/pgtable.h | 4 +++
>>> arch/powerpc/include/asm/mmu_context.h | 2 ++
>>> arch/powerpc/include/asm/paca.h | 8 +++++
>>> arch/powerpc/kernel/asm-offsets.c | 2 ++
>>> arch/powerpc/kernel/entry_64.S | 4 +--
>>> arch/powerpc/kernel/exceptions-64s.S | 16 +++++++++
>>> arch/powerpc/kernel/mce.c | 2 +-
>>> arch/powerpc/kernel/mce_power.c | 10 ++++--
>>> arch/powerpc/kernel/paca.c | 18 ++++------
>>> arch/powerpc/kernel/process.c | 13 +++----
>>> arch/powerpc/kernel/prom.c | 2 ++
>>> arch/powerpc/kernel/setup_64.c | 5 +++
>>> arch/powerpc/kexec/core_64.c | 4 +--
>>> arch/powerpc/kexec/ranges.c | 4 +++
>>> arch/powerpc/mm/book3s64/Makefile | 15 ++++----
>>> arch/powerpc/mm/book3s64/hugetlbpage.c | 2 ++
>>> arch/powerpc/mm/book3s64/mmu_context.c | 34 +++++++++++++++----
>>> arch/powerpc/mm/book3s64/pgtable.c | 2 +-
>>> arch/powerpc/mm/book3s64/radix_pgtable.c | 4 +++
>>> arch/powerpc/mm/copro_fault.c | 2 ++
>>> arch/powerpc/mm/ptdump/Makefile | 2 +-
>>> arch/powerpc/platforms/powernv/idle.c | 2 ++
>>> arch/powerpc/platforms/powernv/setup.c | 2 ++
>>> arch/powerpc/platforms/pseries/lpar.c | 11 ++++--
>>> arch/powerpc/platforms/pseries/lparcfg.c | 2 +-
>>> arch/powerpc/platforms/pseries/mobility.c | 6 ++++
>>> arch/powerpc/platforms/pseries/ras.c | 2 ++
>>> arch/powerpc/platforms/pseries/reconfig.c | 2 ++
>>> arch/powerpc/platforms/pseries/setup.c | 6 ++--
>>> arch/powerpc/xmon/xmon.c | 8 +++--
>>> drivers/misc/lkdtm/Makefile | 2 +-
>>> drivers/misc/lkdtm/core.c | 2 +-
>>> 35 files changed, 177 insertions(+), 51 deletions(-)
>>>
>>
>>> diff --git a/arch/powerpc/include/asm/book3s/64/mmu.h b/arch/powerpc/include/asm/book3s/64/mmu.h
>>> index c02f42d1031e..d94ebae386b6 100644
>>> --- a/arch/powerpc/include/asm/book3s/64/mmu.h
>>> +++ b/arch/powerpc/include/asm/book3s/64/mmu.h
>>> @@ -233,7 +245,8 @@ static inline void setup_initial_memory_limit(phys_addr_t first_memblock_base,
>>> * know which translations we will pick. Hence go with hash
>>> * restrictions.
>>> */
>>> - return hash__setup_initial_memory_limit(first_memblock_base,
>>> + if (!radix_enabled())
>>> + return hash__setup_initial_memory_limit(first_memblock_base,
>>> first_memblock_size);
>>
>> It is a void function, using return is not correct.
>
> I guess for this case I can fix as I go.
>
>>> @@ -112,8 +112,15 @@ static inline void hash__flush_tlb_kernel_range(unsigned long start,
>>>
>>> struct mmu_gather;
>>> extern void hash__tlb_flush(struct mmu_gather *tlb);
>>> +extern void flush_tlb_pmd_range(struct mm_struct *mm, pmd_t *pmd,
>>> + unsigned long addr);
>>
>> 'extern' is superflous
>
> Ditto.
>
>>> @@ -144,12 +147,21 @@ static int hash__init_new_context(struct mm_struct *mm)
>>> return index;
>>> }
>>>
>>> +void slb_setup_new_exec(void);
>>
>> Include arch/powerpc/mm/book3s64/internal.h instead
>
> Will do.
>
>>> diff --git a/arch/powerpc/mm/book3s64/pgtable.c b/arch/powerpc/mm/book3s64/pgtable.c
>>> index 7d556b5513e4..57d2d797c4f6 100644
>>> --- a/arch/powerpc/mm/book3s64/pgtable.c
>>> +++ b/arch/powerpc/mm/book3s64/pgtable.c
>>> @@ -535,7 +535,7 @@ static int __init pgtable_debugfs_setup(void)
>>> }
>>> arch_initcall(pgtable_debugfs_setup);
>>>
>>> -#ifdef CONFIG_ZONE_DEVICE
>>> +#if defined(CONFIG_ZONE_DEVICE) && defined(ARCH_HAS_MEMREMAP_COMPAT_ALIGN)
>>
>> Patch 12 does
>>
>> select ARCH_HAS_MEMREMAP_COMPAT_ALIGN if PPC_BOOK3S_64
>
> Ah, I meant to change that to PPC_64S_HASH_MMU.
Oh I did in this patch, I was looking at the wrong commit.
Thanks,
Nick
^ permalink raw reply
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