From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754029AbeDQOhK (ORCPT ); Tue, 17 Apr 2018 10:37:10 -0400 Received: from mail-yb0-f193.google.com ([209.85.213.193]:38147 "EHLO mail-yb0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752687AbeDQOhG (ORCPT ); Tue, 17 Apr 2018 10:37:06 -0400 X-Google-Smtp-Source: AIpwx4/++qPYpLYz3V2X1Rqg6tjjIfTaq9HzmR3G/dVHHnvJQaIT1WBLv+u43AhPkMXFv7P6xDCcHw== From: "Jingoo Han" To: "'Gustavo Pimentel'" , , , , , , Cc: , , References: <4fc069a2b82cc7a3790bc528a6b67636654a3a35.1523973931.git.gustavo.pimentel@synopsys.com> In-Reply-To: <4fc069a2b82cc7a3790bc528a6b67636654a3a35.1523973931.git.gustavo.pimentel@synopsys.com> Subject: Re: [PATCH v5 09/10] PCI: dwc: Small computation improvement Date: Tue, 17 Apr 2018 10:37:00 -0400 Message-ID: <000001d3d659$8dd02c20$a9708460$@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit X-Mailer: Microsoft Outlook 16.0 Content-Language: en-us Thread-Index: AQHVbgOWkc7ZUiVCjpvNKWyHNduXLQKl7+1qo+ynS+A= Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tuesday, April 17, 2018 10:34 AM, Gustavo Pimentel wrote: > > Replaces a simple division by 2 to a right shift rotation of 1 bit. > > Probably any recent and decent compiler does this kind of substitution > in order to improve code performance. Nevertheless it's a coding good > practice whenever there is a division / multiplication by multiple of 2 > to replace it by the equivalent operation in this case, the shift > rotation. > > Signed-off-by: Gustavo Pimentel Acked-by: Jingoo Han > --- > Change v1->v2: > - Nothing changed, just to follow the patch set version. > Change v2->v3: > - Nothing changed, just to follow the patch set version. > Changes v3->v4: > - Added a small explication to the log description. > Changes v4->v5: > - Nothing changed, just to follow the patch set version. > > drivers/pci/dwc/pcie-designware-host.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/pci/dwc/pcie-designware-host.c > b/drivers/pci/dwc/pcie-designware-host.c > index 5a23f78..fc55fde 100644 > --- a/drivers/pci/dwc/pcie-designware-host.c > +++ b/drivers/pci/dwc/pcie-designware-host.c > @@ -332,8 +332,8 @@ int dw_pcie_host_init(struct pcie_port *pp) > > cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, > "config"); > if (cfg_res) { > - pp->cfg0_size = resource_size(cfg_res) / 2; > - pp->cfg1_size = resource_size(cfg_res) / 2; > + pp->cfg0_size = resource_size(cfg_res) >> 1; > + pp->cfg1_size = resource_size(cfg_res) >> 1; > pp->cfg0_base = cfg_res->start; > pp->cfg1_base = cfg_res->start + pp->cfg0_size; > } else if (!pp->va_cfg0_base) { > @@ -377,8 +377,8 @@ int dw_pcie_host_init(struct pcie_port *pp) > break; > case 0: > pp->cfg = win->res; > - pp->cfg0_size = resource_size(pp->cfg) / 2; > - pp->cfg1_size = resource_size(pp->cfg) / 2; > + pp->cfg0_size = resource_size(pp->cfg) >> 1; > + pp->cfg1_size = resource_size(pp->cfg) >> 1; > pp->cfg0_base = pp->cfg->start; > pp->cfg1_base = pp->cfg->start + pp->cfg0_size; > break; > -- > 2.7.4 >