[PATCH v2 0/2] initial usbdrd phy support for Exynosautov920 soc

[PATCH v2 0/2] initial usbdrd phy support for Exynosautov920 soc

[Pritam Manohar Sutar]

This SoC has a single USB 3.1 DRD combo phy and three USB2.0
DRD phy controllers that only support the UTMI+ interface. 
This SoC is very similar to the existing Exynos850 support
in this driver. We have supported only UTMI+ in this patchset.

The difference is that combo phy supports both UTMI+(HS) and 
PIPE3(SS) and is out of scope in this patchset.

changelog
----------
Changes in v2:
- Used standard GENMASK() and FIELD_GET() to get the major version 
  from controller version register.
  link for v1: https://lore.kernel.org/linux-phy/20250514134813.380807-1-pritam.sutar@samsung.com/

Pritam Manohar Sutar (2):
  dt-bindings: phy: samsung,usb3-drd-phy: add dt-schema for
    ExynosAutov920
  phy: exyons5-usbdrd: support HS phy for ExynosAutov920

 .../bindings/phy/samsung,usb3-drd-phy.yaml    | 27 ++++++
 drivers/phy/samsung/phy-exynos5-usbdrd.c      | 85 +++++++++++++++++++
 2 files changed, 112 insertions(+)

-- 
2.34.1

[PATCH v2 1/2] dt-bindings: phy: samsung,usb3-drd-phy: add dt-schema for ExynosAutov920

[Pritam Manohar Sutar]

Add a dedicated compatible for USB phy found in this SoC

Signed-off-by: Pritam Manohar Sutar <pritam.sutar@samsung.com>
---
 .../bindings/phy/samsung,usb3-drd-phy.yaml    | 27 +++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml
index fdddddc7d611..c50f4218ded9 100644
--- a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml
@@ -32,6 +32,7 @@ properties:
       - samsung,exynos7-usbdrd-phy
       - samsung,exynos7870-usbdrd-phy
       - samsung,exynos850-usbdrd-phy
+      - samsung,exynosautov920-usb31drd-phy
 
   clocks:
     minItems: 2
@@ -204,6 +205,32 @@ allOf:
         reg-names:
           maxItems: 1
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynosautov920-usb31drd-phy
+    then:
+      $ref: /schemas/usb/usb-switch.yaml#
+
+      properties:
+        clocks:
+          items:
+            - description: ext_xtal clock
+            - description: reference clock
+
+        clock-names:
+          items:
+            - const: ext_xtal
+            - const: ref
+
+        reg:
+          minItems: 1
+          maxItems: 1
+
+        reg-names:
+          minItems: 1
+
 unevaluatedProperties: false
 
 examples:
-- 
2.34.1

[PATCH v2 2/2] phy: exyons5-usbdrd: support HS phy for ExynosAutov920

[Pritam Manohar Sutar]

This SoC has a single USB 3.1 DRD combo phy and three USB2.0
DRD HS phy controllers those only support the UTMI+ interface.

Support only UTMI+ for this SoC which is very similar to what
the existing Exynos850 supports.

The combo phy supports both UTMI+ (HS) and PIPE3 (SS) and is
out of scope of this commit.

Add required change in phy driver to support HS phy for this SoC.

Signed-off-by: Pritam Manohar Sutar <pritam.sutar@samsung.com>
---
 drivers/phy/samsung/phy-exynos5-usbdrd.c | 85 ++++++++++++++++++++++++
 1 file changed, 85 insertions(+)

diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c
index 634c4310c660..b440b56c6595 100644
--- a/drivers/phy/samsung/phy-exynos5-usbdrd.c
+++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c
@@ -177,6 +177,9 @@
 #define HSPHYPLLTUNE_PLL_P_TUNE			GENMASK(3, 0)
 
 /* Exynos850: USB DRD PHY registers */
+#define EXYNOSAUTOv920_DRD_CTRL_VER		0x00
+#define CTRL_VER_MAJOR_VERSION			GENMASK(31, 24)
+
 #define EXYNOS850_DRD_LINKCTRL			0x04
 #define LINKCTRL_FORCE_RXELECIDLE		BIT(18)
 #define LINKCTRL_FORCE_PHYSTATUS		BIT(17)
@@ -1772,6 +1775,10 @@ static const char * const exynos5_regulator_names[] = {
 	"vbus", "vbus-boost",
 };
 
+static const char * const exynosautov920_clk_names[] = {
+	"ext_xtal",
+};
+
 static const struct exynos5_usbdrd_phy_drvdata exynos5420_usbdrd_phy = {
 	.phy_cfg		= phy_cfg_exynos5,
 	.phy_ops		= &exynos5_usbdrd_phy_ops,
@@ -1847,6 +1854,81 @@ static const struct exynos5_usbdrd_phy_drvdata exynos850_usbdrd_phy = {
 	.n_regulators		= ARRAY_SIZE(exynos5_regulator_names),
 };
 
+static void exynosautov920_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd)
+{
+	u32 version;
+
+	version = readl(phy_drd->reg_phy + EXYNOSAUTOv920_DRD_CTRL_VER);
+	dev_info(phy_drd->dev, "usbphy: version:0x%x\n", version);
+
+	if (FIELD_GET(CTRL_VER_MAJOR_VERSION, version) == 0x3)
+		/* utmi init for exynosautov920 HS phy */
+		exynos850_usbdrd_utmi_init(phy_drd);
+}
+
+static int exynosautov920_usbdrd_phy_init(struct phy *phy)
+{
+	struct phy_usb_instance *inst = phy_get_drvdata(phy);
+	struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
+	int ret = 0;
+
+	ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks);
+	if (ret)
+		return ret;
+
+	/* UTMI or PIPE3 specific init */
+	inst->phy_cfg->phy_init(phy_drd);
+
+	clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks);
+
+	return 0;
+}
+
+static void exynosautov920_v3p1_phy_dis(struct phy *phy)
+{
+	struct phy_usb_instance *inst = phy_get_drvdata(phy);
+	struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
+	void __iomem *reg_phy = phy_drd->reg_phy;
+	u32 version;
+
+	version = readl(reg_phy + EXYNOSAUTOv920_DRD_CTRL_VER);
+
+	if (FIELD_GET(CTRL_VER_MAJOR_VERSION, version) == 0x3)
+		exynos850_usbdrd_phy_exit(phy);
+}
+
+static int exynosautov920_usbdrd_phy_exit(struct phy *phy)
+{
+	struct phy_usb_instance *inst = phy_get_drvdata(phy);
+
+	if (inst->phy_cfg->id == EXYNOS5_DRDPHY_UTMI)
+		exynosautov920_v3p1_phy_dis(phy);
+
+	return 0;
+}
+
+static const struct phy_ops exynosautov920_usbdrd_phy_ops = {
+	.init		= exynosautov920_usbdrd_phy_init,
+	.exit		= exynosautov920_usbdrd_phy_exit,
+	.owner		= THIS_MODULE,
+};
+
+static const struct exynos5_usbdrd_phy_config phy_cfg_exynosautov920[] = {
+	{
+		.id		= EXYNOS5_DRDPHY_UTMI,
+		.phy_init	= exynosautov920_usbdrd_utmi_init,
+	},
+};
+
+static const struct exynos5_usbdrd_phy_drvdata exynosautov920_usb31drd_phy = {
+	.phy_cfg		= phy_cfg_exynosautov920,
+	.phy_ops		= &exynosautov920_usbdrd_phy_ops,
+	.clk_names		= exynosautov920_clk_names,
+	.n_clks			= ARRAY_SIZE(exynosautov920_clk_names),
+	.core_clk_names		= exynos5_core_clk_names,
+	.n_core_clks		= ARRAY_SIZE(exynos5_core_clk_names),
+};
+
 static const struct exynos5_usbdrd_phy_config phy_cfg_gs101[] = {
 	{
 		.id		= EXYNOS5_DRDPHY_UTMI,
@@ -2047,6 +2129,9 @@ static const struct of_device_id exynos5_usbdrd_phy_of_match[] = {
 	}, {
 		.compatible = "samsung,exynos850-usbdrd-phy",
 		.data = &exynos850_usbdrd_phy
+	}, {
+		.compatible = "samsung,exynosautov920-usb31drd-phy",
+		.data = &exynosautov920_usb31drd_phy
 	},
 	{ },
 };
-- 
2.34.1

Re: [PATCH v2 2/2] phy: exyons5-usbdrd: support HS phy for ExynosAutov920

[neil.armstrong]

On 16/05/2025 12:26, Pritam Manohar Sutar wrote:
> This SoC has a single USB 3.1 DRD combo phy and three USB2.0
> DRD HS phy controllers those only support the UTMI+ interface.
> 
> Support only UTMI+ for this SoC which is very similar to what
> the existing Exynos850 supports.
> 
> The combo phy supports both UTMI+ (HS) and PIPE3 (SS) and is
> out of scope of this commit.
> 
> Add required change in phy driver to support HS phy for this SoC.
> 
> Signed-off-by: Pritam Manohar Sutar <pritam.sutar@samsung.com>
> ---
>   drivers/phy/samsung/phy-exynos5-usbdrd.c | 85 ++++++++++++++++++++++++
>   1 file changed, 85 insertions(+)
> 
> diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c
> index 634c4310c660..b440b56c6595 100644
> --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c
> +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c
> @@ -177,6 +177,9 @@
>   #define HSPHYPLLTUNE_PLL_P_TUNE			GENMASK(3, 0)
>   
>   /* Exynos850: USB DRD PHY registers */
> +#define EXYNOSAUTOv920_DRD_CTRL_VER		0x00
> +#define CTRL_VER_MAJOR_VERSION			GENMASK(31, 24)
> +
>   #define EXYNOS850_DRD_LINKCTRL			0x04
>   #define LINKCTRL_FORCE_RXELECIDLE		BIT(18)
>   #define LINKCTRL_FORCE_PHYSTATUS		BIT(17)
> @@ -1772,6 +1775,10 @@ static const char * const exynos5_regulator_names[] = {
>   	"vbus", "vbus-boost",
>   };
>   
> +static const char * const exynosautov920_clk_names[] = {
> +	"ext_xtal",
> +};
> +
>   static const struct exynos5_usbdrd_phy_drvdata exynos5420_usbdrd_phy = {
>   	.phy_cfg		= phy_cfg_exynos5,
>   	.phy_ops		= &exynos5_usbdrd_phy_ops,
> @@ -1847,6 +1854,81 @@ static const struct exynos5_usbdrd_phy_drvdata exynos850_usbdrd_phy = {
>   	.n_regulators		= ARRAY_SIZE(exynos5_regulator_names),
>   };
>   
> +static void exynosautov920_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd)
> +{
> +	u32 version;
> +
> +	version = readl(phy_drd->reg_phy + EXYNOSAUTOv920_DRD_CTRL_VER);
> +	dev_info(phy_drd->dev, "usbphy: version:0x%x\n", version);

Please do not add mode info to boot log, use dev_dbg instead.

> +
> +	if (FIELD_GET(CTRL_VER_MAJOR_VERSION, version) == 0x3)
> +		/* utmi init for exynosautov920 HS phy */
> +		exynos850_usbdrd_utmi_init(phy_drd);
> +}
> +
> +static int exynosautov920_usbdrd_phy_init(struct phy *phy)
> +{
> +	struct phy_usb_instance *inst = phy_get_drvdata(phy);
> +	struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
> +	int ret = 0;
> +
> +	ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks);
> +	if (ret)
> +		return ret;
> +
> +	/* UTMI or PIPE3 specific init */
> +	inst->phy_cfg->phy_init(phy_drd);
> +
> +	clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks);
> +
> +	return 0;
> +}
> +
> +static void exynosautov920_v3p1_phy_dis(struct phy *phy)
> +{
> +	struct phy_usb_instance *inst = phy_get_drvdata(phy);
> +	struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
> +	void __iomem *reg_phy = phy_drd->reg_phy;
> +	u32 version;
> +
> +	version = readl(reg_phy + EXYNOSAUTOv920_DRD_CTRL_VER);
> +
> +	if (FIELD_GET(CTRL_VER_MAJOR_VERSION, version) == 0x3)
> +		exynos850_usbdrd_phy_exit(phy);
> +}
> +
> +static int exynosautov920_usbdrd_phy_exit(struct phy *phy)
> +{
> +	struct phy_usb_instance *inst = phy_get_drvdata(phy);
> +
> +	if (inst->phy_cfg->id == EXYNOS5_DRDPHY_UTMI)
> +		exynosautov920_v3p1_phy_dis(phy);
> +
> +	return 0;
> +}
> +
> +static const struct phy_ops exynosautov920_usbdrd_phy_ops = {
> +	.init		= exynosautov920_usbdrd_phy_init,
> +	.exit		= exynosautov920_usbdrd_phy_exit,

<snip>

> +		.id		= EXYNOS5_DRDPHY_UTMI,
> +		.phy_init	= exynosautov920_usbdrd_utmi_init,

<snip>

> +	}, {
> +		.compatible = "samsung,exynosautov920-usb31drd-phy",
> +		.data = &exynosautov920_usb31drd_phy

All those new ops are only called when matching this compatible, it it really
necessary to check the version ? is there "samsung,exynosautov920-usb31drd-phy" PHYs
with version different from 3 in the wild ?

Neil

>   	},
>   	{ },
>   };

Re: [PATCH v2 2/2] phy: exyons5-usbdrd: support HS phy for ExynosAutov920

[Krzysztof Kozlowski]

On 20/05/2025 09:39, neil.armstrong@linaro.org wrote:
>> diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c
>> index 634c4310c660..b440b56c6595 100644
>> --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c
>> +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c
>> @@ -177,6 +177,9 @@
>>   #define HSPHYPLLTUNE_PLL_P_TUNE			GENMASK(3, 0)
>>   
>>   /* Exynos850: USB DRD PHY registers */
>> +#define EXYNOSAUTOv920_DRD_CTRL_VER		0x00
>> +#define CTRL_VER_MAJOR_VERSION			GENMASK(31, 24)
>> +
>>   #define EXYNOS850_DRD_LINKCTRL			0x04
>>   #define LINKCTRL_FORCE_RXELECIDLE		BIT(18)
>>   #define LINKCTRL_FORCE_PHYSTATUS		BIT(17)
>> @@ -1772,6 +1775,10 @@ static const char * const exynos5_regulator_names[] = {
>>   	"vbus", "vbus-boost",
>>   };
>>   
>> +static const char * const exynosautov920_clk_names[] = {
>> +	"ext_xtal",
>> +};
>> +
>>   static const struct exynos5_usbdrd_phy_drvdata exynos5420_usbdrd_phy = {
>>   	.phy_cfg		= phy_cfg_exynos5,
>>   	.phy_ops		= &exynos5_usbdrd_phy_ops,
>> @@ -1847,6 +1854,81 @@ static const struct exynos5_usbdrd_phy_drvdata exynos850_usbdrd_phy = {
>>   	.n_regulators		= ARRAY_SIZE(exynos5_regulator_names),
>>   };
>>   
>> +static void exynosautov920_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd)
>> +{
>> +	u32 version;
>> +
>> +	version = readl(phy_drd->reg_phy + EXYNOSAUTOv920_DRD_CTRL_VER);
>> +	dev_info(phy_drd->dev, "usbphy: version:0x%x\n", version);
> 
> Please do not add mode info to boot log, use dev_dbg instead.

Just drop entirely, not even worth dbg (see coding style, driver
development debugging guide). It is fixed per given compatible, isn't
it? If not, there is entire commit msg to explain unusual things.

> 
>> +
>> +	if (FIELD_GET(CTRL_VER_MAJOR_VERSION, version) == 0x3)
>> +		/* utmi init for exynosautov920 HS phy */
>> +		exynos850_usbdrd_utmi_init(phy_drd);
>> +}
>> +
>> +static int exynosautov920_usbdrd_phy_init(struct phy *phy)
>> +{
>> +	struct phy_usb_instance *inst = phy_get_drvdata(phy);
>> +	struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
>> +	int ret = 0;
>> +
>> +	ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks);
>> +	if (ret)
>> +		return ret;
>> +
>> +	/* UTMI or PIPE3 specific init */
>> +	inst->phy_cfg->phy_init(phy_drd);
>> +
>> +	clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks);
>> +
>> +	return 0;
>> +}
>> +
>> +static void exynosautov920_v3p1_phy_dis(struct phy *phy)
>> +{
>> +	struct phy_usb_instance *inst = phy_get_drvdata(phy);
>> +	struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
>> +	void __iomem *reg_phy = phy_drd->reg_phy;
>> +	u32 version;
>> +
>> +	version = readl(reg_phy + EXYNOSAUTOv920_DRD_CTRL_VER);
>> +
>> +	if (FIELD_GET(CTRL_VER_MAJOR_VERSION, version) == 0x3)
>> +		exynos850_usbdrd_phy_exit(phy);
>> +}
>> +
>> +static int exynosautov920_usbdrd_phy_exit(struct phy *phy)
>> +{
>> +	struct phy_usb_instance *inst = phy_get_drvdata(phy);
>> +
>> +	if (inst->phy_cfg->id == EXYNOS5_DRDPHY_UTMI)
>> +		exynosautov920_v3p1_phy_dis(phy);
>> +
>> +	return 0;
>> +}
>> +
>> +static const struct phy_ops exynosautov920_usbdrd_phy_ops = {
>> +	.init		= exynosautov920_usbdrd_phy_init,
>> +	.exit		= exynosautov920_usbdrd_phy_exit,
> 
> <snip>
> 
>> +		.id		= EXYNOS5_DRDPHY_UTMI,
>> +		.phy_init	= exynosautov920_usbdrd_utmi_init,
> 
> <snip>
> 
>> +	}, {
>> +		.compatible = "samsung,exynosautov920-usb31drd-phy",
>> +		.data = &exynosautov920_usb31drd_phy
> 
> All those new ops are only called when matching this compatible, it it really
> necessary to check the version ? is there "samsung,exynosautov920-usb31drd-phy" PHYs
> with version different from 3 in the wild ?


Yeah, this looks like downstream code. Anyway this would need
explanation in the commit msg.

Best regards,
Krzysztof

Re: [PATCH v2 1/2] dt-bindings: phy: samsung,usb3-drd-phy: add dt-schema for ExynosAutov920

[Krzysztof Kozlowski]

On 16/05/2025 12:26, Pritam Manohar Sutar wrote:
> Add a dedicated compatible for USB phy found in this SoC
> 
> Signed-off-by: Pritam Manohar Sutar <pritam.sutar@samsung.com>
> ---
>  .../bindings/phy/samsung,usb3-drd-phy.yaml    | 27 +++++++++++++++++++
>  1 file changed, 27 insertions(+)

A nit, subject: drop second/last, redundant "dt-schema for". The
"dt-bindings" prefix is already stating that these are bindings in
dtschema format.
See also:
https://elixir.bootlin.com/linux/v6.7-rc8/source/Documentation/devicetree/bindings/submitting-patches.rst#L18

> 
> diff --git a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml
> index fdddddc7d611..c50f4218ded9 100644
> --- a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml
> +++ b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml
> @@ -32,6 +32,7 @@ properties:
>        - samsung,exynos7-usbdrd-phy
>        - samsung,exynos7870-usbdrd-phy
>        - samsung,exynos850-usbdrd-phy
> +      - samsung,exynosautov920-usb31drd-phy
>  
>    clocks:
>      minItems: 2
> @@ -204,6 +205,32 @@ allOf:
>          reg-names:
>            maxItems: 1
>  
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: samsung,exynosautov920-usb31drd-phy
> +    then:
> +      $ref: /schemas/usb/usb-switch.yaml#
> +
> +      properties:
> +        clocks:
> +          items:

Why there is no main PHY clock?

> +            - description: ext_xtal clock
> +            - description: reference clock

Both external oscillator and reference clocks? What are these clocks?

> +
> +        clock-names:
> +          items:
> +            - const: ext_xtal
> +            - const: ref
> +
> +        reg:
> +          minItems: 1

No, there is no such syntax. Drop.

> +          maxItems: 1
> +
> +        reg-names:
> +          minItems: 1

No, look at existing code and do the same.

> +
>  unevaluatedProperties: false
>  
>  examples:


Best regards,
Krzysztof

RE: [PATCH v2 1/2] dt-bindings: phy: samsung,usb3-drd-phy: add dt-schema for ExynosAutov920

[Pritam Manohar Sutar]

Hi Krzysztof, 

Thank you for the reviewing the patches.

> -----Original Message-----
> From: Krzysztof Kozlowski <krzk@kernel.org>
> Sent: 20 May 2025 01:15 PM
> To: Pritam Manohar Sutar <pritam.sutar@samsung.com>; vkoul@kernel.org;
> kishon@kernel.org; robh@kernel.org; krzk+dt@kernel.org;
> conor+dt@kernel.org; alim.akhtar@samsung.com; andre.draszik@linaro.org;
> peter.griffin@linaro.org; kauschluss@disroot.org;
> m.szyprowski@samsung.com; s.nawrocki@samsung.com
> Cc: linux-phy@lists.infradead.org; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-samsung-
> soc@vger.kernel.org; rosa.pila@samsung.com; dev.tailor@samsung.com;
> faraz.ata@samsung.com; muhammed.ali@samsung.com;
> selvarasu.g@samsung.com
> Subject: Re: [PATCH v2 1/2] dt-bindings: phy: samsung,usb3-drd-phy: add dt-
> schema for ExynosAutov920
> 
> On 16/05/2025 12:26, Pritam Manohar Sutar wrote:
> > Add a dedicated compatible for USB phy found in this SoC
> >
> > Signed-off-by: Pritam Manohar Sutar <pritam.sutar@samsung.com>
> > ---
> >  .../bindings/phy/samsung,usb3-drd-phy.yaml    | 27 +++++++++++++++++++
> >  1 file changed, 27 insertions(+)
> 
> A nit, subject: drop second/last, redundant "dt-schema for". The "dt-bindings"
> prefix is already stating that these are bindings in dtschema format.
> See also:
> https://protect2.fireeye.com/v1/url?k=e78ee20f-b815db03-e78f6940-
> 000babff3563-8256a76d4c2ebd67&q=1&e=1643274a-07fa-4563-af27-
> b2f2eff30417&u=https%3A%2F%2Felixir.bootlin.com%2Flinux%2Fv6.7-
> rc8%2Fsource%2FDocumentation%2Fdevicetree%2Fbindings%2Fsubmitting-
> patches.rst%23L18
> 

Will update the commit title as below
"dt-bindings: phy: samsung,usb3-drd-phy: add ExynosAutov920 compatible"

> >
> > diff --git
> > a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml
> > b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml
> > index fdddddc7d611..c50f4218ded9 100644
> > --- a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml
> > +++ b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml
> > @@ -32,6 +32,7 @@ properties:
> >        - samsung,exynos7-usbdrd-phy
> >        - samsung,exynos7870-usbdrd-phy
> >        - samsung,exynos850-usbdrd-phy
> > +      - samsung,exynosautov920-usb31drd-phy
> >
> >    clocks:
> >      minItems: 2
> > @@ -204,6 +205,32 @@ allOf:
> >          reg-names:
> >            maxItems: 1
> >
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          contains:
> > +            const: samsung,exynosautov920-usb31drd-phy
> > +    then:
> > +      $ref: /schemas/usb/usb-switch.yaml#
> > +
> > +      properties:
> > +        clocks:
> > +          items:
> 
> Why there is no main PHY clock?

external crystal clk (ext_xtal) is used as main phy clk.

> 
> > +            - description: ext_xtal clock
> > +            - description: reference clock
> 
> Both external oscillator and reference clocks? What are these clocks?

ext_xtal is used as PHY clock to access register and reference clock 
for PHY operations.

Will add more description in patch.

> 
> > +
> > +        clock-names:
> > +          items:
> > +            - const: ext_xtal
> > +            - const: ref
> > +
> > +        reg:
> > +          minItems: 1
> 
> No, there is no such syntax. Drop.

Will remove this

> 
> > +          maxItems: 1
> > +
> > +        reg-names:
> > +          minItems: 1
> 
> No, look at existing code and do the same.

Will replace "minItems"  by "maxItems"

> 
> > +
> >  unevaluatedProperties: false
> >
> >  examples:
> 
> 
> Best regards,
> Krzysztof

Thank you. 

RE: [PATCH v2 2/2] phy: exyons5-usbdrd: support HS phy for ExynosAutov920

[Pritam Manohar Sutar]

Hi Neil,

Thank you for reviewing the patches.

> -----Original Message-----
> From: neil.armstrong@linaro.org <neil.armstrong@linaro.org>
> Sent: 20 May 2025 01:10 PM
> To: Pritam Manohar Sutar <pritam.sutar@samsung.com>; vkoul@kernel.org;
> kishon@kernel.org; robh@kernel.org; krzk+dt@kernel.org;
> conor+dt@kernel.org; alim.akhtar@samsung.com; andre.draszik@linaro.org;
> peter.griffin@linaro.org; kauschluss@disroot.org;
> m.szyprowski@samsung.com; s.nawrocki@samsung.com
> Cc: linux-phy@lists.infradead.org; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-samsung-
> soc@vger.kernel.org; rosa.pila@samsung.com; dev.tailor@samsung.com;
> faraz.ata@samsung.com; muhammed.ali@samsung.com;
> selvarasu.g@samsung.com
> Subject: Re: [PATCH v2 2/2] phy: exyons5-usbdrd: support HS phy for
> ExynosAutov920
> 
> On 16/05/2025 12:26, Pritam Manohar Sutar wrote:
> > This SoC has a single USB 3.1 DRD combo phy and three USB2.0 DRD HS
> > phy controllers those only support the UTMI+ interface.
> >
> > Support only UTMI+ for this SoC which is very similar to what the
> > existing Exynos850 supports.
> >
> > The combo phy supports both UTMI+ (HS) and PIPE3 (SS) and is out of
> > scope of this commit.
> >
> > Add required change in phy driver to support HS phy for this SoC.
> >
> > Signed-off-by: Pritam Manohar Sutar <pritam.sutar@samsung.com>
> > ---
> >   drivers/phy/samsung/phy-exynos5-usbdrd.c | 85
> ++++++++++++++++++++++++
> >   1 file changed, 85 insertions(+)
> >
> > diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c
> > b/drivers/phy/samsung/phy-exynos5-usbdrd.c
> > index 634c4310c660..b440b56c6595 100644
> > --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c
> > +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c
> > @@ -177,6 +177,9 @@
> >   #define HSPHYPLLTUNE_PLL_P_TUNE			GENMASK(3, 0)
> >
> >   /* Exynos850: USB DRD PHY registers */
> > +#define EXYNOSAUTOv920_DRD_CTRL_VER		0x00
> > +#define CTRL_VER_MAJOR_VERSION			GENMASK(31, 24)
> > +
> >   #define EXYNOS850_DRD_LINKCTRL			0x04
> >   #define LINKCTRL_FORCE_RXELECIDLE		BIT(18)
> >   #define LINKCTRL_FORCE_PHYSTATUS		BIT(17)
> > @@ -1772,6 +1775,10 @@ static const char * const
> exynos5_regulator_names[] = {
> >   	"vbus", "vbus-boost",
> >   };
> >
> > +static const char * const exynosautov920_clk_names[] = {
> > +	"ext_xtal",
> > +};
> > +
> >   static const struct exynos5_usbdrd_phy_drvdata exynos5420_usbdrd_phy = {
> >   	.phy_cfg		= phy_cfg_exynos5,
> >   	.phy_ops		= &exynos5_usbdrd_phy_ops,
> > @@ -1847,6 +1854,81 @@ static const struct exynos5_usbdrd_phy_drvdata
> exynos850_usbdrd_phy = {
> >   	.n_regulators		= ARRAY_SIZE(exynos5_regulator_names),
> >   };
> >
> > +static void exynosautov920_usbdrd_utmi_init(struct exynos5_usbdrd_phy
> > +*phy_drd) {
> > +	u32 version;
> > +
> > +	version = readl(phy_drd->reg_phy +
> EXYNOSAUTOv920_DRD_CTRL_VER);
> > +	dev_info(phy_drd->dev, "usbphy: version:0x%x\n", version);
> 
> Please do not add mode info to boot log, use dev_dbg instead.

Will replace dev_info by dev_dbg.

> 
> > +
> > +	if (FIELD_GET(CTRL_VER_MAJOR_VERSION, version) == 0x3)
> > +		/* utmi init for exynosautov920 HS phy */
> > +		exynos850_usbdrd_utmi_init(phy_drd);
> > +}
> > +
> > +static int exynosautov920_usbdrd_phy_init(struct phy *phy) {
> > +	struct phy_usb_instance *inst = phy_get_drvdata(phy);
> > +	struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
> > +	int ret = 0;
> > +
> > +	ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd-
> >clks);
> > +	if (ret)
> > +		return ret;
> > +
> > +	/* UTMI or PIPE3 specific init */
> > +	inst->phy_cfg->phy_init(phy_drd);
> > +
> > +	clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks,
> > +phy_drd->clks);
> > +
> > +	return 0;
> > +}
> > +
> > +static void exynosautov920_v3p1_phy_dis(struct phy *phy) {
> > +	struct phy_usb_instance *inst = phy_get_drvdata(phy);
> > +	struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
> > +	void __iomem *reg_phy = phy_drd->reg_phy;
> > +	u32 version;
> > +
> > +	version = readl(reg_phy + EXYNOSAUTOv920_DRD_CTRL_VER);
> > +
> > +	if (FIELD_GET(CTRL_VER_MAJOR_VERSION, version) == 0x3)
> > +		exynos850_usbdrd_phy_exit(phy);
> > +}
> > +
> > +static int exynosautov920_usbdrd_phy_exit(struct phy *phy) {
> > +	struct phy_usb_instance *inst = phy_get_drvdata(phy);
> > +
> > +	if (inst->phy_cfg->id == EXYNOS5_DRDPHY_UTMI)
> > +		exynosautov920_v3p1_phy_dis(phy);
> > +
> > +	return 0;
> > +}
> > +
> > +static const struct phy_ops exynosautov920_usbdrd_phy_ops = {
> > +	.init		= exynosautov920_usbdrd_phy_init,
> > +	.exit		= exynosautov920_usbdrd_phy_exit,
> 
> <snip>
> 
> > +		.id		= EXYNOS5_DRDPHY_UTMI,
> > +		.phy_init	= exynosautov920_usbdrd_utmi_init,
> 
> <snip>
> 
> > +	}, {
> > +		.compatible = "samsung,exynosautov920-usb31drd-phy",
> > +		.data = &exynosautov920_usb31drd_phy
> 
> All those new ops are only called when matching this compatible, it it really
> necessary to check the version ? is there "samsung,exynosautov920-usb31drd-
> phy" PHYs with version different from 3 in the wild ?
> 

This SoC has a single USB 3.1 DRD combo phy of version v400 (major : minor versions) and three USB2.0
DRD phy v303 (major : minor versions) controllers those only support the UTMI+ interface. Currently, 
supporting only v303 phys in this patch-set, and planning v400 phy later (soon). 

Yes, there's v400 phy version that is different from v303 phy. Hence, phy version check is needed to support both the phys for same compatible.

> Neil
> 
> >   	},
> >   	{ },
> >   };


Thank you,
Pritam

RE: [PATCH v2 2/2] phy: exyons5-usbdrd: support HS phy for ExynosAutov920

[Pritam Manohar Sutar]

Hi Krzysztof,

> -----Original Message-----
> From: Krzysztof Kozlowski <krzk@kernel.org>
> Sent: 20 May 2025 01:13 PM
> To: Neil Armstrong <neil.armstrong@linaro.org>; Pritam Manohar Sutar
> <pritam.sutar@samsung.com>; vkoul@kernel.org; kishon@kernel.org;
> robh@kernel.org; krzk+dt@kernel.org; conor+dt@kernel.org;
> alim.akhtar@samsung.com; andre.draszik@linaro.org; peter.griffin@linaro.org;
> kauschluss@disroot.org; m.szyprowski@samsung.com;
> s.nawrocki@samsung.com
> Cc: linux-phy@lists.infradead.org; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-samsung-
> soc@vger.kernel.org; rosa.pila@samsung.com; dev.tailor@samsung.com;
> faraz.ata@samsung.com; muhammed.ali@samsung.com;
> selvarasu.g@samsung.com
> Subject: Re: [PATCH v2 2/2] phy: exyons5-usbdrd: support HS phy for
> ExynosAutov920
> 
> On 20/05/2025 09:39, neil.armstrong@linaro.org wrote:
> >> diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c
> >> b/drivers/phy/samsung/phy-exynos5-usbdrd.c
> >> index 634c4310c660..b440b56c6595 100644
> >> --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c
> >> +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c
> >> @@ -177,6 +177,9 @@
> >>   #define HSPHYPLLTUNE_PLL_P_TUNE			GENMASK(3,
> 0)
> >>
> >>   /* Exynos850: USB DRD PHY registers */
> >> +#define EXYNOSAUTOv920_DRD_CTRL_VER		0x00
> >> +#define CTRL_VER_MAJOR_VERSION			GENMASK(31,
> 24)
> >> +
> >>   #define EXYNOS850_DRD_LINKCTRL			0x04
> >>   #define LINKCTRL_FORCE_RXELECIDLE		BIT(18)
> >>   #define LINKCTRL_FORCE_PHYSTATUS		BIT(17)
> >> @@ -1772,6 +1775,10 @@ static const char * const
> exynos5_regulator_names[] = {
> >>   	"vbus", "vbus-boost",
> >>   };
> >>
> >> +static const char * const exynosautov920_clk_names[] = {
> >> +	"ext_xtal",
> >> +};
> >> +
> >>   static const struct exynos5_usbdrd_phy_drvdata exynos5420_usbdrd_phy =
> {
> >>   	.phy_cfg		= phy_cfg_exynos5,
> >>   	.phy_ops		= &exynos5_usbdrd_phy_ops,
> >> @@ -1847,6 +1854,81 @@ static const struct exynos5_usbdrd_phy_drvdata
> exynos850_usbdrd_phy = {
> >>   	.n_regulators		= ARRAY_SIZE(exynos5_regulator_names),
> >>   };
> >>
> >> +static void exynosautov920_usbdrd_utmi_init(struct
> >> +exynos5_usbdrd_phy *phy_drd) {
> >> +	u32 version;
> >> +
> >> +	version = readl(phy_drd->reg_phy +
> EXYNOSAUTOv920_DRD_CTRL_VER);
> >> +	dev_info(phy_drd->dev, "usbphy: version:0x%x\n", version);
> >
> > Please do not add mode info to boot log, use dev_dbg instead.
> 
> Just drop entirely, not even worth dbg (see coding style, driver development
> debugging guide). It is fixed per given compatible, isn't it? If not, there is entire
> commit msg to explain unusual things.

This SoC has a single USB 3.1 DRD combo v400 phy and three USB2.0 DRD phy v303
controllers those only support the UTMI+ interface. Currently, supporting only 
v303 phy in this patch-set, and planning v400 phy later (soon). Same may be 
also updated in commit  message. 

If there's any issue in phy init, dbg print is needed to debug which phy caused it. 

> 
> >
> >> +
> >> +	if (FIELD_GET(CTRL_VER_MAJOR_VERSION, version) == 0x3)
> >> +		/* utmi init for exynosautov920 HS phy */
> >> +		exynos850_usbdrd_utmi_init(phy_drd);
> >> +}
> >> +
> >> +static int exynosautov920_usbdrd_phy_init(struct phy *phy) {
> >> +	struct phy_usb_instance *inst = phy_get_drvdata(phy);
> >> +	struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
> >> +	int ret = 0;
> >> +
> >> +	ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd-
> >clks);
> >> +	if (ret)
> >> +		return ret;
> >> +
> >> +	/* UTMI or PIPE3 specific init */
> >> +	inst->phy_cfg->phy_init(phy_drd);
> >> +
> >> +	clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks,
> >> +phy_drd->clks);
> >> +
> >> +	return 0;
> >> +}
> >> +
> >> +static void exynosautov920_v3p1_phy_dis(struct phy *phy) {
> >> +	struct phy_usb_instance *inst = phy_get_drvdata(phy);
> >> +	struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
> >> +	void __iomem *reg_phy = phy_drd->reg_phy;
> >> +	u32 version;
> >> +
> >> +	version = readl(reg_phy + EXYNOSAUTOv920_DRD_CTRL_VER);
> >> +
> >> +	if (FIELD_GET(CTRL_VER_MAJOR_VERSION, version) == 0x3)
> >> +		exynos850_usbdrd_phy_exit(phy);
> >> +}
> >> +
> >> +static int exynosautov920_usbdrd_phy_exit(struct phy *phy) {
> >> +	struct phy_usb_instance *inst = phy_get_drvdata(phy);
> >> +
> >> +	if (inst->phy_cfg->id == EXYNOS5_DRDPHY_UTMI)
> >> +		exynosautov920_v3p1_phy_dis(phy);
> >> +
> >> +	return 0;
> >> +}
> >> +
> >> +static const struct phy_ops exynosautov920_usbdrd_phy_ops = {
> >> +	.init		= exynosautov920_usbdrd_phy_init,
> >> +	.exit		= exynosautov920_usbdrd_phy_exit,
> >
> > <snip>
> >
> >> +		.id		= EXYNOS5_DRDPHY_UTMI,
> >> +		.phy_init	= exynosautov920_usbdrd_utmi_init,
> >
> > <snip>
> >
> >> +	}, {
> >> +		.compatible = "samsung,exynosautov920-usb31drd-phy",
> >> +		.data = &exynosautov920_usb31drd_phy
> >
> > All those new ops are only called when matching this compatible, it it
> > really necessary to check the version ? is there
> > "samsung,exynosautov920-usb31drd-phy" PHYs with version different from 3
> in the wild ?
> 
> 
> Yeah, this looks like downstream code. Anyway this would need explanation in
> the commit msg.

Commit msg can be updated as mentioned below 

" This SoC has a single USB 3.1 DRD combo v400 phy that supports 
both UTMI+ (HS) and PIPE3 (SS) and three USB2.0 DRD v303 phy 
controllers those only support the UTMI+ (HS) interface. 
	
Support only HS phy in this commit which is very similar to what
the existing Exynos850 supports.

Support combo phy later (soon) and this is out of scope of this commit.

Add required change in phy driver to support HS phy for this SoC."

> 
> Best regards,
> Krzysztof

Thank you,
Pritam

Re: [PATCH v2 1/2] dt-bindings: phy: samsung,usb3-drd-phy: add dt-schema for ExynosAutov920

[Krzysztof Kozlowski]

On 21/05/2025 08:48, Pritam Manohar Sutar wrote:
>>> diff --git
>>> a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml
>>> b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml
>>> index fdddddc7d611..c50f4218ded9 100644
>>> --- a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml
>>> +++ b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml
>>> @@ -32,6 +32,7 @@ properties:
>>>        - samsung,exynos7-usbdrd-phy
>>>        - samsung,exynos7870-usbdrd-phy
>>>        - samsung,exynos850-usbdrd-phy
>>> +      - samsung,exynosautov920-usb31drd-phy
>>>
>>>    clocks:
>>>      minItems: 2
>>> @@ -204,6 +205,32 @@ allOf:
>>>          reg-names:
>>>            maxItems: 1
>>>
>>> +  - if:
>>> +      properties:
>>> +        compatible:
>>> +          contains:
>>> +            const: samsung,exynosautov920-usb31drd-phy
>>> +    then:
>>> +      $ref: /schemas/usb/usb-switch.yaml#
>>> +
>>> +      properties:
>>> +        clocks:
>>> +          items:
>>
>> Why there is no main PHY clock?
> 
> external crystal clk (ext_xtal) is used as main phy clk.

So this is the main phy clock? This describes the clock input, not what
you have on your board. If you change external crystal to internal clock
in one design, you change the binding? No, this makes no sense.



Best regards,
Krzysztof

Re: [PATCH v2 2/2] phy: exyons5-usbdrd: support HS phy for ExynosAutov920

[Krzysztof Kozlowski]

On 21/05/2025 09:10, Pritam Manohar Sutar wrote:
> Hi Krzysztof,
> 
>> -----Original Message-----
>> From: Krzysztof Kozlowski <krzk@kernel.org>
>> Sent: 20 May 2025 01:13 PM
>> To: Neil Armstrong <neil.armstrong@linaro.org>; Pritam Manohar Sutar
>> <pritam.sutar@samsung.com>; vkoul@kernel.org; kishon@kernel.org;
>> robh@kernel.org; krzk+dt@kernel.org; conor+dt@kernel.org;
>> alim.akhtar@samsung.com; andre.draszik@linaro.org; peter.griffin@linaro.org;
>> kauschluss@disroot.org; m.szyprowski@samsung.com;
>> s.nawrocki@samsung.com
>> Cc: linux-phy@lists.infradead.org; devicetree@vger.kernel.org; linux-
>> kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-samsung-
>> soc@vger.kernel.org; rosa.pila@samsung.com; dev.tailor@samsung.com;
>> faraz.ata@samsung.com; muhammed.ali@samsung.com;
>> selvarasu.g@samsung.com
>> Subject: Re: [PATCH v2 2/2] phy: exyons5-usbdrd: support HS phy for
>> ExynosAutov920
>>
>> On 20/05/2025 09:39, neil.armstrong@linaro.org wrote:
>>>> diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c
>>>> b/drivers/phy/samsung/phy-exynos5-usbdrd.c
>>>> index 634c4310c660..b440b56c6595 100644
>>>> --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c
>>>> +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c
>>>> @@ -177,6 +177,9 @@
>>>>   #define HSPHYPLLTUNE_PLL_P_TUNE			GENMASK(3,
>> 0)
>>>>
>>>>   /* Exynos850: USB DRD PHY registers */
>>>> +#define EXYNOSAUTOv920_DRD_CTRL_VER		0x00
>>>> +#define CTRL_VER_MAJOR_VERSION			GENMASK(31,
>> 24)
>>>> +
>>>>   #define EXYNOS850_DRD_LINKCTRL			0x04
>>>>   #define LINKCTRL_FORCE_RXELECIDLE		BIT(18)
>>>>   #define LINKCTRL_FORCE_PHYSTATUS		BIT(17)
>>>> @@ -1772,6 +1775,10 @@ static const char * const
>> exynos5_regulator_names[] = {
>>>>   	"vbus", "vbus-boost",
>>>>   };
>>>>
>>>> +static const char * const exynosautov920_clk_names[] = {
>>>> +	"ext_xtal",
>>>> +};
>>>> +
>>>>   static const struct exynos5_usbdrd_phy_drvdata exynos5420_usbdrd_phy =
>> {
>>>>   	.phy_cfg		= phy_cfg_exynos5,
>>>>   	.phy_ops		= &exynos5_usbdrd_phy_ops,
>>>> @@ -1847,6 +1854,81 @@ static const struct exynos5_usbdrd_phy_drvdata
>> exynos850_usbdrd_phy = {
>>>>   	.n_regulators		= ARRAY_SIZE(exynos5_regulator_names),
>>>>   };
>>>>
>>>> +static void exynosautov920_usbdrd_utmi_init(struct
>>>> +exynos5_usbdrd_phy *phy_drd) {
>>>> +	u32 version;
>>>> +
>>>> +	version = readl(phy_drd->reg_phy +
>> EXYNOSAUTOv920_DRD_CTRL_VER);
>>>> +	dev_info(phy_drd->dev, "usbphy: version:0x%x\n", version);
>>>
>>> Please do not add mode info to boot log, use dev_dbg instead.
>>
>> Just drop entirely, not even worth dbg (see coding style, driver development
>> debugging guide). It is fixed per given compatible, isn't it? If not, there is entire
>> commit msg to explain unusual things.
> 
> This SoC has a single USB 3.1 DRD combo v400 phy and three USB2.0 DRD phy v303


That's a different device, no? Look at the compatible here - it says
usb31drd.

What does 31 stand for?

> controllers those only support the UTMI+ interface. Currently, supporting only 
> v303 phy in this patch-set, and planning v400 phy later (soon). Same may be 
> also updated in commit  message. 
> 
> If there's any issue in phy init, dbg print is needed to debug which phy caused it. 
No, rethink rather this makes sense at all. Please read carefully
writing bindings, which will tell you that you cannot have different
devices under the same compatible. Unless you say these are the same
devices and it differs by other phy? But this is a phy... so many questions.

Best regards,
Krzysztof

Re: [PATCH v2 2/2] phy: exyons5-usbdrd: support HS phy for ExynosAutov920

[Krzysztof Kozlowski]

On 21/05/2025 10:47, Krzysztof Kozlowski wrote:
> On 21/05/2025 09:10, Pritam Manohar Sutar wrote:
>> Hi Krzysztof,
>>
>>> -----Original Message-----
>>> From: Krzysztof Kozlowski <krzk@kernel.org>
>>> Sent: 20 May 2025 01:13 PM
>>> To: Neil Armstrong <neil.armstrong@linaro.org>; Pritam Manohar Sutar
>>> <pritam.sutar@samsung.com>; vkoul@kernel.org; kishon@kernel.org;
>>> robh@kernel.org; krzk+dt@kernel.org; conor+dt@kernel.org;
>>> alim.akhtar@samsung.com; andre.draszik@linaro.org; peter.griffin@linaro.org;
>>> kauschluss@disroot.org; m.szyprowski@samsung.com;
>>> s.nawrocki@samsung.com
>>> Cc: linux-phy@lists.infradead.org; devicetree@vger.kernel.org; linux-
>>> kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-samsung-
>>> soc@vger.kernel.org; rosa.pila@samsung.com; dev.tailor@samsung.com;
>>> faraz.ata@samsung.com; muhammed.ali@samsung.com;
>>> selvarasu.g@samsung.com
>>> Subject: Re: [PATCH v2 2/2] phy: exyons5-usbdrd: support HS phy for
>>> ExynosAutov920
>>>
>>> On 20/05/2025 09:39, neil.armstrong@linaro.org wrote:
>>>>> diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c
>>>>> b/drivers/phy/samsung/phy-exynos5-usbdrd.c
>>>>> index 634c4310c660..b440b56c6595 100644
>>>>> --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c
>>>>> +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c
>>>>> @@ -177,6 +177,9 @@
>>>>>   #define HSPHYPLLTUNE_PLL_P_TUNE			GENMASK(3,
>>> 0)
>>>>>
>>>>>   /* Exynos850: USB DRD PHY registers */
>>>>> +#define EXYNOSAUTOv920_DRD_CTRL_VER		0x00
>>>>> +#define CTRL_VER_MAJOR_VERSION			GENMASK(31,
>>> 24)
>>>>> +
>>>>>   #define EXYNOS850_DRD_LINKCTRL			0x04
>>>>>   #define LINKCTRL_FORCE_RXELECIDLE		BIT(18)
>>>>>   #define LINKCTRL_FORCE_PHYSTATUS		BIT(17)
>>>>> @@ -1772,6 +1775,10 @@ static const char * const
>>> exynos5_regulator_names[] = {
>>>>>   	"vbus", "vbus-boost",
>>>>>   };
>>>>>
>>>>> +static const char * const exynosautov920_clk_names[] = {
>>>>> +	"ext_xtal",
>>>>> +};
>>>>> +
>>>>>   static const struct exynos5_usbdrd_phy_drvdata exynos5420_usbdrd_phy =
>>> {
>>>>>   	.phy_cfg		= phy_cfg_exynos5,
>>>>>   	.phy_ops		= &exynos5_usbdrd_phy_ops,
>>>>> @@ -1847,6 +1854,81 @@ static const struct exynos5_usbdrd_phy_drvdata
>>> exynos850_usbdrd_phy = {
>>>>>   	.n_regulators		= ARRAY_SIZE(exynos5_regulator_names),
>>>>>   };
>>>>>
>>>>> +static void exynosautov920_usbdrd_utmi_init(struct
>>>>> +exynos5_usbdrd_phy *phy_drd) {
>>>>> +	u32 version;
>>>>> +
>>>>> +	version = readl(phy_drd->reg_phy +
>>> EXYNOSAUTOv920_DRD_CTRL_VER);
>>>>> +	dev_info(phy_drd->dev, "usbphy: version:0x%x\n", version);
>>>>
>>>> Please do not add mode info to boot log, use dev_dbg instead.
>>>
>>> Just drop entirely, not even worth dbg (see coding style, driver development
>>> debugging guide). It is fixed per given compatible, isn't it? If not, there is entire
>>> commit msg to explain unusual things.
>>
>> This SoC has a single USB 3.1 DRD combo v400 phy and three USB2.0 DRD phy v303
> 
> 
> That's a different device, no? Look at the compatible here - it says
> usb31drd.
> 
> What does 31 stand for?
> 
>> controllers those only support the UTMI+ interface. Currently, supporting only 
>> v303 phy in this patch-set, and planning v400 phy later (soon). Same may be 
>> also updated in commit  message. 
>>
>> If there's any issue in phy init, dbg print is needed to debug which phy caused it. 
> No, rethink rather this makes sense at all. Please read carefully
> writing bindings, which will tell you that you cannot have different
> devices under the same compatible. Unless you say these are the same
> devices and it differs by other phy? But this is a phy... so many questions.

Hm, unless you want to say devices are fully compatible, the version is
fully detectable and the driver will make use of that. That would be
fine, but should be expressed in commit msg and actually we should see
the second phy variant already in the patchset.

Best regards,
Krzysztof

RE: [PATCH v2 1/2] dt-bindings: phy: samsung,usb3-drd-phy: add dt-schema for ExynosAutov920

[Pritam Manohar Sutar]

Hi Krzysztof, 

> -----Original Message-----
> From: Krzysztof Kozlowski <krzk@kernel.org>
> Sent: 21 May 2025 02:15 PM
> To: Pritam Manohar Sutar <pritam.sutar@samsung.com>; vkoul@kernel.org;
> kishon@kernel.org; robh@kernel.org; krzk+dt@kernel.org;
> conor+dt@kernel.org; alim.akhtar@samsung.com; andre.draszik@linaro.org;
> peter.griffin@linaro.org; kauschluss@disroot.org;
> m.szyprowski@samsung.com; s.nawrocki@samsung.com
> Cc: linux-phy@lists.infradead.org; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-samsung-
> soc@vger.kernel.org; rosa.pila@samsung.com; dev.tailor@samsung.com;
> faraz.ata@samsung.com; muhammed.ali@samsung.com;
> selvarasu.g@samsung.com
> Subject: Re: [PATCH v2 1/2] dt-bindings: phy: samsung,usb3-drd-phy: add dt-
> schema for ExynosAutov920
> 
> On 21/05/2025 08:48, Pritam Manohar Sutar wrote:
> >>> diff --git
> >>> a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml
> >>> b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml
> >>> index fdddddc7d611..c50f4218ded9 100644
> >>> ---
> >>> a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml
> >>> +++ b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yam
> >>> +++ l
> >>> @@ -32,6 +32,7 @@ properties:
> >>>        - samsung,exynos7-usbdrd-phy
> >>>        - samsung,exynos7870-usbdrd-phy
> >>>        - samsung,exynos850-usbdrd-phy
> >>> +      - samsung,exynosautov920-usb31drd-phy
> >>>
> >>>    clocks:
> >>>      minItems: 2
> >>> @@ -204,6 +205,32 @@ allOf:
> >>>          reg-names:
> >>>            maxItems: 1
> >>>
> >>> +  - if:
> >>> +      properties:
> >>> +        compatible:
> >>> +          contains:
> >>> +            const: samsung,exynosautov920-usb31drd-phy
> >>> +    then:
> >>> +      $ref: /schemas/usb/usb-switch.yaml#
> >>> +
> >>> +      properties:
> >>> +        clocks:
> >>> +          items:
> >>
> >> Why there is no main PHY clock?
> >
> > external crystal clk (ext_xtal) is used as main phy clk.
> 
> So this is the main phy clock? This describes the clock input, not what you have
> on your board. If you change external crystal to internal clock in one design, you
> change the binding? No, this makes no sense.
> 
> 

Yes, this is the main phy clock. Will revisit the binding and try reusing existing one.

> 
> Best regards,
> Krzysztof

Thank you,
Pritam

Re: [PATCH v2 2/2] phy: exyons5-usbdrd: support HS phy for ExynosAutov920

['Neil Armstrong']

On 21/05/2025 08:56, Pritam Manohar Sutar wrote:
> Hi Neil,
> 
> Thank you for reviewing the patches.
> 
>> -----Original Message-----
>> From: neil.armstrong@linaro.org <neil.armstrong@linaro.org>
>> Sent: 20 May 2025 01:10 PM
>> To: Pritam Manohar Sutar <pritam.sutar@samsung.com>; vkoul@kernel.org;
>> kishon@kernel.org; robh@kernel.org; krzk+dt@kernel.org;
>> conor+dt@kernel.org; alim.akhtar@samsung.com; andre.draszik@linaro.org;
>> peter.griffin@linaro.org; kauschluss@disroot.org;
>> m.szyprowski@samsung.com; s.nawrocki@samsung.com
>> Cc: linux-phy@lists.infradead.org; devicetree@vger.kernel.org; linux-
>> kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-samsung-
>> soc@vger.kernel.org; rosa.pila@samsung.com; dev.tailor@samsung.com;
>> faraz.ata@samsung.com; muhammed.ali@samsung.com;
>> selvarasu.g@samsung.com
>> Subject: Re: [PATCH v2 2/2] phy: exyons5-usbdrd: support HS phy for
>> ExynosAutov920
>>
>> On 16/05/2025 12:26, Pritam Manohar Sutar wrote:
>>> This SoC has a single USB 3.1 DRD combo phy and three USB2.0 DRD HS
>>> phy controllers those only support the UTMI+ interface.
>>>
>>> Support only UTMI+ for this SoC which is very similar to what the
>>> existing Exynos850 supports.
>>>
>>> The combo phy supports both UTMI+ (HS) and PIPE3 (SS) and is out of
>>> scope of this commit.
>>>
>>> Add required change in phy driver to support HS phy for this SoC.
>>>
>>> Signed-off-by: Pritam Manohar Sutar <pritam.sutar@samsung.com>
>>> ---
>>>    drivers/phy/samsung/phy-exynos5-usbdrd.c | 85
>> ++++++++++++++++++++++++
>>>    1 file changed, 85 insertions(+)
>>>
>>> diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c
>>> b/drivers/phy/samsung/phy-exynos5-usbdrd.c
>>> index 634c4310c660..b440b56c6595 100644
>>> --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c
>>> +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c
>>> @@ -177,6 +177,9 @@
>>>    #define HSPHYPLLTUNE_PLL_P_TUNE			GENMASK(3, 0)
>>>
>>>    /* Exynos850: USB DRD PHY registers */
>>> +#define EXYNOSAUTOv920_DRD_CTRL_VER		0x00
>>> +#define CTRL_VER_MAJOR_VERSION			GENMASK(31, 24)
>>> +
>>>    #define EXYNOS850_DRD_LINKCTRL			0x04
>>>    #define LINKCTRL_FORCE_RXELECIDLE		BIT(18)
>>>    #define LINKCTRL_FORCE_PHYSTATUS		BIT(17)
>>> @@ -1772,6 +1775,10 @@ static const char * const
>> exynos5_regulator_names[] = {
>>>    	"vbus", "vbus-boost",
>>>    };
>>>
>>> +static const char * const exynosautov920_clk_names[] = {
>>> +	"ext_xtal",
>>> +};
>>> +
>>>    static const struct exynos5_usbdrd_phy_drvdata exynos5420_usbdrd_phy = {
>>>    	.phy_cfg		= phy_cfg_exynos5,
>>>    	.phy_ops		= &exynos5_usbdrd_phy_ops,
>>> @@ -1847,6 +1854,81 @@ static const struct exynos5_usbdrd_phy_drvdata
>> exynos850_usbdrd_phy = {
>>>    	.n_regulators		= ARRAY_SIZE(exynos5_regulator_names),
>>>    };
>>>
>>> +static void exynosautov920_usbdrd_utmi_init(struct exynos5_usbdrd_phy
>>> +*phy_drd) {
>>> +	u32 version;
>>> +
>>> +	version = readl(phy_drd->reg_phy +
>> EXYNOSAUTOv920_DRD_CTRL_VER);
>>> +	dev_info(phy_drd->dev, "usbphy: version:0x%x\n", version);
>>
>> Please do not add mode info to boot log, use dev_dbg instead.
> 
> Will replace dev_info by dev_dbg.
> 
>>
>>> +
>>> +	if (FIELD_GET(CTRL_VER_MAJOR_VERSION, version) == 0x3)
>>> +		/* utmi init for exynosautov920 HS phy */
>>> +		exynos850_usbdrd_utmi_init(phy_drd);
>>> +}
>>> +
>>> +static int exynosautov920_usbdrd_phy_init(struct phy *phy) {
>>> +	struct phy_usb_instance *inst = phy_get_drvdata(phy);
>>> +	struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
>>> +	int ret = 0;
>>> +
>>> +	ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd-
>>> clks);
>>> +	if (ret)
>>> +		return ret;
>>> +
>>> +	/* UTMI or PIPE3 specific init */
>>> +	inst->phy_cfg->phy_init(phy_drd);
>>> +
>>> +	clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks,
>>> +phy_drd->clks);
>>> +
>>> +	return 0;
>>> +}
>>> +
>>> +static void exynosautov920_v3p1_phy_dis(struct phy *phy) {
>>> +	struct phy_usb_instance *inst = phy_get_drvdata(phy);
>>> +	struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
>>> +	void __iomem *reg_phy = phy_drd->reg_phy;
>>> +	u32 version;
>>> +
>>> +	version = readl(reg_phy + EXYNOSAUTOv920_DRD_CTRL_VER);
>>> +
>>> +	if (FIELD_GET(CTRL_VER_MAJOR_VERSION, version) == 0x3)
>>> +		exynos850_usbdrd_phy_exit(phy);
>>> +}
>>> +
>>> +static int exynosautov920_usbdrd_phy_exit(struct phy *phy) {
>>> +	struct phy_usb_instance *inst = phy_get_drvdata(phy);
>>> +
>>> +	if (inst->phy_cfg->id == EXYNOS5_DRDPHY_UTMI)
>>> +		exynosautov920_v3p1_phy_dis(phy);
>>> +
>>> +	return 0;
>>> +}
>>> +
>>> +static const struct phy_ops exynosautov920_usbdrd_phy_ops = {
>>> +	.init		= exynosautov920_usbdrd_phy_init,
>>> +	.exit		= exynosautov920_usbdrd_phy_exit,
>>
>> <snip>
>>
>>> +		.id		= EXYNOS5_DRDPHY_UTMI,
>>> +		.phy_init	= exynosautov920_usbdrd_utmi_init,
>>
>> <snip>
>>
>>> +	}, {
>>> +		.compatible = "samsung,exynosautov920-usb31drd-phy",
>>> +		.data = &exynosautov920_usb31drd_phy
>>
>> All those new ops are only called when matching this compatible, it it really
>> necessary to check the version ? is there "samsung,exynosautov920-usb31drd-
>> phy" PHYs with version different from 3 in the wild ?
>>
> 
> This SoC has a single USB 3.1 DRD combo phy of version v400 (major : minor versions) and three USB2.0
> DRD phy v303 (major : minor versions) controllers those only support the UTMI+ interface. Currently,
> supporting only v303 phys in this patch-set, and planning v400 phy later (soon).
> 
> Yes, there's v400 phy version that is different from v303 phy. Hence, phy version check is needed to support both the phys for same compatible.

OK so add 2 compatibles, one for the usb31drd and one for the usb2drd since those are 2 difference hardware.

Neil

> 
>> Neil
>>
>>>    	},
>>>    	{ },
>>>    };
> 
> 
> Thank you,
> Pritam
> 

Re: [PATCH v2 2/2] phy: exyons5-usbdrd: support HS phy for ExynosAutov920

[Krzysztof Kozlowski]

On 21/05/2025 14:56, 'Neil Armstrong' wrote:
>>> <snip>
>>>
>>>> +	}, {
>>>> +		.compatible = "samsung,exynosautov920-usb31drd-phy",
>>>> +		.data = &exynosautov920_usb31drd_phy
>>>
>>> All those new ops are only called when matching this compatible, it it really
>>> necessary to check the version ? is there "samsung,exynosautov920-usb31drd-
>>> phy" PHYs with version different from 3 in the wild ?
>>>
>>
>> This SoC has a single USB 3.1 DRD combo phy of version v400 (major : minor versions) and three USB2.0
>> DRD phy v303 (major : minor versions) controllers those only support the UTMI+ interface. Currently,
>> supporting only v303 phys in this patch-set, and planning v400 phy later (soon).
>>
>> Yes, there's v400 phy version that is different from v303 phy. Hence, phy version check is needed to support both the phys for same compatible.
> 
> OK so add 2 compatibles, one for the usb31drd and one for the usb2drd since those are 2 difference hardware.

...unless this is fully detectable hardware, then use fallbacks and only
one compatible in the driver.

Best regards,
Krzysztof

Re: [PATCH v2 2/2] phy: exyons5-usbdrd: support HS phy for ExynosAutov920

[Neil Armstrong]

On 21/05/2025 14:58, Krzysztof Kozlowski wrote:
> On 21/05/2025 14:56, 'Neil Armstrong' wrote:
>>>> <snip>
>>>>
>>>>> +	}, {
>>>>> +		.compatible = "samsung,exynosautov920-usb31drd-phy",
>>>>> +		.data = &exynosautov920_usb31drd_phy
>>>>
>>>> All those new ops are only called when matching this compatible, it it really
>>>> necessary to check the version ? is there "samsung,exynosautov920-usb31drd-
>>>> phy" PHYs with version different from 3 in the wild ?
>>>>
>>>
>>> This SoC has a single USB 3.1 DRD combo phy of version v400 (major : minor versions) and three USB2.0
>>> DRD phy v303 (major : minor versions) controllers those only support the UTMI+ interface. Currently,
>>> supporting only v303 phys in this patch-set, and planning v400 phy later (soon).
>>>
>>> Yes, there's v400 phy version that is different from v303 phy. Hence, phy version check is needed to support both the phys for same compatible.
>>
>> OK so add 2 compatibles, one for the usb31drd and one for the usb2drd since those are 2 difference hardware.
> 
> ...unless this is fully detectable hardware, then use fallbacks and only
> one compatible in the driver.

But use proper compatible like "samsung,exynosautov92-usb-phy", but still those are
2 very different PHYs connected to different HW blocks, I won't mix USB3.1 and USB2 PHY
compatibles.

Neil

> 
> Best regards,
> Krzysztof