From: Dave Hansen <dave.hansen@intel.com>
To: "Chang S. Bae" <chang.seok.bae@intel.com>, x86@kernel.org
Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de,
dave.hansen@linux.intel.com, colinmitchell@google.com,
chao.gao@intel.com, abusse@amazon.de,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v4 4/6] x86/microcode/intel: Implement staging handler
Date: Wed, 13 Aug 2025 11:44:11 -0700 [thread overview]
Message-ID: <002f259d-2f20-4428-add3-a02650bc728b@intel.com> (raw)
In-Reply-To: <20250813172649.15474-5-chang.seok.bae@intel.com>
> +/*
> + * Determine if the next data chunk can be sent. Each chunk is typically
> + * one page unless the remaining data is smaller. If the total
> + * transmitted data exceeds the defined limit, a timeout occurs.
> + */
This comment isn't really telling the whole story. It's not just
determining if the chunk can be sent, it's calculating it and filling it in.
> +static bool can_send_next_chunk(struct staging_state *ss)
> +{
> + WARN_ON_ONCE(ss->ucode_len < ss->offset);
Please don't WARN_ON() they can be fatal because of panic_on_warn. Also
I think this is the wrong spot for this. We should enforce this at the
time ss->offset is _established_ which is oddly enough in the next patch.
ss->offset = read_mbox_dword(ss->mmio_base);
if (ss->offset > ss->ucode_len)
// error out
> + ss->chunk_size = min(MBOX_XACTION_SIZE, ss->ucode_len - ss->offset);
It's a _little_ non-obvious that "can_send_next_chunk()" is also setting
->chunk_size. It would be easier to grok if it was something like:
ok = calc_next_chunk_size(&ss);
if (!ok)
// error out
> + if (ss->bytes_sent + ss->chunk_size > MBOX_XACTION_MAX(ss->ucode_len)) {
> + ss->state = UCODE_TIMEOUT;
> + return false;
> + }
"TIMEOUT" seems like an odd thing to call this failure. Can you explain
the choice of this error code a bit, please?
> +/*
> + * Handle the staging process using the mailbox MMIO interface. The
> + * microcode image is transferred in chunks until completion. Return the
> + * result state.
> */
> static enum ucode_state do_stage(u64 mmio_pa)
> {
> - pr_debug_once("Staging implementation is pending.\n");
> - return UCODE_ERROR;
> + struct staging_state ss = {};
> +
> + ss.mmio_base = ioremap(mmio_pa, MBOX_REG_NUM * MBOX_REG_SIZE);
> + if (WARN_ON_ONCE(!ss.mmio_base))
> + return UCODE_ERROR;
> +
> + init_stage(&ss);
> +
> + /* Perform the staging process while within the retry limit */
> + while (!is_stage_complete(ss.offset) && can_send_next_chunk(&ss)) {
> + /* Send a chunk of microcode each time: */
> + if (!send_data_chunk(&ss))
> + break;
> + /*
> + * Then, ask the hardware which piece of the image it
> + * needs next. The same piece may be sent more than once.
> + */
> + if (!fetch_next_offset(&ss))
> + break;
> + }
The return types here are a _bit_ wonky. The 'bool' returns make sense
for things like is_stage_complete(). But they don't look right for:
if (!send_data_chunk(&ss))
break;
where we'd typically use an -ERRNO and where 0 mean success. It would
look something like this:
while (!staging_is_complete(&ss)) {
err = send_data_chunk(&ss);
if (err)
break;
err = fetch_next_offset(&ss);
if (err)
break;
}
That's utterly unambiguous about the intent and what types the send and
fetch function _must_ have.
Note I also moved the can_send_next_chunk() call into
staging_is_complete(). I think that makes sense as well for the
top-level loop.
next prev parent reply other threads:[~2025-08-13 18:44 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-20 23:40 [PATCH v2 0/6] x86: Support for Intel Microcode Staging Feature Chang S. Bae
2025-03-20 23:40 ` [PATCH v2 1/6] x86/microcode: Introduce staging step to reduce late-loading time Chang S. Bae
2025-03-20 23:40 ` [PATCH v2 2/6] x86/microcode/intel: Define staging state struct Chang S. Bae
2025-03-20 23:40 ` [PATCH v2 3/6] x86/microcode/intel: Establish staging control logic Chang S. Bae
2025-03-21 21:18 ` [PATCH v2a " Chang S. Bae
2025-03-26 7:35 ` Chao Gao
2025-03-26 18:43 ` Chang S. Bae
2025-03-27 1:44 ` Chao Gao
2025-03-28 14:12 ` Chang S. Bae
2025-03-20 23:40 ` [PATCH v2 4/6] x86/microcode/intel: Implement staging handler Chang S. Bae
2025-03-21 0:15 ` Dave Hansen
2025-03-21 21:19 ` [PATCH v2a " Chang S. Bae
2025-03-26 8:34 ` Chao Gao
2025-03-26 18:43 ` Chang S. Bae
2025-03-21 21:19 ` [PATCH v2 " Chang S. Bae
2025-03-20 23:40 ` [PATCH v2 5/6] x86/microcode/intel: Support mailbox transfer Chang S. Bae
2025-03-21 21:19 ` [PATCH v2a " Chang S. Bae
2025-03-27 3:32 ` [PATCH v2 " Chao Gao
2025-03-27 14:11 ` Chang S. Bae
2025-03-31 19:16 ` Dave Hansen
2025-03-20 23:40 ` [PATCH v2 6/6] x86/microcode/intel: Enable staging when available Chang S. Bae
2025-04-09 23:27 ` [PATCH v3 0/6] x86: Support for Intel Microcode Staging Feature Chang S. Bae
2025-04-09 23:27 ` [PATCH v3 1/6] x86/microcode: Introduce staging step to reduce late-loading time Chang S. Bae
2025-04-09 23:27 ` [PATCH v3 2/6] x86/microcode/intel: Establish staging control logic Chang S. Bae
2025-04-09 23:27 ` [PATCH v3 3/6] x86/microcode/intel: Define staging state struct Chang S. Bae
2025-04-09 23:27 ` [PATCH v3 4/6] x86/microcode/intel: Implement staging handler Chang S. Bae
2025-04-09 23:27 ` [PATCH v3 5/6] x86/microcode/intel: Support mailbox transfer Chang S. Bae
2025-04-16 14:14 ` Chao Gao
2025-04-16 17:22 ` Chang S. Bae
2025-04-16 17:37 ` Dave Hansen
2025-04-09 23:27 ` [PATCH v3 6/6] x86/microcode/intel: Enable staging when available Chang S. Bae
2025-08-13 17:26 ` [PATCH v4 0/6] x86: Support for Intel Microcode Staging Feature Chang S. Bae
2025-08-13 17:26 ` [PATCH v4 1/6] x86/microcode: Introduce staging step to reduce late-loading time Chang S. Bae
2025-08-18 7:45 ` Chao Gao
2025-08-13 17:26 ` [PATCH v4 2/6] x86/microcode/intel: Establish staging control logic Chang S. Bae
2025-08-13 18:21 ` Dave Hansen
2025-08-13 20:46 ` Chang S. Bae
2025-08-13 20:55 ` Dave Hansen
2025-08-14 18:30 ` Chang S. Bae
2025-08-22 22:39 ` [PATCH] x86/cpu/topology: Make primary thread mask available with SMP=n Chang S. Bae
2025-08-23 16:05 ` Chang S. Bae
2025-08-22 22:39 ` [PATCH v4a 2/6] x86/microcode/intel: Establish staging control logic Chang S. Bae
2025-08-22 23:34 ` Dave Hansen
2025-08-13 17:26 ` [PATCH v4 3/6] x86/microcode/intel: Define staging state struct Chang S. Bae
2025-08-13 18:25 ` Dave Hansen
2025-08-22 22:39 ` [PATCH v4a " Chang S. Bae
2025-08-13 17:26 ` [PATCH v4 4/6] x86/microcode/intel: Implement staging handler Chang S. Bae
2025-08-13 18:44 ` Dave Hansen [this message]
2025-08-22 22:39 ` [PATCH v4a " Chang S. Bae
2025-08-13 17:26 ` [PATCH v4 5/6] x86/microcode/intel: Support mailbox transfer Chang S. Bae
2025-08-13 19:07 ` Dave Hansen
2025-08-22 22:40 ` [PATCH v4a " Chang S. Bae
2025-08-13 17:26 ` [PATCH v4 6/6] x86/microcode/intel: Enable staging when available Chang S. Bae
2025-08-18 8:35 ` Chao Gao
2025-08-22 22:42 ` Chang S. Bae
2025-08-13 19:08 ` [PATCH v4 0/6] x86: Support for Intel Microcode Staging Feature Dave Hansen
2025-08-23 15:52 ` [PATCH v5 0/7] " Chang S. Bae
2025-08-23 15:52 ` [PATCH v5 1/7] x86/cpu/topology: Make primary thread mask available with SMP=n Chang S. Bae
2025-08-23 15:52 ` [PATCH v5 2/7] x86/microcode: Introduce staging step to reduce late-loading time Chang S. Bae
2025-08-23 15:52 ` [PATCH v5 3/7] x86/microcode/intel: Establish staging control logic Chang S. Bae
2025-08-23 15:52 ` [PATCH v5 4/7] x86/microcode/intel: Define staging state struct Chang S. Bae
2025-08-23 15:52 ` [PATCH v5 5/7] x86/microcode/intel: Implement staging handler Chang S. Bae
2025-08-23 15:52 ` [PATCH v5 6/7] x86/microcode/intel: Support mailbox transfer Chang S. Bae
2025-08-23 15:52 ` [PATCH v5 7/7] x86/microcode/intel: Enable staging when available Chang S. Bae
2025-08-26 22:13 ` [PATCH v5 0/7] x86: Support for Intel Microcode Staging Feature Luck, Tony
2025-08-26 22:15 ` Chang S. Bae
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