From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752522AbeDKAB3 (ORCPT ); Tue, 10 Apr 2018 20:01:29 -0400 Received: from mail-qk0-f193.google.com ([209.85.220.193]:46081 "EHLO mail-qk0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752408AbeDKABY (ORCPT ); Tue, 10 Apr 2018 20:01:24 -0400 X-Google-Smtp-Source: AIpwx4/t25Ie8jtOWQk6sxCm9kVr3D608eEAyx0vFN39+LuWqxBEEx0JwSl3vo4vcYr6mYT3kGXFIg== From: "Jingoo Han" To: "'Gustavo Pimentel'" , , , , , , Cc: , , References: <5181f7ffbb9d2889974c49d84e72042251adf8b6.1523266508.git.gustavo.pimentel@synopsys.com> In-Reply-To: <5181f7ffbb9d2889974c49d84e72042251adf8b6.1523266508.git.gustavo.pimentel@synopsys.com> Subject: Re: [PATCH v2 8/9] PCI: dwc: Small computation improvement Date: Tue, 10 Apr 2018 20:01:21 -0400 Message-ID: <003001d3d128$39f3eaa0$addbbfe0$@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit X-Mailer: Microsoft Outlook 16.0 Content-Language: en-us Thread-Index: AQEaRjwvEF5/h3QMrbPVq+Y0x5xNJwIXxkZLpV0FZyA= Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Monday, April 9, 2018 5:41 AM, Gustavo Pimentel wrote: > > Replaces a simple division by 2 to a right shift rotation of 1 bit. It looks good. However, would you add a simple reason to the commit message? Best regards, Jingoo Han > > Signed-off-by: Gustavo Pimentel > --- > Change v1->v2: > - Nothing changed, just to follow the patch set version. > > drivers/pci/dwc/pcie-designware-host.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/pci/dwc/pcie-designware-host.c > b/drivers/pci/dwc/pcie-designware-host.c > index 03e9b82..8e6fed4 100644 > --- a/drivers/pci/dwc/pcie-designware-host.c > +++ b/drivers/pci/dwc/pcie-designware-host.c > @@ -332,8 +332,8 @@ int dw_pcie_host_init(struct pcie_port *pp) > > cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, > "config"); > if (cfg_res) { > - pp->cfg0_size = resource_size(cfg_res) / 2; > - pp->cfg1_size = resource_size(cfg_res) / 2; > + pp->cfg0_size = resource_size(cfg_res) >> 1; > + pp->cfg1_size = resource_size(cfg_res) >> 1; > pp->cfg0_base = cfg_res->start; > pp->cfg1_base = cfg_res->start + pp->cfg0_size; > } else if (!pp->va_cfg0_base) { > @@ -377,8 +377,8 @@ int dw_pcie_host_init(struct pcie_port *pp) > break; > case 0: > pp->cfg = win->res; > - pp->cfg0_size = resource_size(pp->cfg) / 2; > - pp->cfg1_size = resource_size(pp->cfg) / 2; > + pp->cfg0_size = resource_size(pp->cfg) >> 1; > + pp->cfg1_size = resource_size(pp->cfg) >> 1; > pp->cfg0_base = pp->cfg->start; > pp->cfg1_base = pp->cfg->start + pp->cfg0_size; > break; > -- > 2.7.4 >