Re: [patch] Re: alpha - generic_init_pit - why using RTC for calibration?

Oleg I. Vdovikin
2001-07-05T08:37:58Z

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That's it.

Please also include my old rtc patch for 2.2.x series into official 2.2.20
kernel.

Thanks,
Oleg.

-------------
From: "Jeff Garzik" <jgarzik@mandrakesoft.com>
Subject: Re: [patch] Re: alpha - generic_init_pit - why using RTC for
calibration?

> Oleg,
>
> The official kernel now carries Richard's version. Can you post a diff
> on linux-kernel against version 2.4.7-pre2 perhaps, which cleans up
> Richard's code to yours?
> --
> Jeff Garzik | Thalidomide, eh?
> Building 1024 | So you're saying the eggplant has an accomplice?
> MandrakeSoft |
>

[-- Attachment #2: linux-2.2.x.rtc.patch --]
[-- Type: application/octet-stream, Size: 1972 bytes --]

--- linux/arch/alpha/kernel/time.c.orig Mon Jul 2 14:05:09 2001
+++ linux/arch/alpha/kernel/time.c Mon Jul 2 15:47:45 2001
@@ -231,6 +231,49 @@
outb(0x13, 0x42);
}

+/*
+ * Calibrate CPU clock using legacy 8254 timer/counter. Stolen from
+ * arch/i386/time.c.
+ */
+
+#define CALIBRATE_DIVISOR 0xffff
+
+static unsigned long __init
+calibrate_cc(void)
+{
+ unsigned int cc;
+ unsigned long count = 0;
+
+ /* Set the Gate high, disable speaker */
+ outb((inb(0x61) & ~0x02) | 0x01, 0x61);
+
+ /*
+ * Now let's take care of CTC channel 2
+ *
+ * Set the Gate high, program CTC channel 2 for mode 0,
+ * (interrupt on terminal count mode), binary count,
+ * load maximum divisor we can get for accuracy - 65535
+ */
+
+ outb(0xb0, 0x43); /* binary, mode 0, LSB/MSB, Ch 2 */
+ outb(CALIBRATE_DIVISOR & 0xff, 0x42); /* LSB of count */
+ outb(CALIBRATE_DIVISOR >> 8, 0x42); /* MSB of count */
+
+ /* we still should not hang if timer not runing or N/A */
+ for (cc = rpcc(); (inb(0x61) & 0x20) == 0 && !(count >> 32); count++);
+
+ /* cycles delta */
+ cc = rpcc() - cc;
+
+ /* check for the reliable result */
+ if ((count < 1) || (count >> 32))
+ return 0;
+
+ /* and the final result in HZ */
+ return ((unsigned long)cc * CLOCK_TICK_RATE) / CALIBRATE_DIVISOR;
+}
+
+
void
time_init(void)
{
@@ -239,6 +282,10 @@
unsigned long cycle_freq, ppm_error;
long diff;

+ /* Calibrate CPU clock using CTC. If this fails, use RTC. */
+ if (!est_cycle_freq)
+ est_cycle_freq = calibrate_cc();
+
/*
* The Linux interpretation of the CMOS clock register contents:
* When the Update-In-Progress (UIP) flag goes from 1 to 0, the
@@ -275,7 +322,7 @@
if (diff < 0)
diff = -diff;
ppm_error = (diff * 1000000L) / cycle_freq;
-#if 0
+#if 1
printk("Alpha clock init: HWRPB %lu, Measured %lu, error=%lu ppm.\n",
hwrpb->cycle_freq, est_cycle_freq, ppm_error);
#endif

[-- Attachment #3: linux-2.4.7pre2.rtc.patch --]
[-- Type: application/octet-stream, Size: 1905 bytes --]

--- arch/alpha/kernel/time.c.orig Thu Jul 5 12:18:48 2001
+++ arch/alpha/kernel/time.c Thu Jul 5 12:24:11 2001
@@ -174,13 +174,12 @@
* arch/i386/time.c.
*/

-#define CALIBRATE_LATCH (52 * LATCH)
-#define CALIBRATE_TIME (52 * 1000020 / HZ)
+#define CALIBRATE_LATCH 0xffff

static unsigned long __init
calibrate_cc_with_pic(void)
{
- int cc;
+ unsigned int cc;
unsigned long count = 0;

/* Set the Gate high, disable speaker */
@@ -191,39 +190,24 @@
*
* Set the Gate high, program CTC channel 2 for mode 0,
* (interrupt on terminal count mode), binary count,
- * load 5 * LATCH count, (LSB and MSB) to begin countdown.
+ * load maximum divisor we can get for accuracy - 65535
*/
outb(0xb0, 0x43); /* binary, mode 0, LSB/MSB, Ch 2 */
outb(CALIBRATE_LATCH & 0xff, 0x42); /* LSB of count */
outb(CALIBRATE_LATCH >> 8, 0x42); /* MSB of count */
-
- cc = rpcc();
- do {
- count++;
- } while ((inb(0x61) & 0x20) == 0);
+
+ /* we still should not hang if timer not runing or N/A */
+ for (cc = rpcc(); (inb(0x61) & 0x20) == 0 && !(count >> 32); count++);
+
+ /* cycles delta */
cc = rpcc() - cc;
-
- /* Error: ECTCNEVERSET */
- if (count <= 1)
- goto bad_ctc;
-
- /* Error: ECPUTOOFAST */
- if (count >> 32)
- goto bad_ctc;
-
- /* Error: ECPUTOOSLOW */
- if (cc <= CALIBRATE_TIME)
- goto bad_ctc;
-
- return ((long)cc * 1000000) / CALIBRATE_TIME;
-
- /*
- * The CTC wasn't reliable: we got a hit on the very first read,
- * or the CPU was so fast/slow that the quotient wouldn't fit in
- * 32 bits..
- */
- bad_ctc:
- return 0;
+
+ /* check for the reliable result */
+ if ((count < 1) || (count >> 32))
+ return 0;
+
+ /* and the final result in HZ */
+ return ((unsigned long)cc * CLOCK_TICK_RATE) / CALIBRATE_LATCH;
}

/* The Linux interpretation of the CMOS clock register contents: