From: "Kevin D. Kissell" <kevink@mips.com>
To: "Sunil Naidu" <akula2.shark@gmail.com>,
"Ralf Baechle" <ralf@linux-mips.org>
Cc: <linux-kernel@vger.kernel.org>,
"sathesh babu" <sathesh_edara2003@yahoo.co.in>,
<linux-mips@linux-mips.org>
Subject: Re: Running Linux on FPGA
Date: Sun, 21 Jan 2007 12:22:20 +0100 [thread overview]
Message-ID: <005101c73d4e$6bbf96d0$10eca8c0@grendel> (raw)
In-Reply-To: 8355959a0701210159k2fcb2323s2d38f91a41fcb942@mail.gmail.com
> > The overhead of timer interrupts at this low clockrate is significant
> > so I recommend to minimize the timer interrupt rate as far as possible.
> > This is really a tradeoff between latency and overhead and matters
> > much less on hardcores which run at hundreds of MHz. For power sensitive
> > applications lowering the interrupt rate can also help. And that's alredy
> > pretty much what you need to know, that is a 10ms timer is fine.
> >
>
> I have worked with FPGA Linux system which is reconfigurable
> on-the-fly by the 200Mhz ARM9 CPU running Debian Linux, Altera Cyclone
> II FPGA is included on my TS-7300 board. Advantage is, Altera FPGA and
> a dedicated high-speed bus between the CPU and FPGA provides a good
> design scope to provide many solutions.
What's your point here? A 200MHz hard ore won't see the issues
under discussion. We're talking about systems where the CPU itself
is "soft" and implemented in an FPGA.
Regards,
Kevin K.
next prev parent reply other threads:[~2007-01-21 11:34 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20070120234237.49126.qmail@web7912.mail.in.yahoo.com>
2007-01-21 0:14 ` Running Linux on FPGA Ralf Baechle
2007-01-21 9:59 ` Sunil Naidu
2007-01-21 11:22 ` Kevin D. Kissell [this message]
2007-01-21 21:31 ` Jan Engelhardt
2007-01-22 16:58 ` Kevin D. Kissell
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