e100 patch for kernel 2.2.18

["Thomas Jarosch" <thomas.jarosch@styletec.de>]

[-- Attachment #1: Type: text/plain, Size: 200 bytes --]

Hi,

I've seen the e100 udelay/compile problem twice and now I think,
I should release my patch.

I've already send it to Intel but the are not responding.

Please CC: any comments.

cheers, Thomas.


[-- Attachment #2: e100-type.patch --]
[-- Type: application/octet-stream, Size: 408 bytes --]

diff -r -u e100-1.3.14.orig/src/e100.h e100-1.3.14/src/e100.h
--- e100-1.3.14.orig/src/e100.h	Tue Sep 26 17:15:05 2000
+++ e100-1.3.14/src/e100.h	Fri Nov 24 19:33:09 2000
@@ -254,7 +254,7 @@
 #include <linux/slab.h>
 #include <asm/io.h>
 
-typedef unsigned long dma_addr_t;
+// typedef unsigned long dma_addr_t;
 
 extern inline void *pci_alloc_consistent (struct pci_dev *dev,
     size_t size,

[-- Attachment #3: e100-mdelay.patch --]
[-- Type: application/octet-stream, Size: 5247 bytes --]

diff -r -u e100-1.3.20/src/e100.c e100-1.3.20.working/src/e100.c
--- e100-1.3.20/src/e100.c	Wed Nov  1 15:32:53 2000
+++ e100-1.3.20.working/src/e100.c	Sat Dec  9 10:04:46 2000
@@ -1423,7 +1423,7 @@
 	e100_retry = E100_CMD_WAIT;
 	while (((bddp->scbp->scb_status & SCB_CUS_MASK) == SCB_CUS_ACTIVE)
             && (e100_retry)) {
-	    udelay(mstous(20));
+	    mdelay(20);
 	    e100_retry--;
 	}
     }
@@ -1683,7 +1683,7 @@
 	    printk(KERN_WARNING "e100[%d]: Did not load ucode\n", bdp->bd_number);
 	} else {
 	    bddp->ucode_loaded = 1;
-	    drv_usecwait(mstous(1000));   /* 1 sec wait */
+	    mdelay(1000);
 	}
     }
 
@@ -3182,7 +3182,7 @@
     bddp->scbp->scb_port = SelfTestCommandCode;
 
     /* Wait 5 milliseconds for the self-test to complete */
-    drv_usecwait(mstous(50));
+    mdelay(5);
 
     /* if The First Self Test DWORD Still Zero, We've timed out. * If the
      * second DWORD is not zero then we have an error. */
@@ -3451,7 +3451,7 @@
 	e100_retry = E100_CMD_WAIT;
 	while (((bddp->scbp->scb_status & SCB_CUS_MASK) == SCB_CUS_ACTIVE)
             && (e100_retry)) {
-	    drv_usecwait(mstous(20));
+	    mdelay(20);
 	    e100_retry--;
 	}
     }
@@ -3531,7 +3531,7 @@
 	i = 0;
 	while (((bddp->scbp->scb_status & SCB_CUS_MASK) == SCB_CUS_ACTIVE)
             && (i < 5)) {
-	    drv_usecwait(mstous(20));
+	    mdelay(20);
 	    i++;
 	}
     }
@@ -3688,7 +3688,7 @@
     e100_retry = E100_CMD_WAIT;
     while (((uint16_t) bddp->pstats_counters->cmd_complete != 0xA007)
 	&& (e100_retry)) {
-	drv_usecwait(mstous(20));
+	mdelay(20);
 	e100_retry--;
     }
 
@@ -3730,7 +3730,7 @@
 
     while (((bddp->scbp->scb_status & SCB_CUS_MASK) == SCB_CUS_ACTIVE)
 	&& (retry)) {
-	drv_usecwait(mstous(20));
+	mdelay(20);
 	retry--;
     }
     if (!retry) {
@@ -3887,7 +3887,7 @@
 
     /* Wait 100ms for some status */
     for (delay = 0; delay < 100; delay++) {
-	drv_usecwait(mstous(1));
+	mdelay (1);
 
 	/* need to check the pmc_buff status in case it's from the *
 	 *    set_multicast cmd */
@@ -3964,7 +3964,7 @@
     bddp->scbp->scb_port = reset_cmd;
 
     /* wait 5 milliseconds for the reset to take effect */
-    drv_usecwait(mstous(5));
+    mdelay(5);
 
     /* Mask off our interrupt line -- its unmasked after reset */
     e100_dis_intr(bdp);
@@ -4097,7 +4097,7 @@
 	i = 0;
 	while (((bddp->scbp->scb_status & SCB_CUS_MASK) == SCB_CUS_ACTIVE)
             && (i < 5)) {
-	    drv_usecwait(mstous(20));
+	    mdelay(20);
 	    i++;
 	}
 	if (i == 5) {
@@ -4894,7 +4894,7 @@
 	    e100_MdiWrite(bdp, MDI_CONTROL_REG, Phy1, MDI_CR_ISOLATE);
 
 	    /* wait 100 milliseconds for the phy to isolate. */
-	    drv_usecwait(mstous(100));
+	    mdelay(100);
 	}
 
 	/* Since this Phy is at address 0, we must enable it.  So clear */
@@ -4902,7 +4902,7 @@
 	e100_MdiWrite(bdp, MDI_CONTROL_REG, 0, MDI_CR_AUTO_SELECT);
 
 	/* wait 100 milliseconds for the phy to be enabled. */
-	drv_usecwait(mstous(100));
+	mdelay(100);
 
 	/* restart the auto-negotion process */
 	e100_MdiWrite(bdp, MDI_CONTROL_REG, 0,
@@ -4917,7 +4917,7 @@
 	    if (MdiStatusReg & MDI_SR_AUTO_NEG_COMPLETE)
 		break;
 
-	    drv_usecwait(mstous(10));
+	    mdelay(10);
 	    ReNegotiateTime--;
 	}
 
@@ -4945,14 +4945,14 @@
 		e100_MdiWrite(bdp, MDI_CONTROL_REG, 0, MDI_CR_ISOLATE);
 
 		/* wait 100 milliseconds for the phy to isolate. */
-		drv_usecwait(mstous(100));
+		mdelay(100);
 
 		/* Now re-enable PHY 1 */
 		e100_MdiWrite(bdp, MDI_CONTROL_REG, Phy1,
 		    MDI_CR_AUTO_SELECT);
 
 		/* wait 100 milliseconds for the phy to be enabled. */
-		drv_usecwait(mstous(100));
+		mdelay(100);
 
 		/* restart the auto-negotion process */
 		e100_MdiWrite(bdp, MDI_CONTROL_REG, bddp->phy_addr,
@@ -5146,7 +5146,7 @@
 
 		    /* if non-zero, wait for 100 ms before reading again */
 		    if (errors) {
-			udelay(mstous(100));
+			mdelay(100);
 			e100_MdiRead(bdp, PHY_82555_EOF_COUNTER, PhyAdd, &errors);
 
 			/* if non-zero again, we disable polarity */
@@ -5217,7 +5217,7 @@
 	for (i = 0; (!(mdi_status_reg & MDI_SR_AUTO_NEG_COMPLETE)) &&
 		 (i < 300); i++) {
 	    /* delay 10 milliseconds */
-	    udelay(TEN_MILLI_SEC);
+	    mdelay (10);
 
 	    /* now re-read the value. Sticky so read twice */
 	    e100_MdiRead(bdp, MDI_STATUS_REG, bddp->phy_addr,
@@ -5491,7 +5491,7 @@
 
     e100_MdiWrite(bdp, MDI_CONTROL_REG, bddp->phy_addr, control);
 
-    drv_usecwait(mstous(2000));
+    mdelay(2000);
 }
 
 
diff -r -u e100-1.3.20/src/e100.h e100-1.3.20.working/src/e100.h
--- e100-1.3.20/src/e100.h	Wed Nov  1 15:32:53 2000
+++ e100-1.3.20.working/src/e100.h	Sat Dec  9 10:04:46 2000
@@ -1367,9 +1367,9 @@
 #define IS_VALID_MULTICAST(x)  ((x)->bytes[0] & 0x1 )
 
 /* Macros for e100_delay */
-#define   mstous(X)   ((X)*1000) /* millisecs to microsecs */
-#define  ONE_MILLI_SEC 1000
-#define  TEN_MILLI_SEC ONE_MILLI_SEC * 10
+// #define   mstous(X)   ((X)*1000) /* millisecs to microsecs */
+// #define  ONE_MILLI_SEC 1000
+// #define  TEN_MILLI_SEC ONE_MILLI_SEC * 10
 
 /* Device ID macros */
 #define get_pci_dev(X)          ((X)&PCI_DEV_NO)