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From: Rahul Tanwar <rtanwar@maxlinear.com>
To: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: "bigeasy@linutronix.de" <bigeasy@linutronix.de>,
	"robh@kernel.org" <robh@kernel.org>,
	"tglx@linutronix.de" <tglx@linutronix.de>,
	"mingo@redhat.com" <mingo@redhat.com>,
	"bp@alien8.de" <bp@alien8.de>, "x86@kernel.org" <x86@kernel.org>,
	"hpa@zytor.com" <hpa@zytor.com>,
	"dave.hansen@linux.intel.com" <dave.hansen@linux.intel.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	linux-lgm-soc <linux-lgm-soc@maxlinear.com>
Subject: Re: [PATCH RESEND 1/1] x86/of: Add support for boot time interrupt mode config
Date: Mon, 14 Nov 2022 10:00:02 +0000	[thread overview]
Message-ID: <00ce811f-2ec8-802d-d032-8ac2c65d06ff@maxlinear.com> (raw)
In-Reply-To: <Y3IOEFTZ1e/7uWJ4@smile.fi.intel.com>


Hi Andy,

Thanks for response.

On 14/11/2022 5:45 pm, Andy Shevchenko wrote:
> This email was sent from outside of MaxLinear.
> 
> 
> On Mon, Nov 14, 2022 at 05:20:06PM +0800, Rahul Tanwar wrote:
>> Presently, init/boot time interrupt delivery mode is enumerated only
>> for ACPI enabled systems by parsing MADT table or for older systems
>> by parsing MP table. But for OF based x86 systems, it is assumed &
>> fixed to legacy PIC mode.
>>
>> Add support for configuration of init time interrupt delivery mode for
>> x86 OF based systems by introducing a new optional boolean property
>> 'intel,no-imcr' for interrupt-controller node of local APIC. This
>> property emulates IMCRP Bit 7 of MP feature info byte 2 of MP
>> floating pointer structure.
>>
>> Defaults to legacy PIC mode if absent. Configures it to virtual wire
>> compatibility mode if present.
> 
> ...
> 
>> +     if (of_property_read_bool(dn, "intel,no-imcr")) {
> 
> I can't find this property in the Documentation/devicetree/bindings.
> 
> Moreover, I prefer to see positive one, something like:
> 
>          intel,virtual-wire-bla-bla-bla
> 
> Please consult with DT people on how properly name it.


Yes, agree. Need to add it in bindings doc after finalizing the property 
name. I chose "intel,no-imcr" to have a direct correlation with the MPS
spec defined data field for the same purpose. It reads below bit in 
mpparse code to detect PIC mode or virtual wire mode.

Bit 7: IMCRP. When the IMCR presence bit is set, the IMCR is present and 
PIC Mode is implemented; otherwise, Virtual Wire Mode is implemented.

Please refer [1]

[1] https://www.manualslib.com/manual/77733/Intel 
Multiprocessor.html?page=40#manual

Regards,
Rahul


> 
>> +             pr_info("    Virtual Wire compatibility mode.\n");
>> +             pic_mode = 0;
>> +     } else {
>> +             pr_info("    IMCR and PIC compatibility mode.\n");
>> +             pic_mode = 1;
>> +     }
> 
> --
> With Best Regards,
> Andy Shevchenko
> 
> 
> 


  reply	other threads:[~2022-11-14 10:05 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-14  9:20 [PATCH RESEND 0/1] x86/of: Fix a bug in x86 arch OF support Rahul Tanwar
2022-11-14  9:20 ` [PATCH RESEND 1/1] x86/of: Add support for boot time interrupt mode config Rahul Tanwar
2022-11-14  9:44   ` Andy Shevchenko
2022-11-14 10:00     ` Rahul Tanwar [this message]
2022-11-14 10:24       ` Andy Shevchenko

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