From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757743Ab3FTMkT (ORCPT ); Thu, 20 Jun 2013 08:40:19 -0400 Received: from mailout1.samsung.com ([203.254.224.24]:59812 "EHLO mailout1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757704Ab3FTMkP (ORCPT ); Thu, 20 Jun 2013 08:40:15 -0400 X-AuditID: cbfee690-b7f6f6d00000740c-9f-51c2f82df227 From: Jingoo Han To: "'Kukjin Kim'" , "'Bjorn Helgaas'" Cc: linux-samsung-soc@vger.kernel.org, linux-pci@vger.kernel.org, devicetree-discuss@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, "'Grant Likely'" , "'Andrew Murray'" , "'Thomas Petazzoni'" , "'Thierry Reding'" , "'Jason Gunthorpe'" , Arnd Bergmann , "'Surendranath Gurivireddy Balla'" , "'Siva Reddy Kallam'" , "'Thomas Abraham'" , "'Tomasz Figa'" , "'Pratyush Anand'" , "'Mohit KUMAR'" , Jingoo Han Subject: [PATCH V8 0/3] PCIe support for Samsung Exynos5440 SoC Date: Thu, 20 Jun 2013 21:40:12 +0900 Message-id: <00da01ce6db3$4ea4f490$ebeeddb0$@samsung.com> MIME-version: 1.0 Content-type: text/plain; charset=us-ascii Content-transfer-encoding: 7bit X-Mailer: Microsoft Outlook 14.0 Thread-index: Ac5ts0qiIBCvLwUpTGeEBwayV0CEtg== Content-language: ko X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrCKsWRmVeSWpSXmKPExsVy+t8zY13dH4cCDSZv4LJo/r+d1eLvpGPs FkuaMixeHtK0ODD7IavFqzMb2SwuL7zEavH9hqlF74KrbBabHl9jtbi8aw6bxdl5x9ksZpzf x2SxceovRov2S8oWK5q2Mlosvric2WL9jNcsFrtXLmGxODZjCaPF0wdNTA6iHmvmrWH0+P1r EqNH35SrbB5PNl1k9FiwqdTjzrU9bB6bl9R7nJ+xkNHj+45eoIItqxg9fr7U8Xj6Yy+zx+dN cgG8UVw2Kak5mWWpRfp2CVwZz5ctYitY2cVY0bzvJFMD483ELkZODgkBE4mnu3pZIGwxiQv3 1rN1MXJxCAksY5RYteU4M0zR1NYbjBCJ6YwSL/+uY4FwfjFKHGn7yQpSxSagJvHly2F2EFtE wF/i2tVWsCJmgTY2ifXPPoIlhAXsJX717mACsVkEVCXurL/PCGLzClhKbLjexwJhC0r8mHwP zGYW0JJYv/M4E4QtL7F5zVuokxQkdpx9zQixTE/i4pep7BA1IhL7XrwDO1VC4AWHxKvbV6GW CUh8m3wIaCgHUEJWYtMBqDmSEgdX3GCZwCg2C8nqWUhWz0KyehaSFQsYWVYxiqYWJBcUJ6UX megVJ+YWl+al6yXn525ihKSYCTsY7x2wPsSYDLR+IrOUaHI+MEXllcQbGpsZWZiamBobmVua kSasJM6r3mIdKCSQnliSmp2aWpBaFF9UmpNafIiRiYNTqoExpruwv6NJp/fYi51WP+4WOfG3 v9U6nChwbP+JVGHdF2c0rCeXcd61iAjhu3w9q7f2EOf3EPff3K/+Ffa7zl0qWGLVr+Q1Y9OM uhvr0kyZEnlPCn36snZhytHbj9fKGj+LWrfnh/CzHBeNnxYqLzJPv3P7uO3rh0uOnEWi6x6f 0L/2VenfwbpdSizFGYmGWsxFxYkAcAnpVUcDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprAJsWRmVeSWpSXmKPExsVy+t9jQV3dH4cCDR6kWjT/385q8XfSMXaL JU0ZFi8PaVocmP2Q1eLVmY1sFpcXXmK1+H7D1KJ3wVU2i02Pr7FaXN41h83i7LzjbBYzzu9j stg49RejRfslZYsVTVsZLRZfXM5ssX7GaxaL3SuXsFgcm7GE0eLpgyYmB1GPNfPWMHr8/jWJ 0aNvylU2jyebLjJ6LNhU6nHn2h42j81L6j3Oz1jI6PF9Ry9QwZZVjB4/X+p4PP2xl9nj8ya5 AN6oBkabjNTElNQihdS85PyUzLx0WyXv4HjneFMzA0NdQ0sLcyWFvMTcVFslF58AXbfMHKBv lRTKEnNKgUIBicXFSvp2mCaEhrjpWsA0Ruj6hgTB9RgZoIGEdYwZz5ctYitY2cVY0bzvJFMD 483ELkZODgkBE4mprTcYIWwxiQv31rN1MXJxCAlMZ5R4+XcdC4Tzi1HiSNtPVpAqNgE1iS9f DrOD2CIC/hLXrraCFTELtLFJrH/2ESwhLGAv8at3BxOIzSKgKnFn/X2wFbwClhIbrvexQNiC Ej8m3wOzmQW0JNbvPM4EYctLbF7zlhniJAWJHWdfM0Is05O4+GUqO0SNiMS+F+8YJzAKzEIy ahaSUbOQjJqFpGUBI8sqRtHUguSC4qT0XCO94sTc4tK8dL3k/NxNjOD09Ux6B+OqBotDjAIc jEo8vBqXDwYKsSaWFVfmHmKU4GBWEuFNnXMoUIg3JbGyKrUoP76oNCe1+BBjMtCnE5mlRJPz gak1ryTe0NjEzMjSyMzCyMTcnDRhJXHeg63WgUIC6YklqdmpqQWpRTBbmDg4pRqAnlC8mrKn pkCx68Wq632V5psvnxGX/ibqrRW/JKveTvWq9ppHXl8/XXuuMT+3YkNsSotV18c/hYZvXhuI znwv4LpF+rxh+r5FPxh911UecBdt4WE8GORmerLmc3r705mKhz8d7e8Q5WVOmlFW8Thr8z35 jPp9X+v5gz682vzU/Srj0bmvy1SVWIozEg21mIuKEwGYfqaeowMAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, This series of patches introduces PCIe support for Samsung Exynos5440, and is based on the latest 'linux-next' tree (20130619). These patches was tested with Intel e1000e LAN card on Exynos5440. This PATCH v8 follows: * PATCH v7, sent on June, 20th 2013 * PATCH v6, sent on June, 20th 2013 * PATCH v5, sent on June, 13th 2013 * PATCH v4, sent on June, 12th 2013 * PATCH v3, sent on June, 6th 2013 * PATCH v2, sent on March, 23rd 2013 * PATCH v1, sent on March, 4th 2013 Changes between v7 and v8: * Changed the file name from 'pci-exynos.c' to 'pci-designware.c', and added a generic string for compatible property to exynos-pcie.txt * Moved pci_add_resource_offset() for I/O space to the 'if' clause * Added Arnd's Acked-by Changes between v6 and v7: * Split ARM DT patch to two patches * Fixed node naming * Added Arnd's Acked-by Changes between v5 and v6: * Replaced phys_addr_t with u64 for physical addresses of regions * Removed unnecessary inbound functions * Added handling of io_offset, mem_offset as Arnd Bergmann guided * Fixed calculating 'io' resource * Removed module_exit() in order not to allow module unload Changes between v4 and v5: * Used gpio binding in DT * Increased the size of MEM region to 512 MB including CFG and IO regions in DT * Reduced the size of CFG region to 4096 byte in DT * Used the size of MEM region instead of hard-coded in_mem_size * Fixed exynos_pcie_prog_viewport_{mem/io}_{outbound/inbound} functions to use both translated addresses and untranslated addresses * Replaced pci_add_resource_offset() with pci_add_resource() * Added values from the DT individually to io_base, mem_base Changes between v3 and v4: * Added support for multi domains as reviewed by Jason Gunthorpe, and Arnd Bergmann. * Fixed both MEM space and I/O space in DT. * Removed redundant physical addresses from struct pcie_port, added devm_ioremap_resource() to make add_pcie_port() simpler. * Added clock names and clock enable/disable. Changes between v2 and v3: * Rebased on the top of 3.10-rc4 * Updated names of PCIe PHY registers Changes between v1 and v2: * Moved Exynos PCIe driver from arch/arm to drivers/pci/host. * Added DT properties of PCI DT standard. Here is the lspci -vv output. 0000:00:00.0 PCI bridge: Samsung Electronics Co Ltd Device a549 (rev 01) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- TAbort- Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Power Management version 3 Flags: PMEClk- DSI- D1+ D2- AuxCurrent=375mA PME(D0+,D1+,D2-,D3hot+,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: [70] Express (v2) Root Port (Slot-), MSI 00 DevCap: MaxPayload 512 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag+ RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 5GT/s, Width x4, ASPM L0s L1, Latency L0 <64ns, L1 <2us ClockPM- Surprise- LLActRep+ BwNot+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk- DLActive+ BWMgmt+ ABWMgmt- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- DevCap2: Completion Timeout: Range ABCD, TimeoutDis+ ARIFwd- DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- ARIFwd- LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1- EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- Capabilities: [100 v2] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn- Capabilities: [148 v1] Virtual Channel Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 Arb: Fixed- WRR32- WRR64- WRR128- Ctrl: ArbSelect=Fixed Status: InProgress- VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256- Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff Status: NegoPending- InProgress- Kernel driver in use: pcieport 0000:01:00.0 Ethernet controller: Intel Corporation 82574L Gigabit Network Connection Subsystem: Intel Corporation Gigabit CT Desktop Adapter Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- TAbort- SERR- TAbort- Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Power Management version 3 Flags: PMEClk- DSI- D1+ D2- AuxCurrent=375mA PME(D0+,D1+,D2-,D3hot+,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: [70] Express (v2) Root Port (Slot-), MSI 00 DevCap: MaxPayload 512 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag+ RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 5GT/s, Width x4, ASPM L0s L1, Latency L0 <64ns, L1 <2us ClockPM- Surprise- LLActRep+ BwNot+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk- DLActive+ BWMgmt+ ABWMgmt- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- DevCap2: Completion Timeout: Range ABCD, TimeoutDis+ ARIFwd- DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- ARIFwd- LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1- EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- Capabilities: [100 v2] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn- Capabilities: [148 v1] Virtual Channel Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 Arb: Fixed- WRR32- WRR64- WRR128- Ctrl: ArbSelect=Fixed Status: InProgress- VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256- Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff Status: NegoPending- InProgress- Kernel driver in use: pcieport 0001:01:00.0 Ethernet controller: Intel Corporation 82574L Gigabit Network Connection Subsystem: Intel Corporation Gigabit CT Desktop Adapter Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR-