Re: [PATCH v2] ASoC: Intel: sof_rt5682: Add support for jsl_rt5682_rt1019

[Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>]

On 9/5/22 10:07, Lu, Brent wrote:
> 
>> On 8/16/22 09:54, Sean Hong wrote:
>>> This patch adds the driver data for rt5682 support jsl_rt5682_rt1019.
>>>
>>> Signed-off-by: Sean Hong <sean.hong@quanta.corp-partner.google.com>
>>> ---
>>>  sound/soc/intel/boards/sof_rt5682.c               |  9 +++++++++
>>>  sound/soc/intel/common/soc-acpi-intel-jsl-match.c | 12 ++++++++++++
>>>  2 files changed, 21 insertions(+)
>>>
>>> diff --git a/sound/soc/intel/boards/sof_rt5682.c
>>> b/sound/soc/intel/boards/sof_rt5682.c
>>> index 045965312..3a840f3a9 100644
>>> --- a/sound/soc/intel/boards/sof_rt5682.c
>>> +++ b/sound/soc/intel/boards/sof_rt5682.c
>>> @@ -1100,6 +1100,15 @@ static const struct platform_device_id
>> board_ids[] = {
>>>  					SOF_RT5682_SSP_AMP(1) |
>>>  					SOF_RT5682_NUM_HDMIDEV(4)),
>>>  	},
>>> +	{
>>> +		.name = "jsl_rt5682_rt1019",
>>> +		.driver_data = (kernel_ulong_t)(SOF_RT5682_MCLK_EN |
>>> +					SOF_RT5682_MCLK_24MHZ |
>>
>> I see it's the same setting for all JSL devices but I am having doubts on this
>> MCLK.  Is this 24MHz value correct for JSL? It's derived from ICL so in theory
>> the MCLK should be a multiple of 19.2MHz if the root frequency was the
>> oscillator.
>>
>> Is this intentional?
>>
> 
> I've checked some internal wiki page and sof git log. It seems the first amp enabled
> on JSL is max98373 running in TDM 4 slot 100fs so 24MHz MCLK seems to be a
> reasonable choice. The commis is 5340225a7 ("topology: Add JSL da7219+max98373 support")
> 
> +# SSP 1 (ID: 0)
> +DAI_CONFIG(SSP, SPK_INDEX, 0, SPK_NAME,
> +       SSP_CONFIG(DSP_B, SSP_CLOCK(mclk, 24000000, codec_mclk_in),
> +               SSP_CLOCK(bclk, 4800000, codec_slave),
> +               SSP_CLOCK(fsync, 48000, codec_slave),
> +               SSP_TDM(4, 25, 3, 240),
> +               SSP_CONFIG_DATA(SSP, SPK_INDEX, 16)))
> 
> I've also tested 19.2MHz on JSL boards and it also works. 1K sinetone playback sounds ok.
> Since JSL boards are using 2.304 MHz bclk for max98360a and 3.072 MHz bclk for alc1015 now,
> changing to 19.2 MHz mclk seems no benefit.

Functionally there should be no difference, but the 24 MHz MCLK can only
be created on JSL from the 96 MHz HDaudio PLL while the 19.2 MHz can be
divided from the oscillator.

I guess it's too late to optimize now that the topology files are in use
so here is my Ack:

Acked-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>


but that's a clear miss in the topology reviews.