From: Rob Landley <landley@webofficenow.com>
To: Vojtech Pavlik <vojtech@suse.cz>
Cc: linux-kernel@vger.kernel.org
Subject: Re: Hardware testing [was Re: VIA Southbridge bug (Was: Crash on boot (2.4.5))]
Date: Wed, 11 Jul 2001 11:05:19 -0400 [thread overview]
Message-ID: <01071111051902.02490@localhost.localdomain> (raw)
In-Reply-To: <E15JIVD-0000Qc-00@the-village.bc.nu> <01071011282504.00634@localhost.localdomain> <20010711111159.A2026@suse.cz>
In-Reply-To: <20010711111159.A2026@suse.cz>
On Wednesday 11 July 2001 05:11, Vojtech Pavlik wrote:
> Don't forget the L1/L2/L3 caches. I had once a mainboard with a faulty
> L2 cache chip ('twas a K6-3 CPU, plus a FIC VA-503+ mainboard). No memory
> or CPU test found the failure, yet kernel compliation was still crashing
> after 6-8 hours.
>
> I modified the 'memtest.c' little proggy (not the big memtest86, just a
> little utility that runs under Linux), to use patterns and test size
> that tests the L1 and then L2, and the error has shown after ten seconds
> of running the test.
I don't suppose you still have that lying around somewhere? :)
Rob
next prev parent reply other threads:[~2001-07-12 0:07 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2001-06-25 6:17 Crash on boot (2.4.5) Andy Ward
2001-06-25 6:32 ` VIA Southbridge bug (Was: Crash on boot (2.4.5)) Steven Walter
2001-06-25 7:06 ` Alan Cox
2001-06-30 13:58 ` Pavel Machek
2001-07-08 17:37 ` Alan Cox
2001-07-09 16:48 ` Rob Landley
2001-07-10 9:17 ` Ville Herva
2001-07-10 15:28 ` Hardware testing [was Re: VIA Southbridge bug (Was: Crash on boot (2.4.5))] Rob Landley
2001-07-11 4:18 ` Albert D. Cahalan
2001-07-11 8:43 ` Ville Herva
2001-07-11 9:11 ` Vojtech Pavlik
2001-07-11 15:05 ` Rob Landley [this message]
2001-07-12 6:57 ` Ville Herva
2001-07-10 21:24 ` VIA Southbridge bug (Was: Crash on boot (2.4.5)) Adam Sampson
2001-07-11 8:32 ` Ville Herva
2001-07-11 9:03 ` Eyal Lebedinsky
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