From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Siddharth Vadapalli <s-vadapalli@ti.com>,
krzysztof.kozlowski+dt@linaro.org
Cc: robh+dt@kernel.org, lee.jones@linaro.org, kishon@ti.com,
vkoul@kernel.org, dan.carpenter@oracle.com, rogerq@kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-phy@lists.infradead.org,
linux-arm-kernel@lists.infradead.org, sjakhade@cadence.com
Subject: Re: [PATCH 1/6] dt-bindings: phy: ti: phy-gmii-sel: Add bindings for J721e
Date: Wed, 21 Sep 2022 08:39:35 +0200 [thread overview]
Message-ID: <011ce9d2-ea39-9235-323a-eac453effb66@linaro.org> (raw)
In-Reply-To: <fdeb4f4f-2712-fe35-a5c2-935d3a4baf38@ti.com>
On 20/09/2022 06:27, Siddharth Vadapalli wrote:
> Hello Krzysztof,
>
>>> + then:
>>> + properties:
>>> + ti,qsgmii-main-ports:
>>> + minItems: 2
>>> + maxItems: 2
>>> + items:
>>> + minimum: 1
>>> + maximum: 8
>>> +
>>> - if:
>>> not:
>>> properties:
>>> @@ -94,6 +133,7 @@ allOf:
>>> contains:
>>> enum:
>>> - ti,j7200-cpsw5g-phy-gmii-sel
>>> + - ti,j721e-cpsw9g-phy-gmii-sel
>>> then:
>>> properties:
>>> ti,qsgmii-main-ports: false
>>
>> This is interesting here... Did you test the bindings with your DTS?
>
> Yes, I tried it out with different compatibles in the DTS file for the
> node, making sure that the property "ti,qsgmii-main-ports" is allowed
> only for the "ti,j7200-cpsw5g-phy-gmii-sel" and the
> "ti,j721e-cpsw9g-phy-gmii-sel" compatibles. Additionally, I also tested
> that the "minItems", "maxItems", "minimum" and "maximum" checks apply.
> All of the rules within the "allOf", are enforced one after the other in
> sequence, based on my testing. Please let me know in case of any
> suggestions to implement it in a better way.
Great! I think I see now what I missed previously. The last hunk with
"ti,qsgmii-main-ports: false" is in a if: with negation ("not:")?
Best regards,
Krzysztof
next prev parent reply other threads:[~2022-09-21 6:39 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-14 9:39 [PATCH 0/6] Add support for J721e CPSW9G and SGMII mode Siddharth Vadapalli
2022-09-14 9:39 ` [PATCH 1/6] dt-bindings: phy: ti: phy-gmii-sel: Add bindings for J721e Siddharth Vadapalli
2022-09-14 16:15 ` Rob Herring
2022-09-15 5:28 ` Siddharth Vadapalli
2022-09-19 10:17 ` Krzysztof Kozlowski
2022-09-20 4:56 ` Siddharth Vadapalli
2022-09-21 6:36 ` Krzysztof Kozlowski
2022-09-19 10:15 ` Krzysztof Kozlowski
2022-09-20 4:27 ` Siddharth Vadapalli
2022-09-21 6:39 ` Krzysztof Kozlowski [this message]
2022-09-21 7:23 ` Siddharth Vadapalli
2022-09-14 9:39 ` [PATCH 2/6] phy: ti: gmii-sel: Add support for configuring CPSW5G ports in SGMII mode Siddharth Vadapalli
2022-09-14 9:39 ` [PATCH 3/6] phy: ti: gmii-sel: Add support for CPSW9G GMII SEL in J721e Siddharth Vadapalli
2022-09-14 11:34 ` Roger Quadros
2022-09-15 6:19 ` Siddharth Vadapalli
2022-09-14 9:39 ` [PATCH 4/6] phy: ti: gmii-sel: Enable SGMII mode configuration for J721E Siddharth Vadapalli
2022-09-14 9:39 ` [PATCH 5/6] phy: ti: phy-j721e-wiz: Add SGMII support in wiz driver " Siddharth Vadapalli
2022-09-14 9:39 ` [PATCH 6/6] phy: cadence: Sierra: Add PCIe + SGMII PHY multilink configuration Siddharth Vadapalli
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