RE: [PATCH 3/5] arm64: dts: exynos: add initial CMU clock nodes in Exynos Auto v920

sunyeal.hong
2024-07-05T07:52:26Z

Hello Jaewon,

> -----Original Message-----
> From: Jaewon Kim <jaewon02.kim@samsung.com>
> Sent: Friday, July 5, 2024 1:42 PM
> To: Sunyeal Hong <sunyeal.hong@samsung.com>; Krzysztof Kozlowski
> <krzk@kernel.org>; Sylwester Nawrocki <s.nawrocki@samsung.com>; Chanwoo
> Choi <cw00.choi@samsung.com>; Alim Akhtar <alim.akhtar@samsung.com>;
> Michael Turquette <mturquette@baylibre.com>; Stephen Boyd
> <sboyd@kernel.org>
> Cc: linux-samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org; linux-
> kernel@vger.kernel.org
> Subject: Re: [PATCH 3/5] arm64: dts: exynos: add initial CMU clock nodes
> in Exynos Auto v920
>
> Hi Sunyeal,
>
>
> On 7/5/24 11:11, Sunyeal Hong wrote:
> > Add cmu_top, cmu_peric0 clock nodes and switch USI clocks instead of
> > dummy fixed-rate-clock.
> >
> > Signed-off-by: Sunyeal Hong <sunyeal.hong@samsung.com>
> > ---
> > .../arm64/boot/dts/exynos/exynosautov920.dtsi | 40 +++++++++++++------
> > 1 file changed, 27 insertions(+), 13 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
> > b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
> > index c1c8566d74f5..1659c0a375c9 100644
> > --- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
> > +++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
> > @@ -6,6 +6,7 @@
> > *
> > */
> >
> > +#include <dt-bindings/clock/samsung,exynosautov920.h>
> > #include <dt-bindings/interrupt-controller/arm-gic.h>
> > #include <dt-bindings/soc/samsung,exynos-usi.h>
> >
> > @@ -38,17 +39,6 @@ xtcxo: clock {
> > clock-output-names = "oscclk";
> > };
> >
> > - /*
> > - * FIXME: Keep the stub clock for serial driver, until proper clock
> > - * driver is implemented.
> > - */
> > - clock_usi: clock-usi {
> > - compatible = "fixed-clock";
> > - #clock-cells = <0>;
> > - clock-frequency = <200000000>;
> > - clock-output-names = "usi";
> > - };
> > -
> > cpus: cpus {
> > #address-cells = <2>;
> > #size-cells = <0>;
> > @@ -182,6 +172,28 @@ chipid@10000000 {
> > reg = <0x10000000 0x24>;
> > };
> >
> > + cmu_peric0: clock-controller@10800000 {
> > + compatible = "samsung,exynosautov920-cmu-peric0";
> > + reg = <0x10800000 0x8000>;
> > + #clock-cells = <1>;
> > +
> > + clocks = <&xtcxo>,
> > + <&cmu_top DOUT_CLKCMU_PERIC0_NOC>,
> > + <&cmu_top DOUT_CLKCMU_PERIC0_IP>;
> > + clock-names = "oscclk",
> > + "dout_clkcmu_peric0_noc",
> > + "dout_clkcmu_peric0_ip";
> > + };
> > +
> > + cmu_top: clock-controller@11000000 {
> > + compatible = "samsung,exynosautov920-cmu-top";
> > + reg = <0x11000000 0x8000>;
> > + #clock-cells = <1>;
> > +
> > + clocks = <&xtcxo>;
> > + clock-names = "oscclk";
> > + };
> > +
> > gic: interrupt-controller@10400000 {
> > compatible = "arm,gic-v3";
> > #interrupt-cells = <3>;
> > @@ -213,7 +225,8 @@ usi_0: usi@108800c0 {
> > #address-cells = <1>;
> > #size-cells = <1>;
> > ranges;
> > - clocks = <&clock_usi>, <&clock_usi>;
> > + clocks = <&cmu_peric0 CLK_DOUT_PERIC0_USI00_USI>,
> > + <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>;
>
> it seems that the clocks have been switched.
> CLK_DOUT_PERIC0_USI00_USI is ipclk and CLK_MOUT_PERIC0_NOC_USER is pclk of
> USI.
>
>
>
> > clock-names = "pclk", "ipclk";
> > status = "disabled";
> >
> > @@ -224,7 +237,8 @@ serial_0: serial@10880000 {
> > interrupts = <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>;
> > pinctrl-names = "default";
> > pinctrl-0 = <&uart0_bus>;
> > - clocks = <&clock_usi>, <&clock_usi>;
> > + clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>,
> > + <&cmu_peric0 CLK_DOUT_PERIC0_USI00_USI>;
> > clock-names = "uart", "clk_uart_baud0";
> > samsung,uart-fifosize = <256>;
> > status = "disabled";
>
> Thanks
> Jaewon Kim
>

I will change ipclk and pclk clock node as you requested.

Thanks,
Sunyeal Hong