Re: [PATCH v4 1/5] hisi_acc_vfio_pci: fix XQE dma address error

liulongfang
2025-02-26T11:21:20Z

On 2025/2/25 14:27, Longfang Liu wrote:
> The dma addresses of EQE and AEQE are wrong after migration and
> results in guest kernel-mode encryption services failure.
> Comparing the definition of hardware registers, we found that
> there was an error when the data read from the register was
> combined into an address. Therefore, the address combination
> sequence needs to be corrected.
>
> Even after fixing the above problem, we still have an issue
> where the Guest from an old kernel can get migrated to
> new kernel and may result in wrong data.
>
> In order to ensure that the address is correct after migration,
> if an old magic number is detected, the dma address needs to be
> updated.
>
> Fixes: b0eed085903e ("hisi_acc_vfio_pci: Add support for VFIO live migration")
> Signed-off-by: Longfang Liu <liulongfang@huawei.com>
> ---
> .../vfio/pci/hisilicon/hisi_acc_vfio_pci.c | 40 ++++++++++++++++---
> .../vfio/pci/hisilicon/hisi_acc_vfio_pci.h | 14 ++++++-
> 2 files changed, 46 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c b/drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c
> index 451c639299eb..35316984089b 100644
> --- a/drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c
> +++ b/drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c
> @@ -350,6 +350,31 @@ static int vf_qm_func_stop(struct hisi_qm *qm)
> return hisi_qm_mb(qm, QM_MB_CMD_PAUSE_QM, 0, 0, 0);
> }
>
> +static int vf_qm_version_check(struct acc_vf_data *vf_data, struct device *dev)
> +{
> + switch (vf_data->acc_magic) {
> + case ACC_DEV_MAGIC_V2:
> + if (vf_data->major_ver < ACC_DRV_MAJOR_VER ||
> + vf_data->minor_ver < ACC_DRV_MINOR_VER)
> + dev_info(dev, "migration driver version not match!\n");
> + return -EINVAL;
> + break;
> + case ACC_DEV_MAGIC_V1:
> + /* Correct dma address */
> + vf_data->eqe_dma = vf_data->qm_eqc_dw[QM_XQC_ADDR_HIGH];
> + vf_data->eqe_dma <<= QM_XQC_ADDR_OFFSET;
> + vf_data->eqe_dma |= vf_data->qm_eqc_dw[QM_XQC_ADDR_LOW];
> + vf_data->aeqe_dma = vf_data->qm_aeqc_dw[QM_XQC_ADDR_HIGH];
> + vf_data->aeqe_dma <<= QM_XQC_ADDR_OFFSET;
> + vf_data->aeqe_dma |= vf_data->qm_aeqc_dw[QM_XQC_ADDR_LOW];
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> static int vf_qm_check_match(struct hisi_acc_vf_core_device *hisi_acc_vdev,
> struct hisi_acc_vf_migration_file *migf)
> {
> @@ -363,7 +388,8 @@ static int vf_qm_check_match(struct hisi_acc_vf_core_device *hisi_acc_vdev,
> if (migf->total_length < QM_MATCH_SIZE || hisi_acc_vdev->match_done)
> return 0;
>
> - if (vf_data->acc_magic != ACC_DEV_MAGIC) {
> + ret = vf_qm_version_check(vf_data, dev);
> + if (ret) {
> dev_err(dev, "failed to match ACC_DEV_MAGIC\n");
> return -EINVAL;
> }
> @@ -418,7 +444,9 @@ static int vf_qm_get_match_data(struct hisi_acc_vf_core_device *hisi_acc_vdev,
> int vf_id = hisi_acc_vdev->vf_id;
> int ret;
>
> - vf_data->acc_magic = ACC_DEV_MAGIC;
> + vf_data->acc_magic = ACC_DEV_MAGIC_V2;
> + vf_data->major_ver = ACC_DRV_MAR;
> + vf_data->minor_ver = ACC_DRV_MIN;

The values ​​here should be ACC_DRV_MAJOR_VER and ACC_DRV_MINOR_VER
I will fix this in the next version.

Thanks.
Longfang.

> /* Save device id */
> vf_data->dev_id = hisi_acc_vdev->vf_dev->device;
>
> @@ -496,12 +524,12 @@ static int vf_qm_read_data(struct hisi_qm *vf_qm, struct acc_vf_data *vf_data)
> return -EINVAL;
>
> /* Every reg is 32 bit, the dma address is 64 bit. */
> - vf_data->eqe_dma = vf_data->qm_eqc_dw[1];
> + vf_data->eqe_dma = vf_data->qm_eqc_dw[QM_XQC_ADDR_HIGH];
> vf_data->eqe_dma <<= QM_XQC_ADDR_OFFSET;
> - vf_data->eqe_dma |= vf_data->qm_eqc_dw[0];
> - vf_data->aeqe_dma = vf_data->qm_aeqc_dw[1];
> + vf_data->eqe_dma |= vf_data->qm_eqc_dw[QM_XQC_ADDR_LOW];
> + vf_data->aeqe_dma = vf_data->qm_aeqc_dw[QM_XQC_ADDR_HIGH];
> vf_data->aeqe_dma <<= QM_XQC_ADDR_OFFSET;
> - vf_data->aeqe_dma |= vf_data->qm_aeqc_dw[0];
> + vf_data->aeqe_dma |= vf_data->qm_aeqc_dw[QM_XQC_ADDR_LOW];
>
> /* Through SQC_BT/CQC_BT to get sqc and cqc address */
> ret = qm_get_sqc(vf_qm, &vf_data->sqc_dma);
> diff --git a/drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.h b/drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.h
> index 245d7537b2bc..91002ceeebc1 100644
> --- a/drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.h
> +++ b/drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.h
> @@ -39,6 +39,9 @@
> #define QM_REG_ADDR_OFFSET 0x0004
>
> #define QM_XQC_ADDR_OFFSET 32U
> +#define QM_XQC_ADDR_LOW 0x1
> +#define QM_XQC_ADDR_HIGH 0x2
> +
> #define QM_VF_AEQ_INT_MASK 0x0004
> #define QM_VF_EQ_INT_MASK 0x000c
> #define QM_IFC_INT_SOURCE_V 0x0020
> @@ -50,10 +53,15 @@
> #define QM_EQC_DW0 0X8000
> #define QM_AEQC_DW0 0X8020
>
> +#define ACC_DRV_MAJOR_VER 1
> +#define ACC_DRV_MINOR_VER 0
> +
> +#define ACC_DEV_MAGIC_V1 0XCDCDCDCDFEEDAACC
> +#define ACC_DEV_MAGIC_V2 0xAACCFEEDDECADEDE
> +
> struct acc_vf_data {
> #define QM_MATCH_SIZE offsetofend(struct acc_vf_data, qm_rsv_state)
> /* QM match information */
> -#define ACC_DEV_MAGIC 0XCDCDCDCDFEEDAACC
> u64 acc_magic;
> u32 qp_num;
> u32 dev_id;
> @@ -61,7 +69,9 @@ struct acc_vf_data {
> u32 qp_base;
> u32 vf_qm_state;
> /* QM reserved match information */
> - u32 qm_rsv_state[3];
> + u16 major_ver;
> + u16 minor_ver;
> + u32 qm_rsv_state[2];
>
> /* QM RW regs */
> u32 aeq_int_mask;
>