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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: O_nrS1S7kB25V_mTlfBxH7lflJCg8t12 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODE2MDA0NSBTYWx0ZWRfX9uafRPJi6BYO cgj9rg6OXr4QwdahcY3PGpMytW6upGG0N9oXgHzglndIzaZk4A5TMOlljP/CqGHguwO+ADrV+Q1 fOFlESYRCIuFLSfBgcOO8Vf1w+5iU+UIkFFYqYRCXBd8+CLVsDc+8luXPn2nifBp5U3AFYNZyVy r0Ok7/R/y7F2AhkM/gqwi77R5ypJg3WAhdJyrla4UGnDzQMPfFEOL84iRGYwSUZyLfy5eox4Cpp zssdqithLDbj4iMIVKe7JJT5JxJuUbPmYqwCpqnA5ek6TCnXHVaLk4c1UG49vDiONQ7srh6Qrvv eUmXS9UgppspKa8Cb/uMA5TIH3iEZKrx/KhstMeyI2esYf6+2qtSqE5g+X4vl3e/Q5gE8JJ0LJj FMNSwWFM X-Authority-Analysis: v=2.4 cv=IIMCChvG c=1 sm=1 tr=0 ts=68a2d2a9 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=9Q8gPALlkHEzzDxkdHlyxw==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=VwQbUJbxAAAA:8 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=1B6o04Z4kyHWbw-D5gsA:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: O_nrS1S7kB25V_mTlfBxH7lflJCg8t12 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-18_03,2025-08-14_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 clxscore=1015 impostorscore=0 phishscore=0 adultscore=0 malwarescore=0 bulkscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508160045 On 7/25/2025 2:05 PM, Neil Armstrong wrote: > The Adreno GPU Management Unit (GMU) can also scale DDR Bandwidth along > the Frequency and Power Domain level, but by default we leave the > OPP core scale the interconnect ddr path. > > Declare the Bus Control Modules (BCMs) and the corresponding parameters > in the GPU info struct to allow the GMU to vote for the bandwidth. > > Reviewed-by: Dmitry Baryshkov > Signed-off-by: Neil Armstrong Reviewed-by: Akhil P Oommen -Akhil > --- > Changes in v2: > - Used proper ACV perfmode bit/freq > - Link to v1: https://lore.kernel.org/r/20250721-topic-x1e80100-gpu-bwvote-v1-1-946619b0f73a@linaro.org > --- > drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > index 00e1afd46b81546eec03e22cda9e9a604f6f3b60..892f98b1f2ae582268adebd758437ff60456cdd5 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > @@ -1440,6 +1440,17 @@ static const struct adreno_info a7xx_gpus[] = { > .pwrup_reglist = &a7xx_pwrup_reglist, > .gmu_chipid = 0x7050001, > .gmu_cgc_mode = 0x00020202, > + .bcms = (const struct a6xx_bcm[]) { > + { .name = "SH0", .buswidth = 16 }, > + { .name = "MC0", .buswidth = 4 }, > + { > + .name = "ACV", > + .fixed = true, > + .perfmode = BIT(3), > + .perfmode_bw = 16500000, > + }, > + { /* sentinel */ }, > + }, > }, > .preempt_record_size = 4192 * SZ_1K, > .speedbins = ADRENO_SPEEDBINS( > > --- > base-commit: 97987520025658f30bb787a99ffbd9bbff9ffc9d > change-id: 20250721-topic-x1e80100-gpu-bwvote-9fc4690fe5e3 > > Best regards,