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charset="utf-8" CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20231009062222epcas5p36768b75c13c7c79965b5863521361a64 References: <20231009062216.6729-1-shradha.t@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Shradha > -----Original Message----- > From: Shradha Todi > Sent: Monday, October 9, 2023 11:52 AM > To: jingoohan1=40gmail.com; lpieralisi=40kernel.org; kw=40linux.com; > robh=40kernel.org; bhelgaas=40google.com; krzysztof.kozlowski=40linaro.or= g; > alim.akhtar=40samsung.com > Cc: linux-pci=40vger.kernel.org; linux-arm-kernel=40lists.infradead.org; = linux- > samsung-soc=40vger.kernel.org; linux-kernel=40vger.kernel.org; > pankaj.dubey=40samsung.com; Shradha Todi > Subject: =5BPATCH=5D PCI: exynos: Adapt to clk_bulk_* APIs >=20 > There is no need to hardcode the clock info in the driver as driver can r= ely on > the devicetree to supply the clocks required for the functioning of the > peripheral. Get rid of the static clock info and obtain the platform supp= lied > clocks. The total number of clocks supplied is obtained using the > devm_clk_bulk_get_all() API and used for the rest of the clk_bulk_* APIs. >=20 > Signed-off-by: Shradha Todi > --- > drivers/pci/controller/dwc/pci-exynos.c =7C 46 ++++++------------------- > 1 file changed, 11 insertions(+), 35 deletions(-) >=20 > diff --git a/drivers/pci/controller/dwc/pci-exynos.c > b/drivers/pci/controller/dwc/pci-exynos.c > index 9e42cfcd99cc..023cf41fccd7 100644 > --- a/drivers/pci/controller/dwc/pci-exynos.c > +++ b/drivers/pci/controller/dwc/pci-exynos.c > =40=40 -54,8 +54,8 =40=40 > struct exynos_pcie =7B > struct dw_pcie pci; > void __iomem *elbi_base; > - struct clk *clk; > - struct clk *bus_clk; > + struct clk_bulk_data *clks; > + int clk_cnt; > struct phy *phy; > struct regulator_bulk_data supplies=5B2=5D; > =7D; > =40=40 -65,30 +65,18 =40=40 static int exynos_pcie_init_clk_resources(str= uct > exynos_pcie *ep) > struct device *dev =3D ep->pci.dev; > int ret; >=20 > - ret =3D clk_prepare_enable(ep->clk); > - if (ret) =7B > - dev_err(dev, =22cannot enable pcie rc clock=22); > + ret =3D devm_clk_bulk_get_all(dev, &ep->clks); > + if (ret < 0) You can checking only for -ve value, what if devm_clk_bulk_get_all() retur= n 0? > return ret; > - =7D >=20 > - ret =3D clk_prepare_enable(ep->bus_clk); > - if (ret) =7B > - dev_err(dev, =22cannot enable pcie bus clock=22); > - goto err_bus_clk; > - =7D > + ep->clk_cnt =3D ret; >=20 > - return 0; > - > -err_bus_clk: > - clk_disable_unprepare(ep->clk); > - > - return ret; > + return clk_bulk_prepare_enable(ep->clk_cnt, ep->clks); > =7D >=20 > static void exynos_pcie_deinit_clk_resources(struct exynos_pcie *ep) = =7B > - clk_disable_unprepare(ep->bus_clk); > - clk_disable_unprepare(ep->clk); > + clk_bulk_disable_unprepare(ep->clk_cnt, ep->clks); > =7D >=20 > static void exynos_pcie_writel(void __iomem *base, u32 val, u32 reg) =40= =40 - > 332,17 +320,9 =40=40 static int exynos_pcie_probe(struct platform_device > *pdev) > if (IS_ERR(ep->elbi_base)) > return PTR_ERR(ep->elbi_base); >=20 > - ep->clk =3D devm_clk_get(dev, =22pcie=22); > - if (IS_ERR(ep->clk)) =7B > - dev_err(dev, =22Failed to get pcie rc clock=5Cn=22); > - return PTR_ERR(ep->clk); > - =7D > - > - ep->bus_clk =3D devm_clk_get(dev, =22pcie_bus=22); > - if (IS_ERR(ep->bus_clk)) =7B > - dev_err(dev, =22Failed to get pcie bus clock=5Cn=22); > - return PTR_ERR(ep->bus_clk); > - =7D > + ret =3D exynos_pcie_init_clk_resources(ep); > + if (ret < 0) > + return ret; >=20 > ep->supplies=5B0=5D.supply =3D =22vdd18=22; > ep->supplies=5B1=5D.supply =3D =22vdd10=22; > =40=40 -351,10 +331,6 =40=40 static int exynos_pcie_probe(struct platform= _device > *pdev) > if (ret) > return ret; >=20 > - ret =3D exynos_pcie_init_clk_resources(ep); > - if (ret) > - return ret; > - > ret =3D regulator_bulk_enable(ARRAY_SIZE(ep->supplies), ep- > >supplies); > if (ret) > return ret; > =40=40 -369,8 +345,8 =40=40 static int exynos_pcie_probe(struct platform_= device > *pdev) >=20 > fail_probe: > phy_exit(ep->phy); > - exynos_pcie_deinit_clk_resources(ep); > regulator_bulk_disable(ARRAY_SIZE(ep->supplies), ep->supplies); > + exynos_pcie_deinit_clk_resources(ep); >=20 > return ret; > =7D > -- > 2.17.1