From: Krzysztof Kozlowski <krzk@kernel.org>
To: adrianhoyin.ng@altera.com, dinguyen@kernel.org, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Cc: Matthew Gerlach <matthew.gerlach@altrera.com>
Subject: Re: [RESEND PATCH 1/2] arm64: dts: socfpga: agilex5: Add SMMU-V3-PMCG nodes
Date: Tue, 17 Jun 2025 08:27:00 +0200 [thread overview]
Message-ID: <0379000a-7ca6-4619-ad71-0ea9f71ffb8f@kernel.org> (raw)
In-Reply-To: <20250616145006.1081013-2-adrianhoyin.ng@altera.com>
On 16/06/2025 16:50, adrianhoyin.ng@altera.com wrote:
> From: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
>
> Add SMMU-V3 PMCG nodes for Agilex5.
>
> Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
> Reviewed-by: Matthew Gerlach <matthew.gerlach@altrera.com>
> ---
> .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 62 +++++++++++++++++++
> 1 file changed, 62 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> index 7d9394a04302..06920de87a41 100644
> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> @@ -133,6 +133,68 @@ usbphy0: usbphy {
> compatible = "usb-nop-xceiv";
> };
>
> + pmu0: pmu {
> + compatible = "arm,armv8-pmuv3";
> + interrupt-parent = <&intc>;
> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
> + };
> +
> + pmu0_tcu: pmu@16002000 {
It does not look like you tested the DTS against bindings. Please run
`make dtbs_check W=1` (see
Documentation/devicetree/bindings/writing-schema.rst or
https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/
for instructions).
Maybe you need to update your dtschema and yamllint. Don't rely on
distro packages for dtschema and be sure you are using the latest
released dtschema.
Or... if it passes still obviously mixes MMIO and non-MMIO nodes. MMIO
nodes go into soc@0.
Best regards,
Krzysztof
next prev parent reply other threads:[~2025-06-17 6:27 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-16 14:50 [RESEND PATCH 0/2] Add SMMU-V3-PMCG and L2/L3 cache nodes in Agilex5 DTSI adrianhoyin.ng
2025-06-16 14:50 ` [RESEND PATCH 1/2] arm64: dts: socfpga: agilex5: Add SMMU-V3-PMCG nodes adrianhoyin.ng
2025-06-17 6:27 ` Krzysztof Kozlowski [this message]
2025-06-17 8:56 ` Ng, Adrian Ho Yin
2025-06-16 14:50 ` [RESEND PATCH 2/2] arm64: dts: socfpga: agilex5: Add L2 and L3 cache adrianhoyin.ng
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