From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CC6A16BFA3; Wed, 7 Aug 2024 05:49:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723009774; cv=none; b=m2AclW8Icqvw+qODt4C90jn7sqLcTyw5/so+AFOGkjbRxytR9nednn/MI8SevbxRCw0oLWRG89ISwFlum3NhCSCaRJVN6yhY7r9MipzrI/A3neu5E+ORO3aCCYkvK4nGVpbUE9adIFvNXXjgC6y4nS2QchiuEnGv+gTTXzPh+Xw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723009774; c=relaxed/simple; bh=NfrOBcjO/1edtJr1f92xqBL5hzAd7ZcuUUv/ggnDR9k=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=J8ihSW43EZVb19NelqRicd6Yr4pO7cdgT8e25ixtzuZlxfEFXPWdi4MMkGgIBupfGsUlSeLcBRLgCpixBzOEeprytzKSpPo/GRFlL8SAC2Tq2aVuKLSwmj0qkfmqaFQ/pJX6g5HH8M+98neVLjIqH2YXLoElINrgRX9nFuSHS04= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=m1TKo++0; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="m1TKo++0" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6E926C32782; Wed, 7 Aug 2024 05:49:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1723009774; bh=NfrOBcjO/1edtJr1f92xqBL5hzAd7ZcuUUv/ggnDR9k=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=m1TKo++0oG4AuvFgbcX7Zd8lsvYZaSD5VQREoYuRyBL9UOmMw8NaTjxEXZ8E6Mxp/ M23nhWPGk+9QsPjZWRZWVq0pSveUuu8MCFTHwEZr41luoWO28Zgawm7f1UyJDUjT3Z VeG1qrEi3eHrQlCSaQmkEAZ175EHtvzSdbTeO1PWy7p/S2wZ4vabV/KLy2ZZyer6Ze Gd1eAZN4zSd7REZJDZTZQqSbgwX1ZdDHMrPdKBYBDXCSELrxovpExoA2Jzwxmacgz5 JjbfP45q3uuwOOibgDaewyPgAYamRzyr3+Bksk53uK0FC46DxVJpbS/SxnWOrgeqqQ cm5/vnS8qjzoA== Message-ID: <03b8a48c-e97e-4d7b-8378-66cc55ed56f7@kernel.org> Date: Wed, 7 Aug 2024 07:49:27 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/3] clk: rockchip: Add dt-binding header for rk3576 To: Detlev Casanova , linux-kernel@vger.kernel.org Cc: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Philipp Zabel , Elaine Zhang , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, kernel@collabora.com, Sugar Zhang References: <20240802214053.433493-1-detlev.casanova@collabora.com> <20240802214053.433493-3-detlev.casanova@collabora.com> <1600ee06-ac19-436f-8229-1bb44b29c683@kernel.org> <2949191.e9J7NaK4W3@trenzalore> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 06/08/2024 17:23, Detlev Casanova wrote: > On Sunday, 4 August 2024 05:53:57 EDT Krzysztof Kozlowski wrote: >> On 02/08/2024 23:35, Detlev Casanova wrote: >>> From: Elaine Zhang >>> >>> Add the dt-bindings header for the rk3576, that gets shared between >>> the clock controller and the clock references in the dts. >>> >>> Signed-off-by: Elaine Zhang >>> Signed-off-by: Sugar Zhang >>> [rebased, separate clocks and resets] >>> Signed-off-by: Detlev Casanova >> >> Please use subject prefixes matching the subsystem. You can get them for >> example with `git log --oneline -- DIRECTORY_OR_FILE` on the directory >> your patch is touching. For bindings, the preferred subjects are >> explained here: >> https://www.kernel.org/doc/html/latest/devicetree/bindings/submitting-patche >> s.html#i-for-patch-submitters >>> --- >>> >>> .../dt-bindings/clock/rockchip,rk3576-cru.h | 589 ++++++++++++++++++ >>> .../dt-bindings/reset/rockchip,rk3576-cru.h | 484 ++++++++++++++ >>> 2 files changed, 1073 insertions(+) >>> create mode 100644 include/dt-bindings/clock/rockchip,rk3576-cru.h >>> create mode 100644 include/dt-bindings/reset/rockchip,rk3576-cru.h >> >> These are bindings. Must be squashed with previous patch. > > Ok, so you'd rather have a commit for reset definitions (dt-bindings: reset: > Add rk3576 reset definitions) and another one for clock definitions + > Documentation (dt-bindings: clock: Add rk3576 clock definitions and > documentation) ? > >>> diff --git a/include/dt-bindings/clock/rockchip,rk3576-cru.h >>> b/include/dt-bindings/clock/rockchip,rk3576-cru.h new file mode 100644 >>> index 0000000000000..14b54543d1a11 >>> --- /dev/null >>> +++ b/include/dt-bindings/clock/rockchip,rk3576-cru.h >>> @@ -0,0 +1,589 @@ >>> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ >> >> Weird license. Why not using recommended one? > > Oh right, I suppose "GPL-2.0 OR MIT" is better ? At least that is what I see > for rk3588. include/dt-bindings/clock/rockchip,rv1126-cru.h uses "GPL-2.0+ OR > MIT" though. > >>> +/* >>> + * Copyright (c) 2023 Rockchip Electronics Co. Ltd. >>> + * Author: Elaine Zhang >>> + */ >>> + >>> +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3576_H >>> +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3576_H >>> + >>> +/* cru-clocks indices */ >>> + >>> +/* cru plls */ >>> +#define PLL_BPLL 1 >>> +#define PLL_LPLL 3 >>> +#define PLL_VPLL 4 >>> +#define PLL_AUPLL 5 >>> +#define PLL_CPLL 6 >>> +#define PLL_GPLL 7 >>> +#define PLL_PPLL 9 >> >> Nope, indices start from 1 and are incremented continuously. > > Why start at 1 ? RK3588 starts at 0 for clocks and resets Or 0, even better, sure. Best regards, Krzysztof