From: Russ Weight <russell.h.weight@intel.com>
To: "Wu, Hao" <hao.wu@intel.com>, "Xu, Yilun" <yilun.xu@intel.com>
Cc: Tom Rix <trix@redhat.com>, "mdf@kernel.org" <mdf@kernel.org>,
"linux-fpga@vger.kernel.org" <linux-fpga@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"lgoncalv@redhat.com" <lgoncalv@redhat.com>,
"Gerlach, Matthew" <matthew.gerlach@intel.com>
Subject: Re: [PATCH v17 0/5] FPGA Image Load (previously Security Manager)
Date: Tue, 26 Oct 2021 10:41:12 -0700 [thread overview]
Message-ID: <03ff4983-d8a9-6ad7-a655-a8dcde3da360@intel.com> (raw)
In-Reply-To: <DM6PR11MB38198F9B969569FDDD71A1CC85849@DM6PR11MB3819.namprd11.prod.outlook.com>
On 10/25/21 11:45 PM, Wu, Hao wrote:
>>>>>>>> The FPGA Image Load Framework was designed with the concept of
>>>>>>>> transferring data to a device without imposing a purpose on the data.
>>>>>>>> The expectation is that the lower-level driver or the device will
>>>>>>>> validate the data. Is there something fundamentally wrong with that
>>>>>>> I think there is something wrong here. As I said before, persistent
>>>>>>> storage updating has different software process from some runtime
>>>>>>> updating, so the class driver should be aware of what the HW engine
>>>>>>> is doing.
>>>>>> So far, there are no self-describing images that cause a
>>>>>> change in run-time behavior, and I don't think that will
>>>>>> happen for the very reason that the class-driver would
>>>>>> need to know about it.
>>>>> Again, the class driver needs to know what is happening, at some
>>>>> abstraction level, to ensure the system is aligned with the HW state.
>>>>>
>>>>> If the class driver cannot tell the detail, it has to assume the
>>>>> whole FPGA region will be changed, and removal & re-enumeration is
>>>>> needed.
>>>> So we make it a requirement that the self-describing files
>>>> cannot make changes that require the class driver to manage
>>>> state.
>>> The API should not only define what it won't do, but also define what
>>> it will do. But the "image load" just specifies the top half of the
>>> process. So I don't think this API would be accepted.
>> So what is the path forward. It seems like you are saying
>> that the self-describing files do not fit in the fpga-mgr.
>> Can we reconsider the FPGA Image Load Framework, which does
>> not make any assumptions about the contents of the image
>> files?
> Why we need such "generic data transfer" interface in FPGA
> framework?
Are you referring to the use of self-describing files?
or the generic nature of this class driver?
> we need to handle the common need for FPGA
> devices only, not all devices, like programming FPGA images.
> So far we even don't know, what's the hardware response on
> these self-describing files, how we define it as a common need
> interface in the framework?
The class driver does not _need_ to reside in the FPGA
framework. I sent an inquiry to the maintainer of the
Firmware update subsystem (and cc'd the kernel mailing list)
and received no responses. I placed it under the FPGA
framework only because the first user of the class driver
is an FPGA driver.
> If you just want to reuse the
> fpga-mgr/framework code for your own purpose, Yes, it seems
> saving some code for you, but finally it loses flexibility, as it's
> not possible to extend common framework for your own
> purpose in the future.
If I understand correctly, you are saying that it doesn't
fit well in the FPGA manager, because not all file types
fit the definition of a firmware update? And future file
types may not fit in fpga-mgr context?
- Russ
>
> Thanks
> Hao
next prev parent reply other threads:[~2021-10-26 17:59 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-29 23:00 [PATCH v17 0/5] FPGA Image Load (previously Security Manager) Russ Weight
2021-09-29 23:00 ` [PATCH v17 1/5] fpga: image-load: fpga image load framework Russ Weight
2021-09-29 23:00 ` [PATCH v17 2/5] fpga: image-load: enable image uploads Russ Weight
2021-10-06 18:13 ` Russ Weight
2021-09-29 23:00 ` [PATCH v17 3/5] fpga: image-load: signal eventfd when complete Russ Weight
2021-09-29 23:00 ` [PATCH v17 4/5] fpga: image-load: add status ioctl Russ Weight
2021-10-15 20:22 ` Lizhi Hou
2021-10-20 21:42 ` Russ Weight
2021-10-26 0:07 ` Lizhi Hou
2021-09-29 23:00 ` [PATCH v17 5/5] fpga: image-load: enable cancel of image upload Russ Weight
2021-10-09 8:08 ` [PATCH v17 0/5] FPGA Image Load (previously Security Manager) Xu Yilun
2021-10-09 12:11 ` Tom Rix
2021-10-11 1:41 ` Xu Yilun
2021-10-11 12:35 ` Tom Rix
2021-10-12 1:00 ` Russ Weight
2021-10-12 7:47 ` Xu Yilun
2021-10-12 7:56 ` Xu Yilun
2021-10-12 17:20 ` Russ Weight
2021-10-13 1:06 ` Xu Yilun
2021-10-13 18:09 ` Russ Weight
2021-10-14 1:49 ` Xu Yilun
[not found] ` <7d1971d0-b50b-077f-2a82-83d822cd2ad7@intel.com>
2021-10-15 2:51 ` Xu Yilun
2021-10-15 17:34 ` Russ Weight
2021-10-18 8:13 ` Xu Yilun
2021-10-18 16:24 ` Russ Weight
2021-10-19 2:53 ` Xu Yilun
2021-10-19 15:09 ` Russ Weight
2021-10-20 1:16 ` Xu Yilun
2021-10-20 16:27 ` Russ Weight
2021-10-26 6:45 ` Wu, Hao
2021-10-26 17:41 ` Russ Weight [this message]
2021-10-27 3:29 ` Wu, Hao
2021-10-27 15:11 ` Russ Weight
2021-10-27 15:34 ` Tom Rix
2021-10-28 15:09 ` Xu Yilun
2021-10-28 16:08 ` Tom Rix
2021-10-29 2:05 ` Xu Yilun
2021-10-12 7:49 ` Xu Yilun
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