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From: Philipp Zabel <p.zabel@pengutronix.de>
To: george.moussalem@outlook.com, Andrew Lunn <andrew@lunn.ch>,
	Heiner Kallweit <hkallweit1@gmail.com>,
	Russell King <linux@armlinux.org.uk>,
	"David S. Miller" <davem@davemloft.net>,
	Eric Dumazet <edumazet@google.com>,
	Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
	Rob Herring <robh@kernel.org>,
	 Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Florian Fainelli <f.fainelli@gmail.com>,
	Bjorn Andersson <andersson@kernel.org>,
	Konrad Dybcio <konradybcio@kernel.org>,
	Michael Turquette <mturquette@baylibre.com>,
	 Stephen Boyd <sboyd@kernel.org>
Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org,
	 linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
	 linux-clk@vger.kernel.org
Subject: Re: [PATCH v3 3/5] net: phy: qcom: at803x: Add Qualcomm IPQ5018 Internal PHY support
Date: Mon, 16 Jun 2025 13:01:34 +0200	[thread overview]
Message-ID: <0444ceee9743a349bb7155dac6ca7ea25f5adb18.camel@pengutronix.de> (raw)
In-Reply-To: <20250602-ipq5018-ge-phy-v3-3-421337a031b2@outlook.com>

On Mo, 2025-06-02 at 13:53 +0400, George Moussalem via B4 Relay wrote:
> From: George Moussalem <george.moussalem@outlook.com>
> 
> The IPQ5018 SoC contains a single internal Gigabit Ethernet PHY which
> provides an MDI interface directly to an RJ45 connector or an external
> switch over a PHY to PHY link.
> 
> The PHY supports 10/100/1000 mbps link modes, CDT, auto-negotiation and
> 802.3az EEE.
> 
> Let's add support for this PHY in the at803x driver as it falls within
> the Qualcomm Atheros OUI.
> 
> Signed-off-by: George Moussalem <george.moussalem@outlook.com>
> ---
>  drivers/net/phy/qcom/Kconfig  |   2 +-
>  drivers/net/phy/qcom/at803x.c | 185 ++++++++++++++++++++++++++++++++++++++++--
>  2 files changed, 178 insertions(+), 9 deletions(-)
> 
[...]
> diff --git a/drivers/net/phy/qcom/at803x.c b/drivers/net/phy/qcom/at803x.c
> index 26350b962890b0321153d74758b13d817407d094..c148e245b5391c5da374ace8609dcdfd8284732d 100644
> --- a/drivers/net/phy/qcom/at803x.c
> +++ b/drivers/net/phy/qcom/at803x.c
> @@ -7,19 +7,24 @@
[...]
> +static int ipq5018_probe(struct phy_device *phydev)
> +{
> +	struct device *dev = &phydev->mdio.dev;
> +	struct ipq5018_priv *priv;
> +	int ret;
> +
> +	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> +	if (!priv)
> +		return -ENOMEM;
> +
> +	priv->set_short_cable_dac = of_property_read_bool(dev->of_node,
> +							  "qcom,dac-preset-short-cable");
> +
> +	priv->rst = devm_reset_control_array_get_exclusive(dev);

Both dt-bindings and dts patch only show a single reset. Is there a
reason this is a reset_control_array?

regards
Philipp

  parent reply	other threads:[~2025-06-16 11:01 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-02  9:53 [PATCH v3 0/5] Add support for the IPQ5018 Internal GE PHY George Moussalem via B4 Relay
2025-06-02  9:53 ` [PATCH v3 1/5] clk: qcom: gcc-ipq5018: fix GE PHY reset George Moussalem via B4 Relay
2025-06-02  9:53 ` [PATCH v3 2/5] dt-bindings: net: qca,ar803x: Add IPQ5018 Internal GE PHY support George Moussalem via B4 Relay
2025-06-05 18:14   ` Rob Herring
2025-06-06 10:54     ` George Moussalem
2025-06-06 13:01       ` Andrew Lunn
2025-06-07  7:32         ` Russell King (Oracle)
2025-06-02  9:53 ` [PATCH v3 3/5] net: phy: qcom: at803x: Add Qualcomm IPQ5018 Internal " George Moussalem via B4 Relay
2025-06-02 12:41   ` Andrew Lunn
2025-06-02 13:02     ` George Moussalem
2025-06-02 13:49       ` Andrew Lunn
2025-06-05 18:18     ` Rob Herring
2025-06-16 11:01   ` Philipp Zabel [this message]
2025-06-16 12:38     ` George Moussalem
2025-06-02  9:53 ` [PATCH v3 4/5] arm64: dts: qcom: ipq5018: Add MDIO buses George Moussalem via B4 Relay
2025-06-02  9:53 ` [PATCH v3 5/5] arm64: dts: qcom: ipq5018: Add GE PHY to internal mdio bus George Moussalem via B4 Relay

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