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Tue, 21 Jul 2026 02:28:57 -0700 (PDT) X-Received: by 2002:a17:90b:580c:b0:38e:2524:724f with SMTP id 98e67ed59e1d1-38e4b410109mr18418025a91.12.1784626137393; Tue, 21 Jul 2026 02:28:57 -0700 (PDT) Received: from [10.218.15.172] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-13d093bd8f6sm3740252c88.4.2026.07.21.02.28.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 21 Jul 2026 02:28:56 -0700 (PDT) Message-ID: <05081037-9ed8-4e0d-8480-cfa45e950727@oss.qualcomm.com> Date: Tue, 21 Jul 2026 14:58:49 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] arm64: Disallow disabling boot CPU based on config To: Sudeep Holla , Daniel Lezcano Cc: Thomas Gleixner , Peter Zijlstra , "Rafael J. Wysocki" , Pavel Machek , Len Brown , Catalin Marinas , Mark Rutland , Lorenzo Pieralisi , Will Deacon , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org References: <20260703-disable_boot_cpu_offline-v2-1-782d16ff58c3@oss.qualcomm.com> <20260703-competent-adaptable-coot-f8daaf@sudeepholla> <4b7fe7e6-2531-4d26-9085-43f40a2ce2e0@oss.qualcomm.com> <20260706-practical-inchworm-of-experience-d4e0ed@sudeepholla> Content-Language: en-US From: Sneh Mankad In-Reply-To: <20260706-practical-inchworm-of-experience-d4e0ed@sudeepholla> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzIxMDA5OSBTYWx0ZWRfX4jGJG4yOPYVY J/4ES7ORIMeyelZEUizBKMd5pyxVURtj90v9/h2gRJ8ZH3epEBpLXU4/Q56sCx4/srA5wQUxyCp tsHOmU/jXKLlQEqI1RHwhIBi99tryzQ/cpmPOuIQ7q5hw0XHf9+58uYQ0/I0KL+kHcFURlpnVVk G+KZ1TJvuCb8nfNZjKq13wqxKygjDeQIrYNtyapI6mhh8r1Z6jnbMuO6KKFF2e5F1xtVnc7CQu3 5EuBfyLoy7S7x1jTg+jzinbhj4nHfo+lzwfkyOoTh/onwHZ4OgROjjVFYx2GGTqv4EoApyTSW8K uYOnRfzmV+NF32fBq2VqoGEhPmKGWhD/leQS+hv5+PJlWXppSgqSDuqwBhPd5V4xPSHSTaF4/AD e50TyaYqpWckpMYpHThy8OAfezKQ2NnO26xtRifsfU8V/XEtHN9fnfc/kX0mh8wsPH16M5f1rm/ 3BYZs9YN8nXaY4jGrVw== X-Proofpoint-Spam-Info: AW1haW4tMjYwNzIxMDA5OSBTYWx0ZWRfX9b36JkVSxAT+ r5zFCa+OF9KLAHw83+3CrF5sWGcsekH/zuz5M6XfcVARXv41QcL12zAog+/V0ZxER5IBDUeV0sP YPKvfy+00GsyhEiC+J5SvUa8zBaRK9U= X-Authority-Analysis: v=2.4 cv=WNpPmHsR c=1 sm=1 tr=0 ts=6a5f3bda cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=dWC8hVThGWP9nuoixJoA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 X-Proofpoint-GUID: cECQ-tTGYgempQJfYNIKOAfIrTCwfIBH X-Proofpoint-ORIG-GUID: cECQ-tTGYgempQJfYNIKOAfIrTCwfIBH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-20_06,2026-07-20_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 clxscore=1015 suspectscore=0 spamscore=0 malwarescore=0 priorityscore=1501 impostorscore=0 phishscore=0 bulkscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607210099 On 06-Jul-26 2:46 PM, Sudeep Holla wrote: > On Sat, Jul 04, 2026 at 08:43:39AM +0200, Daniel Lezcano wrote: >> >> Hi Sudeep, >> >> Le 03/07/2026 à 17:51, Sudeep Holla a écrit : >>> (It is always good to cc all PSCI maintainer for any ARM64 CPU >>> hotpug/suspend related changes) >>> >>> On Fri, Jul 03, 2026 at 04:50:02PM +0530, Sneh Mankad wrote: >>>> The Qualcomm SoCs like LeMans, Monaco support suspend to ram which leads >>>> the SoC to ACPI S3 similar state where SoC is turned off and DDR is >>>> retained. The hardware design on these SoCs forces a constraint to suspend >>>> and resume the system on boot CPU / CPU0. >>>> >>> And you fail to explain why they have that constraint. >>> > > I still need the above to understand the issue/constraint better. Above mentioned SoCs have boot CPU fixed to CPU0 in HW, whenever SoC boots up/cold boots it starts with CPU0. These SoCs support suspend to ram which leads to ACPI S3 similar state (where SoC is turned off and DDR is retained) PSCI SYSTEM_SUSPEND typically will be executed on boot core itself unless it is already offlined and non boot CPUs gets offlined using PSCI CPU_OFF. As HW constraint always makes the SoC to boot with boot CPU, consider a scenario, where Boot CPU is already disabled / offline => suspend to ram is triggered => SoC enters ACPI S3 similar state (only DDR is retained and rest of the SoC is off) External wake up arrives (say power key press) => SoC starts booting with CPU0 => CPU0 becomes first one to "land" in kernel now. Kernel may later bring up other non-boot CPUs via PSCI CPU_ON calls.t However Kernel had already marked CPU0 as disabled/ offline but same ended up in kernel without PSCI CPU_ON call. To prevent this inconsistent state, before starting suspend to ram, need to make sure CPU0 is always online from kernel/ disable offlining of the boot CPU. Although the HW constraint needs boot CPU to be online only when suspend to ram is triggered, current patch disallows disabling it for simplicity. > >>> Is it because some secure context is not allowed to migrate ? >>> >>> We already have a mechanism for that in place and this hack is not at all >>> required. >> Do you mean a mechanism for the secure context or for preventing CPU0 ? >> > > I meant constraint based on secure context. > This is not because secure context not allowed to migrate but above mentioned HW constraints. Thanks, Sneh