From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753776AbeAZP5v (ORCPT ); Fri, 26 Jan 2018 10:57:51 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:50050 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753598AbeAZP5r (ORCPT ); Fri, 26 Jan 2018 10:57:47 -0500 Subject: Re: [PATCH 13/16] arm64: Add support for checking errata based on a list of MIDRS To: Dave Martin Cc: linux-arm-kernel@lists.infradead.org, mark.rutland@arm.com, ckadabi@codeaurora.org, ard.biesheuvel@linaro.org, marc.zyngier@arm.com, catalin.marinas@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, jnair@caviumnetworks.com References: <20180123122809.16269-1-suzuki.poulose@arm.com> <20180123122809.16269-14-suzuki.poulose@arm.com> <20180126141610.GU5862@e103592.cambridge.arm.com> From: Suzuki K Poulose Message-ID: <0558db28-b1f1-b249-6098-99e1071f613f@arm.com> Date: Fri, 26 Jan 2018 15:57:44 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.2 MIME-Version: 1.0 In-Reply-To: <20180126141610.GU5862@e103592.cambridge.arm.com> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 26/01/18 14:16, Dave Martin wrote: > On Tue, Jan 23, 2018 at 12:28:06PM +0000, Suzuki K Poulose wrote: >> Add helpers for detecting an errata on list of midr ranges >> of affected CPUs. > > This doesn't describe what the patch does: instead, helpers are being > added for checking whether an MIDR falls in one of multiple affected > model(s) and or revision(s). > > Doing this makes sense, but is it really worth it? Well, we need th MIDR list helpers anyway for other things: - White list of CPUs where we know KPTI is not needed - Black list of CPUs where DBM shouldn't be enabled. So all we do is add a new type which could reduce the number of entries. > > We might save 100-200 bytes in the kernel image for now, but a common > workaround for errata on multiple unrelated cpus is surely a rare case. > > Only if there are many such lists, or if the lists become large does > this start to seem a clear win. > >> >> Signed-off-by: Suzuki K Poulose >> --- >> arch/arm64/include/asm/cpufeature.h | 1 + >> arch/arm64/kernel/cpu_errata.c | 40 ++++++++++++++++++++++--------------- >> 2 files changed, 25 insertions(+), 16 deletions(-) >> >> diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h >> index a3d54c2c411f..70712de687c7 100644 >> --- a/arch/arm64/include/asm/cpufeature.h >> +++ b/arch/arm64/include/asm/cpufeature.h > > [...] > >> @@ -330,22 +353,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = { >> #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR >> { >> .capability = ARM64_HARDEN_BRANCH_PREDICTOR, >> - ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), >> - .enable = enable_psci_bp_hardening, >> - }, >> - { >> - .capability = ARM64_HARDEN_BRANCH_PREDICTOR, >> - ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), >> - .enable = enable_psci_bp_hardening, >> - }, >> - { >> - .capability = ARM64_HARDEN_BRANCH_PREDICTOR, >> - ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), >> - .enable = enable_psci_bp_hardening, >> - }, >> - { >> - .capability = ARM64_HARDEN_BRANCH_PREDICTOR, >> - ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A75), >> + ERRATA_MIDR_RANGE_LIST(cortex_bp_harden_cpus), > > Could we just use a macro to generate multiple structs, instead of > inventing a new type of struct? We could. Somehow, I don't think we are over engineering much here. Cheers Suzuki