From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 81FC83E8C50 for ; Fri, 15 May 2026 09:58:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778839097; cv=none; b=YYJxra+NhC21N1tH5hfGIJdbs8F5TXm/0iXe4Qc9Sj+h7ZH/HLJnaT6RhPd4jaFcJj+SiMnIYeNUey7OOKiNpQiFmI/lElPzjpVMj505K//+TPwYNBgBOBLIOOP2pFhqzR1oGI94yT/8XR5SbIZnAXeZ7eBOCZGfsa+hnSIowzQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778839097; c=relaxed/simple; bh=oWtNtLFEzhEorQ0wHbh9xN1hmDt/Ws71h7zt9GVd3PI=; h=Message-ID:Date:MIME-Version:Subject:To:CC:References:From: In-Reply-To:Content-Type; b=EQyl4dVTq6lzQq/brv7aejR9qahcc4Q87uSluWa9ED8msMuTyXH/hvqtIdmYfqLdAQ4K3DrtLVMgMZ16fpeTJyu3UbEsV+IQgzQh1oslubodlUVevTCnlYRaM0M+7Bx9+HDB/eLIRrIq9RRBzujdS1SQpoYrz1VzExs4wgmvYSE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=iuB29hLy; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="iuB29hLy" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1778839096; x=1810375096; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=oWtNtLFEzhEorQ0wHbh9xN1hmDt/Ws71h7zt9GVd3PI=; b=iuB29hLyRfcOP6JWgddcMQdN0DH70HDb5WNxXv+nPmHKlTMX9HKH1Wba OnJTT9Er6uwBQgGk8bPOpKVyI2jUmfDWSTiXHUH1gngaVuA8wrhB0/Qjk LGioJ7kR7w/XLPfXTQoYkkMbvghBsOFze5mCIDUDAa+ZNdvILOX4AJoWS YEMhhA+ipfAY3UKHFxaAej49XvP3d9Qhs5Oxq+MpsqMOV+F+tKkxyl1RX 3VUD9GJfbCgYrTPWzVqKiGa6bXV5JXJ7BCbHSITQSsEhUeHPStVsRaVIe xV39SSRu1wcgbq6EGrsZbBbnpaxbnAxqVvOw99tFGVCir6GPvRxsYSDEu w==; X-CSE-ConnectionGUID: tPpFVbmlQVyUrJeCq5qw1g== X-CSE-MsgGUID: OQ64741MRoSIOz0zCJfh6Q== X-IronPort-AV: E=Sophos;i="6.23,236,1770620400"; d="scan'208";a="288921340" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 15 May 2026 02:58:16 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Fri, 15 May 2026 02:58:15 -0700 Received: from [10.159.205.44] (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Fri, 15 May 2026 02:58:13 -0700 Message-ID: <067c55c0-d56c-496e-bf75-5c3491524256@microchip.com> Date: Fri, 15 May 2026 11:58:13 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1] irqchip/atmel-aic5: Free SMR cache on init failure To: Yuho Choi , Thomas Gleixner , Alexandre Belloni , Claudiu Beznea CC: , References: <20260513233139.659956-1-dbgh9129@gmail.com> From: Nicolas Ferre Content-Language: en-US, fr Organization: microchip In-Reply-To: <20260513233139.659956-1-dbgh9129@gmail.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit On 14/05/2026 at 01:31, Yuho Choi wrote: > sama5d2_aic5_of_init() allocates the SMR cache before calling > aic5_of_init(). If that fails, the cache is left allocated even though > no IRQ domain was installed and the cache will not be used. > > Free the cache on the failure path and clear the global pointer. No aic5 = no viable system to run on: I'm not sure it's worth considering the case. > Fixes: a50ac562ef48 ("irqchip/atmel-aic5: Handle suspend to RAM") > Signed-off-by: Yuho Choi > --- > drivers/irqchip/irq-atmel-aic5.c | 11 ++++++++++- > 1 file changed, 10 insertions(+), 1 deletion(-) > > diff --git a/drivers/irqchip/irq-atmel-aic5.c b/drivers/irqchip/irq-atmel-aic5.c > index 1f14b401f71d..58650eb16880 100644 > --- a/drivers/irqchip/irq-atmel-aic5.c > +++ b/drivers/irqchip/irq-atmel-aic5.c > @@ -358,13 +358,22 @@ static int __init sama5d2_aic5_of_init(struct device_node *node, > struct device_node *parent) > { > #ifdef CONFIG_PM > + int rc = 0; > smr_cache = kcalloc(DIV_ROUND_UP(NR_SAMA5D2_IRQS, 32) * 32, > sizeof(*smr_cache), GFP_KERNEL); > if (!smr_cache) > return -ENOMEM; > -#endif > > + rc = aic5_of_init(node, parent, NR_SAMA5D2_IRQS); > + if (rc) { > + kfree(smr_cache); > + smr_cache = NULL; > + } > + > + return rc; > +#else > return aic5_of_init(node, parent, NR_SAMA5D2_IRQS); > +#endif > } > IRQCHIP_DECLARE(sama5d2_aic5, "atmel,sama5d2-aic", sama5d2_aic5_of_init); > > -- > 2.43.0 >