Re: [RESEND PATCH V3 2/8] perf/x86/intel: Basic support for metrics counters

Peter Zijlstra
2019-08-28T07:48:39Z

On Mon, Aug 26, 2019 at 07:47:34AM -0700, kan.liang@linux.intel.com wrote:
> Move BTS index to 47. Because bit 48 in the PERF_GLOBAL_STATUS is used
> to indicate the overflow status of PERF_METRICS counters now.

> diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
> index 457d35a75ad3..88a506312a10 100644
> --- a/arch/x86/include/asm/perf_event.h
> +++ b/arch/x86/include/asm/perf_event.h
> @@ -175,11 +175,56 @@ struct x86_pmu_capability {
> /*
> * We model BTS tracing as another fixed-mode PMC.
> *
> - * We choose a value in the middle of the fixed event range, since lower
> + * We choose value 47 for the fixed index of BTS, since lower
> * values are used by actual fixed events and higher values are used
> * to indicate other overflow conditions in the PERF_GLOBAL_STATUS msr.
> */
> -#define INTEL_PMC_IDX_FIXED_BTS (INTEL_PMC_IDX_FIXED + 16)
> +#define INTEL_PMC_IDX_FIXED_BTS (INTEL_PMC_IDX_FIXED + 15)

Can be its own patch.