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[212.182.62.129]) by smtp.gmail.com with ESMTPSA id c26-20020a19761a000000b0051009ef42a7sm199123lff.287.2024.01.23.10.36.17 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 23 Jan 2024 10:36:18 -0800 (PST) Message-ID: <07cef0ec-dc18-4cee-a6df-8c7f16600c50@linaro.org> Date: Tue, 23 Jan 2024 19:36:17 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 08/11] arm64: dts: qcom: x1e80100: Add display nodes Content-Language: en-US To: Abel Vesa , Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sibi Sankar , Rajendra Nayak Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20240123-x1e80100-dts-missing-nodes-v4-0-072dc2f5c153@linaro.org> <20240123-x1e80100-dts-missing-nodes-v4-8-072dc2f5c153@linaro.org> From: Konrad Dybcio In-Reply-To: <20240123-x1e80100-dts-missing-nodes-v4-8-072dc2f5c153@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 1/23/24 12:01, Abel Vesa wrote: > Add the required nodes to support display on X1E80100. > > Co-developed-by: Sibi Sankar > Signed-off-by: Sibi Sankar > Co-developed-by: Rajendra Nayak > Signed-off-by: Rajendra Nayak > Signed-off-by: Abel Vesa > --- > arch/arm64/boot/dts/qcom/x1e80100.dtsi | 518 +++++++++++++++++++++++++++++++++ > 1 file changed, 518 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > index e8d2ea2b26ed..247ff7a9e405 100644 > --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi > +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > @@ -4,6 +4,7 @@ > */ > > #include > +#include > #include > #include > #include > @@ -3298,6 +3299,523 @@ usb_1_ss1_role_switch: endpoint { > }; > }; > > + mdss: display-subsystem@ae00000 { > + compatible = "qcom,x1e80100-mdss"; > + reg = <0 0x0ae00000 0 0x1000>; > + reg-names = "mdss"; > + > + interrupts = ; > + > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&gcc GCC_DISP_AHB_CLK>, > + <&gcc GCC_DISP_HF_AXI_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_CLK>; > + > + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; > + > + interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS > + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, > + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "mdp0-mem", > + "mdp1-mem"; You likely also want to add the cpu-cfg path [...] > + > + dispcc: clock-controller@af00000 { > + compatible = "qcom,x1e80100-dispcc"; > + reg = <0 0x0af00000 0 0x20000>; > + clocks = <&bi_tcxo_div2>, > + <&bi_tcxo_ao_div2>, > + <&gcc GCC_DISP_AHB_CLK>, This clock is not actually registered with the CCF.. Which means it's also never cleanly shut down.. Please fix the clock driver and check which others got omitted as well. > + <&sleep_clk>, > + <0>, /* dsi0 */ > + <0>, > + <0>, /* dsi1 */ > + <0>, > + <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp0 */ > + <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, > + <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp1 */ > + <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, > + <&mdss_dp2_phy 0>, /* dp2 */ > + <&mdss_dp2_phy 1>, > + <&mdss_dp3_phy 0>, /* dp3 */ > + <&mdss_dp3_phy 1>; > + power-domains = <&rpmhpd RPMHPD_MMCX>; Likely: required-opps = <&rpmhpd_opp_low_svs>; so that the PLLs have a chance to spin up Konrad