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Thu, 10 Oct 2024 10:45:54 +0000 (GMT) Received: from epsmgmc1p1new.samsung.com (unknown [182.195.42.40]) by epsmtrp2.samsung.com (KnoxPortal) with ESMTP id 20241010104554epsmtrp2160f811a65734e82a61728cee45e78be~9EZLjbKzs2675126751epsmtrp2b; Thu, 10 Oct 2024 10:45:54 +0000 (GMT) X-AuditID: b6c32a49-0d5ff700000024cc-c0-6707b14cc17b Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgmc1p1new.samsung.com (Symantec Messaging Gateway) with SMTP id 5C.2C.07371.260B7076; Thu, 10 Oct 2024 19:45:54 +0900 (KST) Received: from FDSFTE196 (unknown [107.116.189.214]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20241010104552epsmtip1f5e87c940987a831806f878b5943e0b7~9EZJ76xC_2499324993epsmtip1b; Thu, 10 Oct 2024 10:45:52 +0000 (GMT) From: "Inbaraj E" To: "'Krzysztof Kozlowski'" , "'Stephen Boyd'" , , , , , , , Cc: , In-Reply-To: <2b3566dd-71ac-4ef7-abdc-524277879aa6@kernel.org> Subject: RE: [PATCH] clk: samsung: fsd: Mark PLL_CAM_CSI as critical Date: Thu, 10 Oct 2024 16:15:51 +0530 Message-ID: <08d001db1b01$94a9b9f0$bdfd2dd0$@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Mailer: Microsoft Outlook 16.0 Thread-Index: AQMYu0UT7KgXFJ9p8WqzYl/+4ytJPAKVNCMjAc9ECZkCVSVjTgGurbUsAUVIpqkCfYGRoQL0rVzSAfBMA4ivfAuNkA== Content-Language: en-in X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrJJsWRmVeSWpSXmKPExsWy7bCmhq7PRvZ0g+2feS0ezNvGZnH9y3NW i5sHdjJZnD+/gd3iY889VovLu+awWcw4v4/J4uIpV4tFW7+wWxx+085q8e/aRhYHbo/3N1rZ PTat6mTz6NuyitHj8ya5AJaobJuM1MSU1CKF1Lzk/JTMvHRbJe/geOd4UzMDQ11DSwtzJYW8 xNxUWyUXnwBdt8wcoKOUFMoSc0qBQgGJxcVK+nY2RfmlJakKGfnFJbZKqQUpOQUmBXrFibnF pXnpenmpJVaGBgZGpkCFCdkZf7d0MxVMVq64P8u/gfGLdBcjJ4eEgInEkR3dzF2MXBxCArsZ JWbMnMoC4XxilDhz5ykjhPONUWJ/22EmmJb9tyZDtexllNh5s58NwnnJKHFo3wZWkCo2AU2J m0f/gbWLCCxlkui894MdJMEsYCax5e59sCJOATuJDw0bwOLCAi4SM/5dAhrLwcEioCqxaIYL SJhXwFJi2uMTrBC2oMTJmU9YIMZoSyxb+JoZ4iIFiZ9Pl4HViAhkSRzb/ACqRlzi6M8esEsl BJZySKw/dIURosFF4tnBvVDNwhKvjm9hh7ClJD6/28sGYftI7J/zC6o+Q+LY9uWsELa9xIEr c1hA7mQGenL9Ln2IsKzE1FPrmCD28kn0/n4CDS1eiR3zYGxliZlH7kONl5TYeXknywRGpVlI XpuF5LVZSF6YhbBtASPLKkbJ1ILi3PTUYtMCw7zUcniEJ+fnbmIEp1ktzx2Mdx980DvEyMTB eIhRgoNZSYRXdyFruhBvSmJlVWpRfnxRaU5q8SFGU2BwT2SWEk3OByb6vJJ4QxNLAxMzMzMT S2MzQyVx3tetc1OEBNITS1KzU1MLUotg+pg4OKUamILybAIEvxXvVT4reuODm0y7413x3Osn 1nPFXvf/y+XfIVumy7tg+c15si0ll9i33tD9/aE3Vb/L6HB7Fatm/fUOPw+nXX4O7L80396+ wXO8iOurxJ6K/2uC9Ff8CmFyZ06Jzm3ZtUDwivLyShXD5ndriwV1vs37+zAiWcNJ+11CesAb vrO/snNmxti/iPDiz1rHJsSiP/mGMPORKIZoz+izzhwNmQHHv6kuOVImWnUn1qGkcrOy8pHQ gz9V010XPN4ueiZc9bPWgtv/vkU2MDj+fdVlLBYv77r/zPTtr9ts+Wfl9je+O1mRcmRH8gq/ yY7zF3B6/ZosVP3ESWLLle173wgkvy4oVOc4cWWJEktxRqKhFnNRcSIAZELxqDwEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprIIsWRmVeSWpSXmKPExsWy7bCSnG7SBvZ0g/urpCwezNvGZnH9y3NW i5sHdjJZnD+/gd3iY889VovLu+awWcw4v4/J4uIpV4tFW7+wWxx+085q8e/aRhYHbo/3N1rZ PTat6mTz6NuyitHj8ya5AJYoLpuU1JzMstQifbsErozfdwsLupUrLq7dxdbAeEO6i5GTQ0LA RGL/rcnMXYxcHEICuxkl/vz6wQiRkJSY/Xs6O4QtLLHy33N2iKLnjBITuyewgSTYBDQlbh79 xwiSEBFYyyTRsX0lWDezgIXE8j/X2SA6HjBL9P35DpbgFLCT+NCwAWyssICLxIx/l4B2c3Cw CKhKLJrhAhLmFbCUmPb4BCuELShxcuYTFoiZ2hK9D1sZYexlC18zQ1ynIPHz6TKwehGBLIlj mx9A1YtLHP3ZwzyBUXgWklGzkIyahWTULCQtCxhZVjFKphYU56bnJhsWGOallusVJ+YWl+al 6yXn525iBMealsYOxnvz/+kdYmTiYDzEKMHBrCTCq7uQNV2INyWxsiq1KD++qDQntfgQozQH i5I4r+GM2SlCAumJJanZqakFqUUwWSYOTqkGJse2a8ebvn6KK7/86AGXypZ0vv0H/uZw3dod XlZ/vE4x5pXQqxksnI9/6d+VZyoLvSN6w8xF+f6OBqd7nz8eyPQ7JappMu2eqKSlS3SwYv16 xkAFEecnLR8+GV7qC2ZZ8NblzfLUNRLZxbXCzEZ8LDtlNdpufnr8vS5x45/oy86Wjze/+HCD s73rbILD8U+dBXvsy/5f+GeywmtO/DvWX2lhbSdZ3S2uTin9yiXCufajvnzr9d7fC08Uf90y Izr4rGjGx5J/jusPNThe9eee9Pf00icPt28VO6Jx0ZRzg8qem7/PMK1/oO1/a9umD08d4mrr JGQO+qb0noyoN34sLPiDfRef6zKlw0K1pl6Py5VYijMSDbWYi4oTATGQXK8kAwAA X-CMS-MailID: 20241010104554epcas5p19fa883f33168b2742738e8edcf1f836a X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20240917101102epcas5p3b17d2774cb74fd4cf61ea52fde85c300 References: <20240917101016.23238-1-inbaraj.e@samsung.com> <0d43a00985a815c1869ebc6c441a2aed.sboyd@kernel.org> <00f001db0a87$cd9ddfa0$68d99ee0$@samsung.com> <633ff284-101d-4651-833e-a6b01626c9a1@kernel.org> <011401db0b13$cbd045f0$6370d1d0$@samsung.com> <1c6c56f7-bdda-4e14-9910-80e0cda0d631@kernel.org> <03ca01db13e3$bc12e360$3438aa20$@samsung.com> <2b3566dd-71ac-4ef7-abdc-524277879aa6@kernel.org> > -----Original Message----- > From: Krzysztof Kozlowski > Sent: 01 October 2024 15:30 > To: Inbaraj E ; 'Stephen Boyd' > ; alim.akhtar=40samsung.com; cw00.choi=40samsung.com; > linux-clk=40vger.kernel.org; linux-kernel=40vger.kernel.org; linux-samsun= g- > soc=40vger.kernel.org; mturquette=40baylibre.com; s.nawrocki=40samsung.co= m > Cc: pankaj.dubey=40samsung.com; gost.dev=40samsung.com > Subject: Re: =5BPATCH=5D clk: samsung: fsd: Mark PLL_CAM_CSI as critical >=20 > On 01/10/2024 11:24, Inbaraj E wrote: > >>>>>>>> CSI stop streaming through pm_runtime_put system is getting > >> halted. > >>>>>>>> So marking PLL_CAM_CSI as critical to prevent disabling. > >>>>>>>> > >>>>>>>> Signed-off-by: Inbaraj E > >>>>>>>> --- > >>>>>>> > >>>>>>> Please add a fixes tag. Although this is likely a band-aid fix > >>>>>>> because marking something critical leaves it enabled forever. > >>>>>> > >>>>>> Sure, will add fixes tag. As per HW manual, this PLL_CAM_CSI is > >>>>>> supplying clock even for CMU SFR access of CSI block, so we can't > >>>>>> gate this. > >>>>> > >>>>> Hm, I am not so sure. The CMU driver should just take appropriate > clock. > >>>>> Sprinkling CLK_CRITICAL looks as substitute of missing clock > >>>>> handling/ > >>>> > >>>> As per HW design, PLL_CAM_CSI is responsible for suppling clock to > >>>> CSI SFR, CMU SFR and some internal block of CAM_CSI. In this some > >>>> of the clock is not handled by any driver but it is required for > >>>> CSI to work properly. For example CSI NOC clock. So this is the > >>>> reason we are > >> marking PLL_CAM_CSI as critical. > >>>> > >>> > >>> This is clock hierarchy for CMU_CAM_CSI block. > >>> > >>> PLL_CAM_CSI -----> DIVIDER --------> CSI_SFR clock > >>> =7C > >>> =7C----> DIVIDER --------> CMU_SFR clock > >>> =7C > >>> =7C----> DIVIDER --------> CSI NOC clock. > >>> > >> > >> And what is the problem in adding proper handling in the driver? You > >> just described case valid for 99% of SoC components. > > > > Hi Kryzstof, > > > > Sorry, but it seems I was not able to explain the issue. Let me add > > more > > details: > > So for CSI IP we have two clocks as ACLK and PCLK which needs to be > > handled by the driver during start and stop streaming. > > > > In BLK_CSI we have CSI IP along with other bunch supporting modules > > such as CMU_CSI, NOC_CSI, CSI_SFR. For all these components of BLK_CSI > > we have a single top level parent PLL clock as PLL_CAM_CSI. > > > > Now if we look into CSI driver perspective it needs only ACLK and PCLK > > clocks for it's operations. But to access CMU SFRs (including > > ACLK/PCLK or any other CMU SFR of BLK_CSI) we need parent clock keep > > supplying clocks. While we try to gate ACLK clock, due to propagation > > logic of clock gating the CCF scans all the clocks from leaf level to > > the parent clock and tries to gate clocks if enable/disable ops is > > valid for any such clock. > > > > Issue here is that we are trying to gate PLL_CAM_CSI which itself is > > accessible only when this clock is enabled. In fact none of CMU_SFR > > will be accessible as soon as PLL_CAM_CSI is gated. CSI driver is not > > intended >=20 > Obviously, but your CMU is taking the necessary clock and enabled it so w= hat > is the problem? >=20 > > to gate this PLL clock but only the leaf level clock which is > > supplying to CSI IP. So in absence of any alternate source of clock > > hierarchy which can supply clock for CMU_CSI we can't gate PLL_CAM_CSI. > > > > Please let us know if you have any other queries why we are insisting > > on marking PLL_CAM_CSI as CRITICAL clock. >=20 > This is so far quite obvious - just like in all other cases, you need the= top clock > taken by proper driver. I don't think you are looking at right drivers an= d right > problem here. >=20 Hi Krzysztof, In this case, platform driver need to get this PLL clock and keep it enabled always. As PLL_CAM_CSI is source clock for accessing CMU registers of CSI block, and PLL_CAM_CSI itself lies in CSI_CMU, driver need to prepare and keep it enabled always. This way other PCLK and ACLK clocks can be gated. But the PLL_CAM_CSI which is parent of the PCLK and ACLK gate clock won't be disabled. Hope this should not be a concern.=20 Regards, Inbaraj E > Best regards, > Krzysztof