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Date:   Fri, 18 Nov 2022 16:51:00 +0000
From:   Paul Cercueil <paul@crapouillou.net>
Subject: Re: [PATCH] MIPS: DTS: CI20: fix reset line polarity of the ethernet
 controller
To:     Dmitry Torokhov <dmitry.torokhov@gmail.com>
Cc:     Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
        linux-mips@vger.kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org
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Hi Dmitry,

Le ven. 18 nov. 2022 =E0 08:43:47 -0800, Dmitry Torokhov=20
<dmitry.torokhov@gmail.com> a =E9crit :
> The reset line is called PWRST#, annotated as "active low" in the
> binding documentation, and is driven low and then high by the driver=20
> to
> reset the chip. However in device tree for CI20 board it was=20
> incorrectly
> marked as "active high". Fix it.
>=20
> Because (as far as I know) the ci20.dts is always built in the kernel=20
> I
> elected not to also add a quirk to gpiolib to force the polarity=20
> there.
>=20
> Fixes: db49ca38579d ("net: davicom: dm9000: switch to using gpiod=20
> API")
> Reported-by: Paul Cercueil <paul@crapouillou.net>
> Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>

Acked-by: Paul Cercueil <paul@crapouillou.net>

Thanks.

Cheers,
-Paul

> ---
>  arch/mips/boot/dts/ingenic/ci20.dts | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>=20
> diff --git a/arch/mips/boot/dts/ingenic/ci20.dts=20
> b/arch/mips/boot/dts/ingenic/ci20.dts
> index 37c46720c719..f38c39572a9e 100644
> --- a/arch/mips/boot/dts/ingenic/ci20.dts
> +++ b/arch/mips/boot/dts/ingenic/ci20.dts
> @@ -438,7 +438,7 @@ dm9000@6 {
>  		ingenic,nemc-tAW =3D <50>;
>  		ingenic,nemc-tSTRV =3D <100>;
>=20
> -		reset-gpios =3D <&gpf 12 GPIO_ACTIVE_HIGH>;
> +		reset-gpios =3D <&gpf 12 GPIO_ACTIVE_LOW>;
>  		vcc-supply =3D <&eth0_power>;
>=20
>  		interrupt-parent =3D <&gpe>;
> --
> 2.38.1.584.g0f3c55d4c2-goog
>=20
>=20
> --
> Dmitry