RE: [PATCH] PCI: exynos: Adapt to clk_bulk_* APIs

["Shradha Todi" <shradha.t@samsung.com>]

Gentle reminder to review this patch. Thanks in advance!

> -----Original Message-----
> From: Shradha Todi [mailto:shradha.t@samsung.com]
> Sent: 09 October 2023 11:52
> To: jingoohan1@gmail.com; lpieralisi@kernel.org; kw@linux.com;
> robh@kernel.org; bhelgaas@google.com; krzysztof.kozlowski@linaro.org;
> alim.akhtar@samsung.com
> Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> samsung-soc@vger.kernel.org; linux-kernel@vger.kernel.org;
> pankaj.dubey@samsung.com; Shradha Todi <shradha.t@samsung.com>
> Subject: [PATCH] PCI: exynos: Adapt to clk_bulk_* APIs
> 
> There is no need to hardcode the clock info in the driver as driver can rely on
> the devicetree to supply the clocks required for the functioning of the
> peripheral. Get rid of the static clock info and obtain the platform supplied
> clocks. The total number of clocks supplied is obtained using the
> devm_clk_bulk_get_all() API and used for the rest of the clk_bulk_* APIs.
> 
> Signed-off-by: Shradha Todi <shradha.t@samsung.com>
> ---
>  drivers/pci/controller/dwc/pci-exynos.c | 46 ++++++-------------------
>  1 file changed, 11 insertions(+), 35 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pci-exynos.c
> b/drivers/pci/controller/dwc/pci-exynos.c
> index 9e42cfcd99cc..023cf41fccd7 100644
> --- a/drivers/pci/controller/dwc/pci-exynos.c
> +++ b/drivers/pci/controller/dwc/pci-exynos.c
> @@ -54,8 +54,8 @@
>  struct exynos_pcie {
>  	struct dw_pcie			pci;
>  	void __iomem			*elbi_base;
> -	struct clk			*clk;
> -	struct clk			*bus_clk;
> +	struct clk_bulk_data		*clks;
> +	int				clk_cnt;
>  	struct phy			*phy;
>  	struct regulator_bulk_data	supplies[2];
>  };
> @@ -65,30 +65,18 @@ static int exynos_pcie_init_clk_resources(struct
> exynos_pcie *ep)
>  	struct device *dev = ep->pci.dev;
>  	int ret;
> 
> -	ret = clk_prepare_enable(ep->clk);
> -	if (ret) {
> -		dev_err(dev, "cannot enable pcie rc clock");
> +	ret = devm_clk_bulk_get_all(dev, &ep->clks);
> +	if (ret < 0)
>  		return ret;
> -	}
> 
> -	ret = clk_prepare_enable(ep->bus_clk);
> -	if (ret) {
> -		dev_err(dev, "cannot enable pcie bus clock");
> -		goto err_bus_clk;
> -	}
> +	ep->clk_cnt = ret;
> 
> -	return 0;
> -
> -err_bus_clk:
> -	clk_disable_unprepare(ep->clk);
> -
> -	return ret;
> +	return clk_bulk_prepare_enable(ep->clk_cnt, ep->clks);
>  }
> 
>  static void exynos_pcie_deinit_clk_resources(struct exynos_pcie *ep)  {
> -	clk_disable_unprepare(ep->bus_clk);
> -	clk_disable_unprepare(ep->clk);
> +	clk_bulk_disable_unprepare(ep->clk_cnt, ep->clks);
>  }
> 
>  static void exynos_pcie_writel(void __iomem *base, u32 val, u32 reg) @@ -
> 332,17 +320,9 @@ static int exynos_pcie_probe(struct platform_device
> *pdev)
>  	if (IS_ERR(ep->elbi_base))
>  		return PTR_ERR(ep->elbi_base);
> 
> -	ep->clk = devm_clk_get(dev, "pcie");
> -	if (IS_ERR(ep->clk)) {
> -		dev_err(dev, "Failed to get pcie rc clock\n");
> -		return PTR_ERR(ep->clk);
> -	}
> -
> -	ep->bus_clk = devm_clk_get(dev, "pcie_bus");
> -	if (IS_ERR(ep->bus_clk)) {
> -		dev_err(dev, "Failed to get pcie bus clock\n");
> -		return PTR_ERR(ep->bus_clk);
> -	}
> +	ret = exynos_pcie_init_clk_resources(ep);
> +	if (ret < 0)
> +		return ret;
> 
>  	ep->supplies[0].supply = "vdd18";
>  	ep->supplies[1].supply = "vdd10";
> @@ -351,10 +331,6 @@ static int exynos_pcie_probe(struct platform_device
> *pdev)
>  	if (ret)
>  		return ret;
> 
> -	ret = exynos_pcie_init_clk_resources(ep);
> -	if (ret)
> -		return ret;
> -
>  	ret = regulator_bulk_enable(ARRAY_SIZE(ep->supplies), ep-
> >supplies);
>  	if (ret)
>  		return ret;
> @@ -369,8 +345,8 @@ static int exynos_pcie_probe(struct platform_device
> *pdev)
> 
>  fail_probe:
>  	phy_exit(ep->phy);
> -	exynos_pcie_deinit_clk_resources(ep);
>  	regulator_bulk_disable(ARRAY_SIZE(ep->supplies), ep->supplies);
> +	exynos_pcie_deinit_clk_resources(ep);
> 
>  	return ret;
>  }
> --
> 2.17.1