From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 25775244671 for ; Thu, 27 Nov 2025 00:49:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764204586; cv=none; b=FOONuncLzpeFtclX+lQc8q+O/9s9gb7bjxgiq4NNXdBsFHaZd0gwWopY1OfGkyrePrDJgKb4G6gD+O+Ro/1hhK5aDRDZ6RWHC4GFDP4Ow6+mNzpyB724vgKTBilVKVqLUb0uPBQyFeXdfxii+om7M/K6Dksho6qnaFf+ACLlfgc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764204586; c=relaxed/simple; bh=wS8EVxR6YX2P5yfvi9alZyf7r7Sl51mfZ6kFOeOmBmI=; h=Date:From:To:cc:Subject:In-Reply-To:Message-ID:References: MIME-Version:Content-Type; b=k9ZJs3Rq8hahgo6fDd+z68lC3dGUtJWqf6UX29ge2vidQ4wR1bYJaW+v2Tsgg3GVSfG+lKt08OHgCGaF0qBnCZmo5wYjSaEPsw2LJIJ58ZgvsPgjQqaEv4+hhvodtqzTP8e5rRhN6xDFtZiQWgv3ZU4BmUqhT/BshwAIexzUEBI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=rXPYIhkl; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="rXPYIhkl" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4B885C4CEF7; Thu, 27 Nov 2025 00:49:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1764204585; bh=wS8EVxR6YX2P5yfvi9alZyf7r7Sl51mfZ6kFOeOmBmI=; h=Date:From:To:cc:Subject:In-Reply-To:References:From; b=rXPYIhklTxIiLyCDyhxyeHHU5ZBJjqxgbp8nS/Iu0fF5lJv8kW9QKfTKOkP1qbTsL zSOL6s9vJZ78fvpYVbJoOzwvH35EIBkpsK8MhEPFK6AwT1/iuG2nl8/ENOjtTT/bL/ ybJjF3LsTiubj5CidvjIV2VZxxkT++qZ1pQaAIdob/XyoeFEtws+SFMKATCZtutZxR BQa6j6amENy0VDu1G7rGMiD/qFfn+xeEfC4pQxJzh/6WbUuJjyPiJlFkn09N5TIHno 5n2/ps6A+i8UyMO2KOl7CVrc0EAao10ZKfPPO3NqB2jIPWDbi3J6K9hKdkCP+vJ77v HII24ulEsng0A== Date: Wed, 26 Nov 2025 17:49:43 -0700 (MST) From: Paul Walmsley To: Himanshu Chauhan cc: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v1 2/2] riscv: Introduce support for hardware break/watchpoints In-Reply-To: <20250710125231.653967-3-hchauhan@ventanamicro.com> Message-ID: <0b77ac0f-a18f-e577-ff92-98ddd1d2bed8@kernel.org> References: <20250710125231.653967-1-hchauhan@ventanamicro.com> <20250710125231.653967-3-hchauhan@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII On Thu, 10 Jul 2025, Himanshu Chauhan wrote: > RISC-V hardware breakpoint framework is built on top of perf subsystem > and uses SBI debug trigger extension to > install/uninstall/update/enable/disable hardware triggers as specified > in Sdtrig ISA extension. > > Signed-off-by: Himanshu Chauhan Talking with Anup, it sounds like you're planning an updated version of this one, so will hold off on it. - Paul