From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 73A41361DD2 for ; Fri, 10 Jul 2026 06:37:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783665437; cv=none; b=OTIfu/Oy2H5FBLDXN/BG+kN656j97oEiAXpe81jWXRrg57DKwCw1YXxo4xW5GMxrJBR/+AZdMoFNJzm0PxVsrMTKIQjdCDhci2+JuRtmiaowhRSL7K9ou0wjL7SLmVPWRemv/8x0NBs6wjnxC2S8md3FACAswq6Hz3hN10WmDj4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783665437; c=relaxed/simple; bh=/zKyv+msrbfJ3fiX/4tO4JJVUdgC29fJ+C78w2qqgJM=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=d4ItihZ4mWny9LB9sEy9J61CzfhohANGBT+9QUlz2DqXIgUAGqGuHwQ8yjUEgb9+43rDaQB9L6FwTWESZiJ/dlWgJgWen3e5u296XDd63rn7jlDgp0LHO1dpOklFCtbHwXcoMCuhhpItFT4qaR2BBCPq10vMl7B04oZezCHAgSQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=TjABRsuy; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="TjABRsuy" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6ED7D168F; Thu, 9 Jul 2026 23:37:11 -0700 (PDT) Received: from [10.174.42.251] (unknown [10.174.42.251]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id DC5563F66F; Thu, 9 Jul 2026 23:37:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1783665435; bh=/zKyv+msrbfJ3fiX/4tO4JJVUdgC29fJ+C78w2qqgJM=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=TjABRsuySFp6zdh8eFUea58VWg0eEBKR3x2Syp15M7bDIUbhcSs3rP6c2JkYC2wvO 71WFTNQ95ERHwdkeSzDH00QRhiAqLYfsQD5ha1YOgHvtNAViCIxxJH3joqzNRh5ZV3 Fmz9BT8RmNrR2O9m2ubghzzax7qIPgYWsms+v8gA= Message-ID: <0c34971d-7243-4e29-9bf7-aa36707b207e@arm.com> Date: Fri, 10 Jul 2026 12:07:09 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/6] arm64: cputype: Add Cortex-A520AE definitions To: Linu Cherian , Catalin Marinas , Will Deacon , Ryan Roberts , Kevin Brodsky , Suzuki K Poulose , Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20260708144331.679816-1-linu.cherian@arm.com> <20260708144331.679816-2-linu.cherian@arm.com> Content-Language: en-US From: Anshuman Khandual In-Reply-To: <20260708144331.679816-2-linu.cherian@arm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 08/07/26 8:13 PM, Linu Cherian wrote: > Add cputype definitions for Cortex-A520AE. > > The definition can be found in Cortex-A520AE TRM, > https://developer.arm.com/documentation/107726/0001/ > as part of MIDR_EL1 bit descriptions. > > This is going to be used in the bbml3 support list. > > Signed-off-by: Linu Cherian > --- > arch/arm64/include/asm/cputype.h | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h > index 1b9f0cda1336..e41fae46426b 100644 > --- a/arch/arm64/include/asm/cputype.h > +++ b/arch/arm64/include/asm/cputype.h > @@ -82,6 +82,7 @@ > #define ARM_CPU_PART_CORTEX_X1 0xD44 > #define ARM_CPU_PART_CORTEX_A510 0xD46 > #define ARM_CPU_PART_CORTEX_A520 0xD80 > +#define ARM_CPU_PART_CORTEX_A520AE 0xD88 > #define ARM_CPU_PART_CORTEX_A710 0xD47 > #define ARM_CPU_PART_CORTEX_A715 0xD4D > #define ARM_CPU_PART_CORTEX_X2 0xD48 > @@ -176,6 +177,7 @@ > #define MIDR_CORTEX_X1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1) > #define MIDR_CORTEX_A510 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A510) > #define MIDR_CORTEX_A520 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A520) > +#define MIDR_CORTEX_A520AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A520AE) > #define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710) > #define MIDR_CORTEX_A715 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A715) > #define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2) Reviewed-by: Anshuman Khandual