From: Wojciech Drewek <wojciech.drewek@intel.com>
To: Jijie Shao <shaojijie@huawei.com>, <yisen.zhuang@huawei.com>,
<salil.mehta@huawei.com>, <davem@davemloft.net>,
<edumazet@google.com>, <kuba@kernel.org>, <pabeni@redhat.com>
Cc: <shenjian15@huawei.com>, <wangjie125@huawei.com>,
<liuyonglong@huawei.com>, <netdev@vger.kernel.org>,
<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH V2 net-next] net: hns3: add some link modes for hisilicon device
Date: Tue, 24 Oct 2023 11:48:09 +0200 [thread overview]
Message-ID: <0c432d17-cfdf-45ff-b9e2-99de17c01ddd@intel.com> (raw)
In-Reply-To: <20231024032034.417509-1-shaojijie@huawei.com>
On 24.10.2023 05:20, Jijie Shao wrote:
> From: Hao Chen <chenhao418@huawei.com>
>
> Add HCLGE_SUPPORT_50G_R1_BIT and HCLGE_SUPPORT_100G_R2_BIT two
> capability bits and Corresponding link modes.
>
> Signed-off-by: Hao Chen <chenhao418@huawei.com>
> Signed-off-by: Jijie Shao <shaojijie@huawei.com>
> ---
> ChangeLog:
> 1. Change "bit_map" to "bmap" to shorten the variable name length,
> suggested by Drewek, Wojciech
> v1: https://lore.kernel.org/all/20231023010836.507078-1-shaojijie@huawei.com/
Thanks!
Reviewed-by: Wojciech Drewek <wojciech.drewek@intel.com>
> ---
> .../hisilicon/hns3/hns3pf/hclge_main.c | 158 +++++++++---------
> .../hisilicon/hns3/hns3pf/hclge_main.h | 16 +-
> 2 files changed, 92 insertions(+), 82 deletions(-)
>
> diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
> index 99c0576e6383..66e5807903a0 100644
> --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
> +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
> @@ -881,8 +881,8 @@ static const struct hclge_speed_bit_map speed_bit_map[] = {
> {HCLGE_MAC_SPEED_10G, HCLGE_SUPPORT_10G_BIT},
> {HCLGE_MAC_SPEED_25G, HCLGE_SUPPORT_25G_BIT},
> {HCLGE_MAC_SPEED_40G, HCLGE_SUPPORT_40G_BIT},
> - {HCLGE_MAC_SPEED_50G, HCLGE_SUPPORT_50G_BIT},
> - {HCLGE_MAC_SPEED_100G, HCLGE_SUPPORT_100G_BIT},
> + {HCLGE_MAC_SPEED_50G, HCLGE_SUPPORT_50G_BITS},
> + {HCLGE_MAC_SPEED_100G, HCLGE_SUPPORT_100G_BITS},
> {HCLGE_MAC_SPEED_200G, HCLGE_SUPPORT_200G_BIT},
> };
>
> @@ -939,100 +939,98 @@ static void hclge_update_fec_support(struct hclge_mac *mac)
> mac->supported);
> }
>
> +static const struct hclge_link_mode_bmap hclge_sr_link_mode_bmap[8] = {
> + {HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseSR_Full_BIT},
> + {HCLGE_SUPPORT_25G_BIT, ETHTOOL_LINK_MODE_25000baseSR_Full_BIT},
> + {HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT},
> + {HCLGE_SUPPORT_50G_R2_BIT, ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT},
> + {HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseSR_Full_BIT},
> + {HCLGE_SUPPORT_100G_R4_BIT, ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT},
> + {HCLGE_SUPPORT_100G_R2_BIT, ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT},
> + {HCLGE_SUPPORT_200G_BIT, ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT},
> +};
> +
> +static const struct hclge_link_mode_bmap hclge_lr_link_mode_bmap[6] = {
> + {HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseLR_Full_BIT},
> + {HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT},
> + {HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT},
> + {HCLGE_SUPPORT_100G_R4_BIT,
> + ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT},
> + {HCLGE_SUPPORT_100G_R2_BIT,
> + ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT},
> + {HCLGE_SUPPORT_200G_BIT,
> + ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT},
> +};
> +
> +static const struct hclge_link_mode_bmap hclge_cr_link_mode_bmap[8] = {
> + {HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseCR_Full_BIT},
> + {HCLGE_SUPPORT_25G_BIT, ETHTOOL_LINK_MODE_25000baseCR_Full_BIT},
> + {HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT},
> + {HCLGE_SUPPORT_50G_R2_BIT, ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT},
> + {HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseCR_Full_BIT},
> + {HCLGE_SUPPORT_100G_R4_BIT, ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT},
> + {HCLGE_SUPPORT_100G_R2_BIT, ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT},
> + {HCLGE_SUPPORT_200G_BIT, ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT},
> +};
> +
> +static const struct hclge_link_mode_bmap hclge_kr_link_mode_bmap[9] = {
> + {HCLGE_SUPPORT_1G_BIT, ETHTOOL_LINK_MODE_1000baseKX_Full_BIT},
> + {HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseKR_Full_BIT},
> + {HCLGE_SUPPORT_25G_BIT, ETHTOOL_LINK_MODE_25000baseKR_Full_BIT},
> + {HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT},
> + {HCLGE_SUPPORT_50G_R2_BIT, ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT},
> + {HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseKR_Full_BIT},
> + {HCLGE_SUPPORT_100G_R4_BIT, ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT},
> + {HCLGE_SUPPORT_100G_R2_BIT, ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT},
> + {HCLGE_SUPPORT_200G_BIT, ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT},
> +};
> +
> static void hclge_convert_setting_sr(u16 speed_ability,
> unsigned long *link_mode)
> {
> - if (speed_ability & HCLGE_SUPPORT_10G_BIT)
> - linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
> - link_mode);
> - if (speed_ability & HCLGE_SUPPORT_25G_BIT)
> - linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
> - link_mode);
> - if (speed_ability & HCLGE_SUPPORT_40G_BIT)
> - linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
> - link_mode);
> - if (speed_ability & HCLGE_SUPPORT_50G_BIT)
> - linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
> - link_mode);
> - if (speed_ability & HCLGE_SUPPORT_100G_BIT)
> - linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
> - link_mode);
> - if (speed_ability & HCLGE_SUPPORT_200G_BIT)
> - linkmode_set_bit(ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT,
> - link_mode);
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(hclge_sr_link_mode_bmap); i++) {
> + if (speed_ability & hclge_sr_link_mode_bmap[i].support_bit)
> + linkmode_set_bit(hclge_sr_link_mode_bmap[i].link_mode,
> + link_mode);
> + }
> }
>
> static void hclge_convert_setting_lr(u16 speed_ability,
> unsigned long *link_mode)
> {
> - if (speed_ability & HCLGE_SUPPORT_10G_BIT)
> - linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
> - link_mode);
> - if (speed_ability & HCLGE_SUPPORT_25G_BIT)
> - linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
> - link_mode);
> - if (speed_ability & HCLGE_SUPPORT_50G_BIT)
> - linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT,
> - link_mode);
> - if (speed_ability & HCLGE_SUPPORT_40G_BIT)
> - linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
> - link_mode);
> - if (speed_ability & HCLGE_SUPPORT_100G_BIT)
> - linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
> - link_mode);
> - if (speed_ability & HCLGE_SUPPORT_200G_BIT)
> - linkmode_set_bit(
> - ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT,
> - link_mode);
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(hclge_lr_link_mode_bmap); i++) {
> + if (speed_ability & hclge_lr_link_mode_bmap[i].support_bit)
> + linkmode_set_bit(hclge_lr_link_mode_bmap[i].link_mode,
> + link_mode);
> + }
> }
>
> static void hclge_convert_setting_cr(u16 speed_ability,
> unsigned long *link_mode)
> {
> - if (speed_ability & HCLGE_SUPPORT_10G_BIT)
> - linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseCR_Full_BIT,
> - link_mode);
> - if (speed_ability & HCLGE_SUPPORT_25G_BIT)
> - linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
> - link_mode);
> - if (speed_ability & HCLGE_SUPPORT_40G_BIT)
> - linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
> - link_mode);
> - if (speed_ability & HCLGE_SUPPORT_50G_BIT)
> - linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
> - link_mode);
> - if (speed_ability & HCLGE_SUPPORT_100G_BIT)
> - linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
> - link_mode);
> - if (speed_ability & HCLGE_SUPPORT_200G_BIT)
> - linkmode_set_bit(ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT,
> - link_mode);
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(hclge_cr_link_mode_bmap); i++) {
> + if (speed_ability & hclge_cr_link_mode_bmap[i].support_bit)
> + linkmode_set_bit(hclge_cr_link_mode_bmap[i].link_mode,
> + link_mode);
> + }
> }
>
> static void hclge_convert_setting_kr(u16 speed_ability,
> unsigned long *link_mode)
> {
> - if (speed_ability & HCLGE_SUPPORT_1G_BIT)
> - linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
> - link_mode);
> - if (speed_ability & HCLGE_SUPPORT_10G_BIT)
> - linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
> - link_mode);
> - if (speed_ability & HCLGE_SUPPORT_25G_BIT)
> - linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
> - link_mode);
> - if (speed_ability & HCLGE_SUPPORT_40G_BIT)
> - linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
> - link_mode);
> - if (speed_ability & HCLGE_SUPPORT_50G_BIT)
> - linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
> - link_mode);
> - if (speed_ability & HCLGE_SUPPORT_100G_BIT)
> - linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
> - link_mode);
> - if (speed_ability & HCLGE_SUPPORT_200G_BIT)
> - linkmode_set_bit(ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT,
> - link_mode);
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(hclge_kr_link_mode_bmap); i++) {
> + if (speed_ability & hclge_kr_link_mode_bmap[i].support_bit)
> + linkmode_set_bit(hclge_kr_link_mode_bmap[i].link_mode,
> + link_mode);
> + }
> }
>
> static void hclge_convert_setting_fec(struct hclge_mac *mac)
> @@ -1158,10 +1156,10 @@ static u32 hclge_get_max_speed(u16 speed_ability)
> if (speed_ability & HCLGE_SUPPORT_200G_BIT)
> return HCLGE_MAC_SPEED_200G;
>
> - if (speed_ability & HCLGE_SUPPORT_100G_BIT)
> + if (speed_ability & HCLGE_SUPPORT_100G_BITS)
> return HCLGE_MAC_SPEED_100G;
>
> - if (speed_ability & HCLGE_SUPPORT_50G_BIT)
> + if (speed_ability & HCLGE_SUPPORT_50G_BITS)
> return HCLGE_MAC_SPEED_50G;
>
> if (speed_ability & HCLGE_SUPPORT_40G_BIT)
> diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
> index 02c7aab3546e..51979cf71262 100644
> --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
> +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
> @@ -185,15 +185,22 @@ enum HLCGE_PORT_TYPE {
> #define HCLGE_SUPPORT_1G_BIT BIT(0)
> #define HCLGE_SUPPORT_10G_BIT BIT(1)
> #define HCLGE_SUPPORT_25G_BIT BIT(2)
> -#define HCLGE_SUPPORT_50G_BIT BIT(3)
> -#define HCLGE_SUPPORT_100G_BIT BIT(4)
> +#define HCLGE_SUPPORT_50G_R2_BIT BIT(3)
> +#define HCLGE_SUPPORT_100G_R4_BIT BIT(4)
> /* to be compatible with exsit board */
> #define HCLGE_SUPPORT_40G_BIT BIT(5)
> #define HCLGE_SUPPORT_100M_BIT BIT(6)
> #define HCLGE_SUPPORT_10M_BIT BIT(7)
> #define HCLGE_SUPPORT_200G_BIT BIT(8)
> +#define HCLGE_SUPPORT_50G_R1_BIT BIT(9)
> +#define HCLGE_SUPPORT_100G_R2_BIT BIT(10)
> +
> #define HCLGE_SUPPORT_GE \
> (HCLGE_SUPPORT_1G_BIT | HCLGE_SUPPORT_100M_BIT | HCLGE_SUPPORT_10M_BIT)
> +#define HCLGE_SUPPORT_50G_BITS \
> + (HCLGE_SUPPORT_50G_R2_BIT | HCLGE_SUPPORT_50G_R1_BIT)
> +#define HCLGE_SUPPORT_100G_BITS \
> + (HCLGE_SUPPORT_100G_R4_BIT | HCLGE_SUPPORT_100G_R2_BIT)
>
> enum HCLGE_DEV_STATE {
> HCLGE_STATE_REINITING,
> @@ -1076,6 +1083,11 @@ struct hclge_mac_speed_map {
> u32 speed_fw; /* speed defined in firmware */
> };
>
> +struct hclge_link_mode_bmap {
> + u16 support_bit;
> + enum ethtool_link_mode_bit_indices link_mode;
> +};
> +
> int hclge_set_vport_promisc_mode(struct hclge_vport *vport, bool en_uc_pmc,
> bool en_mc_pmc, bool en_bc_pmc);
> int hclge_add_uc_addr_common(struct hclge_vport *vport,
next prev parent reply other threads:[~2023-10-24 9:48 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-24 3:20 [PATCH V2 net-next] net: hns3: add some link modes for hisilicon device Jijie Shao
2023-10-24 9:48 ` Wojciech Drewek [this message]
2023-10-25 8:30 ` patchwork-bot+netdevbpf
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