From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4969528D854; Tue, 22 Jul 2025 09:19:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753175948; cv=none; b=qBivbAwqWE4FjNRulxO7wV5VVRPPt80pUBDMXC6eooGMMS2H23W8rU3fjTfGo45dsxf47/fcdnikIadxcfq8iBuNhJfWuwpspg6BrmWg6ZbvnJDTaA7XVvbVVkiOuMcA3bCKr0daJMnmeK5qKzFLBEZWy6nADM9cYBGOj7+LgKI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753175948; c=relaxed/simple; bh=5lRPv2f/qyW3DqGyiltC1DhUAYkoI/BAX4G5BcSjXKg=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=Yv9aTcT9DmEiLO9K4H0kmkMmGSNn4fh41Tbep/wqfm1YquH81Gtl3TfVUXnm1/ei5mvlC5E43vX6fJRZ9R315EQb4iI8x3vVVNHS3AJ6ZTENxKEPHnvwNAIgHvkNNCZrrfRU4LzwD03IbCH4jEtB2dlCeqoIx9Z34oniIly0xvs= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=KJBgUbzu; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="KJBgUbzu" Received: by smtp.kernel.org (Postfix) with ESMTPSA id CA66DC4CEEB; Tue, 22 Jul 2025 09:19:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1753175947; bh=5lRPv2f/qyW3DqGyiltC1DhUAYkoI/BAX4G5BcSjXKg=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=KJBgUbzuv3sf8jL/JvhMOe5M95a4a4ETaRYi/72QkcP7RbfhXq+81NSf78vYqbGYu IB+n463y6TCxEyejBDX+mmibKVCHw5f3ES6K8eYf+vCRlmyt87mT1AjGRJXlbTVGH7 nfcMYLZmtfJw42Y1M6wcHH2vFZuKTtUChy7pUlBeMmkT1y1Bizxa470AV/U54AQqlr 2eOAWJtWHujITd+zeIAm6RJYJz3N8QHvCibHiV44HfyLzKMrVCfNeEYtEKPI4qixFj ErBLVB1IqqZ+KT71bSrS+dh/gUfopO3uluKYZW3IhEwDIYa3SnZlhsp5zFtIt8F3yK kpjJ670cdZROg== Message-ID: <0c94206c-f70f-4bed-81ec-bb2870748121@kernel.org> Date: Tue, 22 Jul 2025 11:18:59 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 02/13] dt-bindings: phy: Add binding for QCS615 standalone QMP DP PHY To: Xiangxu Yin , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Vinod Koul , Kishon Vijay Abraham I Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, dmitry.baryshkov@oss.qualcomm.com, konrad.dybcio@oss.qualcomm.com, fange.zhang@oss.qualcomm.com, quic_lliu6@quicinc.com, quic_yongmou@quicinc.com References: <20250722-add-displayport-support-for-qcs615-platform-v2-0-42b4037171f8@oss.qualcomm.com> <20250722-add-displayport-support-for-qcs615-platform-v2-2-42b4037171f8@oss.qualcomm.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 22/07/2025 09:22, Xiangxu Yin wrote: > Introduce device tree binding documentation for the Qualcomm QMP DP PHY > on QCS615 SoCs. This PHY supports DisplayPort functionality and is > designed to operate independently from the USB3 PHY. A nit, subject: drop second/last, redundant "binding for". The "dt-bindings" prefix is already stating that these are bindings. See also: https://elixir.bootlin.com/linux/v6.7-rc8/source/Documentation/devicetree/bindings/submitting-patches.rst#L18 > > Unlike combo PHYs found on other platforms, the QCS615 DP PHY is > standalone and does not support USB/DP multiplexing. The binding > describes the required clocks, resets, TCSR configuration, and clock/PHY > cells for proper integration. > > Signed-off-by: Xiangxu Yin > --- > .../bindings/phy/qcom,qcs615-qmp-dp-phy.yaml | 111 +++++++++++++++++++++ > 1 file changed, 111 insertions(+) > > diff --git a/Documentation/devicetree/bindings/phy/qcom,qcs615-qmp-dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qcs615-qmp-dp-phy.yaml > new file mode 100644 > index 0000000000000000000000000000000000000000..17e37c1df7b61dc2f7aa35ee106fd94ee2829c5f > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/qcom,qcs615-qmp-dp-phy.yaml > @@ -0,0 +1,111 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/qcom,qcs615-qmp-dp-phy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm QMP PHY controller (DP, QCS615) That's too vague title. You are not adding here Qualcomm QMP PHY controllers. > + > +maintainers: > + - Vinod Koul Hm? Why? > + > +description: > + The QMP DP PHY controller supports DisplayPort physical layer functionality > + on Qualcomm QCS615 SoCs. This PHY is independent from USB3 PHY and does not > + support combo mode. > + > +properties: > + compatible: > + enum: > + - qcom,qcs615-qmp-dp-phy > + > + reg: > + maxItems: 4 I don't understand what you are doing here. Why previous patch evolved into this? Where is any reasoning for that in the changelog? You said: "- Add new binding qcom,qcs615-qmp-dp-phy.yaml for QCS615 standalone DP [Krzysztof]" but you must say WHY you are doing things... Anyway, missing constraints. Look at other Qualcomm bindings. > + > + clocks: > + maxItems: 2 > + > + clock-names: > + items: > + - const: cfg_ahb > + - const: ref > + > + clock-output-names: > + maxItems: 2 > + description: > + Names of the clocks provided by the PHY. Drop description, redundant. It cannot be anything else. > + > + qcom,tcsr-reg: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + items: > + - items: > + - description: phandle to TCSR hardware block > + - description: offset of the DP PHY moode register > + description: > + DP PHY moode register present in the TCSR > + > + resets: > + maxItems: 1 > + > + reset-names: > + items: > + - const: phy Drop reset-names, useless. > + > + vdda-phy-supply: true > + > + vdda-pll-supply: true > + > + "#clock-cells": > + const: 1 > + description: > + See include/dt-bindings/phy/phy-qcom-qmp.h > + > + "#phy-cells": > + const: 1 > + description: > + See include/dt-bindings/phy/phy-qcom-qmp.h > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - clock-output-names > + - qcom,tcsr-reg > + - resets > + - reset-names > + - vdda-phy-supply > + - vdda-pll-supply > + - "#clock-cells" > + - "#phy-cells" > + Why introducing completely different order? See existing binding and DTS coding style. Best regards, Krzysztof