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X-CSE-ConnectionGUID: ZnI6j48cQhGDKHHoL/iyLQ== X-CSE-MsgGUID: LQzlAj0nRhGPVijvX7+ltw== X-IronPort-AV: E=McAfee;i="6800,10657,11625"; a="66367231" X-IronPort-AV: E=Sophos;i="6.20,228,1758610800"; d="scan'208";a="66367231" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Nov 2025 06:20:23 -0800 X-CSE-ConnectionGUID: moZAwUExTIyXcVvVxcwLNQ== X-CSE-MsgGUID: koXGbNzLRI+ZwD7wT/lxIg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.20,228,1758610800"; d="scan'208";a="192838956" Received: from lfiedoro-mobl.ger.corp.intel.com (HELO localhost) ([10.245.246.1]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Nov 2025 06:20:17 -0800 From: Jani Nikula To: Yaroslav Bolyukin , Ville =?utf-8?B?U3lyasOkbMOk?= , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter Cc: Harry Wentland , Leo Li , Rodrigo Siqueira , Alex Deucher , Christian =?utf-8?Q?K=C3=B6nig?= , Wayne Lin , amd-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Yaroslav Bolyukin Subject: Re: [PATCH v6 5/7] drm/edid: for consistency, use mask everywhere for block rev parsing In-Reply-To: <20251126065126.54016-6-iam@lach.pw> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo References: <20251126065126.54016-1-iam@lach.pw> <20251126065126.54016-6-iam@lach.pw> Date: Wed, 26 Nov 2025 16:20:14 +0200 Message-ID: <0c963fb035a157c4094ba7410d4787697cd95699@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On Wed, 26 Nov 2025, Yaroslav Bolyukin wrote: Commit message goes here. > Signed-off-by: Yaroslav Bolyukin > --- > drivers/gpu/drm/drm_displayid_internal.h | 1 + > drivers/gpu/drm/drm_edid.c | 3 ++- > 2 files changed, 3 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/drm_displayid_internal.h b/drivers/gpu/drm/drm_displayid_internal.h > index 724174b429f2..55f972d32847 100644 > --- a/drivers/gpu/drm/drm_displayid_internal.h > +++ b/drivers/gpu/drm/drm_displayid_internal.h > @@ -139,6 +139,7 @@ struct displayid_formula_timings_9 { > u8 vrefresh; > } __packed; > > +#define DISPLAYID_BLOCK_DESCRIPTOR_PAYLOAD_BYTES GENMASK(6, 4) > struct displayid_formula_timing_block { > struct displayid_block base; > struct displayid_formula_timings_9 timings[]; > diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c > index 72a94b1713e2..7bdc99d5084a 100644 > --- a/drivers/gpu/drm/drm_edid.c > +++ b/drivers/gpu/drm/drm_edid.c > @@ -6906,7 +6906,8 @@ static int add_displayid_formula_modes(struct drm_connector *connector, > struct drm_display_mode *newmode; > int num_modes = 0; > bool type_10 = block->tag == DATA_BLOCK_2_TYPE_10_FORMULA_TIMING; > - int timing_size = 6 + ((formula_block->base.rev & 0x70) >> 4); > + int timing_size = 6 + > + FIELD_GET(DISPLAYID_BLOCK_DESCRIPTOR_PAYLOAD_BYTES, formula_block->base.rev); > > /* extended blocks are not supported yet */ > if (timing_size != 6) -- Jani Nikula, Intel