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charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.54.3 (3.54.3-1.fc41) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Sender: riel@surriel.com On Sat, 2025-05-17 at 09:59 +0200, Ingo Molnar wrote: >=20 > CONFIG_X86_TLB_BROADCAST_TLB_FLUSH doesn't actually exist, the name > is=20 > CONFIG_BROADCAST_TLB_FLUSH. >=20 Argh, cut'n'pasted from the wrong tree :( >=20 > we could make this a more obvious: >=20 > And we can drop the ugly & fragile type cast in > invalidate_user_asid(): >=20 > - __set_bit(kern_pcid(asid), > - =C2=A0 (unsigned long > *)this_cpu_ptr(&cpu_tlbstate.user_pcid_flush_mask)); >=20 > + __set_bit(kern_pcid(asid), > this_cpu_ptr(cpu_tlbstate.user_pcid_flush_mask)); >=20 That is a really nice improvement, and it almost works, too ;) In file included from ./arch/x86/include/asm/bitops.h:430, from ./include/linux/bitops.h:68: ./include/asm-generic/bitops/instrumented-non-atomic.h:26:54: note: expected =E2=80=98volatile long unsigned int *=E2=80=99 but argument is of = type =E2=80=98long unsigned int (*)[32]=E2=80=99 26 | ___set_bit(unsigned long nr, volatile unsigned long *addr) | ~~~~~~~~~~~~~~~~~~~~~~~~^~~~ I ended up settling for this: __set_bit(kern_pcid(asid), this_cpu_ptr(&cpu_tlbstate.user_pcid_flush_mask[0])); > 3) >=20 > If we are going to grow user_pcid_flush_mask from 2 bytes to 256 > bytes=20 > then please reorder 'struct tlb_state' for cache efficiency: at > minimum=20 > the ::cr4 shadow should move to before ::user_pcid_flush_mask. But I=20 > think we should probably move user_pcid_flush_mask to the end of the=20 > structure, where it does the least damage to cache layout. Done. V2 to follow in another email. Thank you! --=20 All Rights Reversed.