From: Siddharth Vadapalli <s-vadapalli@ti.com>
To: Chintan Vankar <c-vankar@ti.com>
Cc: Andrew Davis <afd@ti.com>, Peter Rosin <peda@axentia.se>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Conor Dooley <conor+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Rob Herring <robh+dt@kernel.org>, Tero Kristo <kristo@kernel.org>,
Vignesh Raghavendra <vigneshr@ti.com>, Nishanth Menon <nm@ti.com>,
<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>, <srk@ti.com>,
<r-gunasekaran@ti.com>, <danishanwar@ti.com>,
<s-vadapalli@ti.com>
Subject: Re: [PATCH v3 2/5] arm64: dts: ti: k3-j784s4-main: Add CPSW2G and CPSW9G nodes
Date: Thu, 25 Jan 2024 17:33:45 +0530 [thread overview]
Message-ID: <0db57065-b48a-4c63-8ad3-45af2924a3cb@ti.com> (raw)
In-Reply-To: <20240125100501.4137977-3-c-vankar@ti.com>
Hello Chintan,
On 25/01/24 15:34, Chintan Vankar wrote:
> From: Siddharth Vadapalli <s-vadapalli@ti.com>
>
...
>
> + main_cpsw0: ethernet@c000000 {
> + compatible = "ti,j784s4-cpswxg-nuss";
> + reg = <0x00 0xc000000 0x00 0x200000>;
> + reg-names = "cpsw_nuss";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges = <0x00 0x00 0x00 0xc000000 0x00 0x200000>;
> + dma-coherent;
> + clocks = <&k3_clks 64 0>;
> + clock-names = "fck";
> + power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
> +
> + dmas = <&main_udmap 0xca00>,
> + <&main_udmap 0xca01>,
> + <&main_udmap 0xca02>,
> + <&main_udmap 0xca03>,
> + <&main_udmap 0xca04>,
> + <&main_udmap 0xca05>,
> + <&main_udmap 0xca06>,
> + <&main_udmap 0xca07>,
> + <&main_udmap 0x4a00>;
> + dma-names = "tx0", "tx1", "tx2", "tx3",
> + "tx4", "tx5", "tx6", "tx7",
> + "rx";
> +
> + status = "disabled";
> +
> + ethernet-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + main_cpsw0_port1: port@1 {
> + reg = <1>;
> + label = "port1";
> + ti,mac-only;
> + status = "disabled";
> + };
> +
> + main_cpsw0_port2: port@2 {
> + reg = <2>;
> + label = "port2";
> + ti,mac-only;
> + status = "disabled";
> + };
> +
> + main_cpsw0_port3: port@3 {
> + reg = <3>;
> + label = "port3";
> + ti,mac-only;
> + status = "disabled";
> + };
> +
> + main_cpsw0_port4: port@4 {
> + reg = <4>;
> + label = "port4";
> + ti,mac-only;
> + status = "disabled";
> + };
> +
> + main_cpsw0_port5: port@5 {
> + reg = <5>;
> + label = "port5";
Please add the "ti,mac-only" property here and in the following 3 nodes as well
to keep it consistent.
> + status = "disabled";
> + };
> +
> + main_cpsw0_port6: port@6 {
> + reg = <6>;
> + label = "port6";
> + status = "disabled";
> + };
> +
> + main_cpsw0_port7: port@7 {
> + reg = <7>;
> + label = "port7";
> + status = "disabled";
> + };
> +
> + main_cpsw0_port8: port@8 {
> + reg = <8>;
> + label = "port8";
> + status = "disabled";
> + };
> + };
> +
...
--
Regards,
Siddharth.
next prev parent reply other threads:[~2024-01-25 12:04 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-25 10:04 [PATCH v3 0/5] Add CPSW2G and CPSW9G nodes for J784S4 Chintan Vankar
2024-01-25 10:04 ` [PATCH v3 1/5] arm64: dts: ti: k3-j784s4-main: Fix mux-reg-masks in serdes_ln_ctrl Chintan Vankar
2024-01-25 14:47 ` Andrew Davis
2024-01-25 10:04 ` [PATCH v3 2/5] arm64: dts: ti: k3-j784s4-main: Add CPSW2G and CPSW9G nodes Chintan Vankar
2024-01-25 12:03 ` Siddharth Vadapalli [this message]
2024-01-25 10:04 ` [PATCH v3 3/5] arm64: dts: ti: k3-j784s4: Add Main CPSW2G node Chintan Vankar
2024-01-25 10:05 ` [PATCH v3 4/5] arm64: dts: ti: k3-j784s4: Add overlay to enable QSGMII mode with CPSW9G Chintan Vankar
2024-01-25 10:05 ` [PATCH v3 5/5] arm64: dts: ti: k3-j784s4: Add overlay for dual port USXGMII mode Chintan Vankar
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