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Wed, 26 Feb 2025 20:11:48 -0800 (PST) X-Google-Smtp-Source: AGHT+IFRIX3IkvZiOUdHKEbb1/zqOV6uSSXIJDZqwMP6rxtAvZaceoDHFXvQadYXggDDykHwRSrVbA== X-Received: by 2002:a05:6a21:32a8:b0:1ee:c598:7a90 with SMTP id adf61e73a8af0-1f0fc99bf90mr16869027637.39.1740629508534; Wed, 26 Feb 2025 20:11:48 -0800 (PST) Received: from [10.92.199.34] ([202.46.23.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-734a003eb65sm458168b3a.149.2025.02.26.20.11.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 26 Feb 2025 20:11:48 -0800 (PST) Message-ID: <0dffeb3b-63b3-266e-d1e9-b8adda7cc0ec@oss.qualcomm.com> Date: Thu, 27 Feb 2025 09:41:41 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH v4 00/10] PCI: Enable Power and configure the TC956x PCIe switch Content-Language: en-US To: Manivannan Sadhasivam Cc: Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , chaitanya chundru , Bjorn Andersson , Konrad Dybcio , cros-qcom-dts-watchers@chromium.org, Jingoo Han , Bartosz Golaszewski , quic_vbadigan@quicnic.com, amitk@kernel.org, dmitry.baryshkov@linaro.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, jorge.ramirez@oss.qualcomm.com, Bartosz Golaszewski References: <20250225-qps615_v4_1-v4-0-e08633a7bdf8@oss.qualcomm.com> <20250227035737.q7qlexdcieubbphx@thinkpad> <20250227035924.p43tpbtjmqszdww6@thinkpad> From: Krishna Chaitanya Chundru In-Reply-To: <20250227035924.p43tpbtjmqszdww6@thinkpad> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: -6aYzxzHTPATK1gKxcgiea_zg9k1cVSx X-Proofpoint-ORIG-GUID: -6aYzxzHTPATK1gKxcgiea_zg9k1cVSx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-27_02,2025-02-26_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 phishscore=0 bulkscore=0 mlxscore=0 impostorscore=0 spamscore=0 mlxlogscore=836 clxscore=1015 priorityscore=1501 adultscore=0 suspectscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2502270029 On 2/27/2025 9:29 AM, Manivannan Sadhasivam wrote: > On Thu, Feb 27, 2025 at 09:27:47AM +0530, Manivannan Sadhasivam wrote: >> On Tue, Feb 25, 2025 at 03:03:57PM +0530, Krishna Chaitanya Chundru wrote: >>> TC956x is the PCIe switch which has one upstream and three downstream >>> ports. To one of the downstream ports ethernet MAC is connected as endpoint >>> device. Other two downstream ports are supposed to connect to external >>> device. One Host can connect to TC956x by upstream port. >>> >>> TC956x switch power is controlled by the GPIO's. After powering on >>> the switch will immediately participate in the link training. if the >>> host is also ready by that time PCIe link will established. >>> >>> The TC956x needs to configured certain parameters like de-emphasis, >>> disable unused port etc before link is established. >>> >>> As the controller starts link training before the probe of pwrctl driver, >>> the PCIe link may come up as soon as we power on the switch. Due to this >>> configuring the switch itself through i2c will not have any effect as >>> this configuration needs to done before link training. To avoid this >>> introduce two functions in pci_ops to start_link() & stop_link() which >>> will disable the link training if the PCIe link is not up yet. >>> >>> Enable global IRQ for PCIe controller so that recan can happen when >>> link was up through global IRQ. >>> >> >> Move these patches to a separate series. >> > > Or you can just drop them. I have a series that adds global IRQ to most of the > SoCs and sc7280 is one of them. > > - Mani fine for me, I will drop. - Krishna Chaitanya. >