From: "Shradha Todi" <shradha.t@samsung.com>
To: "'Krzysztof Kozlowski'" <krzk@kernel.org>
Cc: <linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-samsung-soc@vger.kernel.or>,
<linux-kernel@vger.kernel.org>, <linux-phy@lists.infradead.org>,
<manivannan.sadhasivam@linaro.org>, <lpieralisi@kernel.org>,
<kw@linux.com>, <robh@kernel.org>, <bhelgaas@google.com>,
<jingoohan1@gmail.com>, <krzk+dt@kernel.org>,
<conor+dt@kernel.org>, <alim.akhtar@samsung.com>,
<vkoul@kernel.org>, <kishon@kernel.org>, <arnd@arndb.de>,
<m.szyprowski@samsung.com>, <jh80.chung@samsung.com>,
"'Hrishikesh Dileep'" <hrishikesh.d@samsung.com>
Subject: RE: [PATCH 03/10] PCI: exynos: Reorder MACROs to maintain consistency
Date: Tue, 27 May 2025 16:12:46 +0530 [thread overview]
Message-ID: <0e2201dbcef4$1a0f8b50$4e2ea1f0$@samsung.com> (raw)
In-Reply-To: <20250521-mysterious-mole-of-priority-8a5f4d@kuoka>
> -----Original Message-----
> From: Krzysztof Kozlowski <krzk@kernel.org>
> Sent: 21 May 2025 15:16
> To: Shradha Todi <shradha.t@samsung.com>
> Cc: linux-pci@vger.kernel.org; devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-samsung-soc@vger.kernel.or;
> linux-kernel@vger.kernel.org; linux-phy@lists.infradead.org; manivannan.sadhasivam@linaro.org; lpieralisi@kernel.org;
> kw@linux.com; robh@kernel.org; bhelgaas@google.com; jingoohan1@gmail.com; krzk+dt@kernel.org; conor+dt@kernel.org;
> alim.akhtar@samsung.com; vkoul@kernel.org; kishon@kernel.org; arnd@arndb.de; m.szyprowski@samsung.com;
> jh80.chung@samsung.com; Hrishikesh Dileep <hrishikesh.d@samsung.com>
> Subject: Re: [PATCH 03/10] PCI: exynos: Reorder MACROs to maintain consistency
>
> On Mon, May 19, 2025 at 01:01:45AM GMT, Shradha Todi wrote:
> > Exynos PCI file follows MACRO definition order where register offset
> > is defined in ascending order and each bit field within the offset is
> > defined right after offset definition. Some MACROs are out of order
> > and so reorder those MACROs to maintain consistency.
> >
> > Suggested-by: Hrishikesh Dileep <hrishikesh.d@samsung.com>
> > Signed-off-by: Shradha Todi <shradha.t@samsung.com>
> > ---
> > drivers/pci/controller/dwc/pci-exynos.c | 6 +++---
> > 1 file changed, 3 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/pci/controller/dwc/pci-exynos.c
> > b/drivers/pci/controller/dwc/pci-exynos.c
> > index 990aaa16b132..286f4987d56f 100644
> > --- a/drivers/pci/controller/dwc/pci-exynos.c
> > +++ b/drivers/pci/controller/dwc/pci-exynos.c
> > @@ -27,11 +27,11 @@
> >
> > /* PCIe ELBI registers */
> > #define EXYNOS_PCIE_IRQ_PULSE 0x000
> > +#define EXYNOS_PCIE_IRQ_EN_PULSE 0x00c
> > #define EXYNOS_IRQ_INTA_ASSERT BIT(0)
> > #define EXYNOS_IRQ_INTB_ASSERT BIT(2)
> > #define EXYNOS_IRQ_INTC_ASSERT BIT(4)
> > #define EXYNOS_IRQ_INTD_ASSERT BIT(6)
> > -#define EXYNOS_PCIE_IRQ_EN_PULSE 0x00c
> > #define EXYNOS_PCIE_IRQ_EN_LEVEL 0x010
> > #define EXYNOS_PCIE_IRQ_EN_SPECIAL 0x014
> > #define EXYNOS_PCIE_SW_WAKE 0x018
> > @@ -42,12 +42,12 @@
> > #define EXYNOS_PCIE_NONSTICKY_RESET 0x024
> > #define EXYNOS_PCIE_APP_INIT_RESET 0x028
> > #define EXYNOS_PCIE_APP_LTSSM_ENABLE 0x02c
> > +#define EXYNOS_PCIE_ELBI_LTSSM_ENABLE 0x1
> > #define EXYNOS_PCIE_ELBI_RDLH_LINKUP 0x074
> > #define EXYNOS_PCIE_ELBI_XMLH_LINKUP BIT(4)
> > -#define EXYNOS_PCIE_ELBI_LTSSM_ENABLE 0x1
> > #define EXYNOS_PCIE_ELBI_SLV_AWMISC 0x11c
> > #define EXYNOS_PCIE_ELBI_SLV_ARMISC 0x120
> > -#define EXYNOS_PCIE_ELBI_SLV_DBI_ENABLE BIT(21)
> > +#define EXYNOS_PCIE_ELBI_SLV_DBI_ENABLE BIT(21)
>
> What changed here? Why you cannot fix indentation while renaming?
>
Will squash the indentation change along with rename
> Best regards,
> Krzysztof
next prev parent reply other threads:[~2025-05-28 4:52 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20250518193219epcas5p24b442233b3e2bc2a92f43b71a126062f@epcas5p2.samsung.com>
2025-05-18 19:31 ` [PATCH 00/10] Add PCIe support for Tesla FSD SoC Shradha Todi
2025-05-18 19:31 ` [PATCH 01/10] PCI: exynos: Change macro names to exynos specific Shradha Todi
2025-05-18 19:31 ` [PATCH 02/10] PCI: exynos: Remove unused MACROs in exynos PCI file Shradha Todi
2025-05-21 9:41 ` Krzysztof Kozlowski
2025-05-27 10:42 ` Shradha Todi
2025-05-18 19:31 ` [PATCH 03/10] PCI: exynos: Reorder MACROs to maintain consistency Shradha Todi
2025-05-21 9:45 ` Krzysztof Kozlowski
2025-05-27 10:42 ` Shradha Todi [this message]
2025-05-18 19:31 ` [PATCH 04/10] PCI: exynos: Add platform device private data Shradha Todi
2025-05-21 9:44 ` Krzysztof Kozlowski
2025-05-27 10:43 ` Shradha Todi
2025-06-13 9:04 ` Manivannan Sadhasivam
2025-05-18 19:31 ` [PATCH 05/10] PCI: exynos: Add structure to hold resource operations Shradha Todi
2025-05-21 9:42 ` Krzysztof Kozlowski
2025-05-27 10:44 ` Shradha Todi
2025-05-18 19:31 ` [PATCH 06/10] dt-bindings: PCI: Add bindings support for Tesla FSD SoC Shradha Todi
2025-05-21 9:37 ` Krzysztof Kozlowski
2025-05-27 10:44 ` Shradha Todi
2025-05-18 19:31 ` [PATCH 07/10] dt-bindings: phy: Add PHY bindings support for " Shradha Todi
2025-05-21 9:33 ` Krzysztof Kozlowski
2025-05-27 10:44 ` Shradha Todi
2025-05-18 19:31 ` [PATCH 08/10] phy: exynos: Add PCIe PHY " Shradha Todi
2025-05-21 9:40 ` Krzysztof Kozlowski
2025-05-27 10:45 ` Shradha Todi
2025-05-28 7:21 ` Krzysztof Kozlowski
2025-05-18 19:31 ` [PATCH 09/10] PCI: exynos: Add support for Tesla " Shradha Todi
2025-05-19 10:26 ` Niklas Cassel
2025-05-21 9:48 ` Krzysztof Kozlowski
2025-05-27 10:45 ` Shradha Todi
2025-05-28 7:25 ` Krzysztof Kozlowski
2025-05-29 10:24 ` Shradha Todi
2025-05-18 19:31 ` [PATCH 10/10] misc: pci_endpoint_test: Add driver data for FSD PCIe controllers Shradha Todi
2025-05-19 9:59 ` Niklas Cassel
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