Re: [PATCH v3 5/6] dt-bindings: soc: fsl: qe: Add support of IRQ in QE GPIO

[Krzysztof Kozlowski <krzk@kernel.org>]

On 28/08/2025 16:12, Christophe Leroy wrote:
> 
> 
> Le 28/08/2025 à 15:28, Rob Herring a écrit :
>> On Mon, Aug 25, 2025 at 2:20 AM Christophe Leroy
>> <christophe.leroy@csgroup.eu> wrote:
>>>
>>> In the QE, a few GPIOs are IRQ capable. Similarly to
>>> commit 726bd223105c ("powerpc/8xx: Adding support of IRQ in MPC8xx
>>> GPIO"), add IRQ support to QE GPIO.
>>>
>>> Add property 'fsl,qe-gpio-irq-mask' similar to
>>> 'fsl,cpm1-gpio-irq-mask' that define which of the GPIOs have IRQs.
>>
>> Why do you need to know this? The ones that have interrupts will be
>> referenced by an 'interrupts' property somewhere.
> 
> I don't follow you. The ones that have interrupts need to be reported by 
> gc->qe_gpio_to_irq[] so that gpiod_to_irq() return the IRQ number, for 
> instance to gpio_sysfs_request_irq() so that it can install an irq 
> handler. I can't see where they would be referenced by an "interrupts" 
> property.

They would be referenced by every consumer of these interrupts. IOW,
this property is completely redundant, because DT holds this information
already in other place.

> 
>>
>>> Here is an exemple for port B of mpc8323 which has IRQs for
>>
>> typo
>>
>>> GPIOs PB7, PB9, PB25 and PB27.
>>>
>>>          qe_pio_b: gpio-controller@1418 {
>>>                  compatible = "fsl,mpc8323-qe-pario-bank";
>>>                  reg = <0x1418 0x18>;
>>>                  interrupts = <4 5 6 7>;
>>>                  interrupt-parent = <&qepic>;
>>>                  gpio-controller;
>>>                  #gpio-cells = <2>;
>>>                  fsl,qe-gpio-irq-mask = <0x01400050>;
>>>          };
>>
>> You are missing #interrupt-cells and interrupt-controller properties.
> 
> The gpio controller is not an interrupt controller. The GPIO controller 
> is brought by patch 1/6 and documented in patch 6/6.

Then the IRQ mask property is not right here. If you say "this GPIOs
have IRQs" it means this is an interrupt controller.

If you say this is not an interrupt controller, then you cannot have
here interrupts per some GPIOs, obviously.


Best regards,
Krzysztof