From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 109F225A655 for ; Tue, 14 Apr 2026 02:10:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.17 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776132606; cv=none; b=k028FPK1emyyhCyMAxKc3CkTBqcGCKgbt1/P9twAOdVoL2XjodFHRwiMNy9BbUnJ7/GCqqQX3FFg7zmQMaqZvlBr+VF2vN1T+dNUIavdcPFZitU8ptvEin1XlPgc/HOuTq6aF2weOchGh5IlNgqFBs40+o/vIMh9VjC+d3WO5s8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776132606; c=relaxed/simple; bh=Hr+qEZC6NJEuWKXXn2Bl5q7hIOzRuEGyvW93qh9ut+E=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=U/QWf8ziPwf8lb6e2/uJV2HVKfjwbwR6xYt45tbGj2qRYTtNendtXay+MWRXH4oASa2OAtH5kLfR0tcV0CutLQDyyEABPFRkLcCvXwEK2+W92EaBgp3O9hrqCl4Nk/1BZPKa0HqfXhsyX/1VUPxcpFUyXjj9+OTir0YjJiioft0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=RAjDtgyL; arc=none smtp.client-ip=198.175.65.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="RAjDtgyL" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1776132604; x=1807668604; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=Hr+qEZC6NJEuWKXXn2Bl5q7hIOzRuEGyvW93qh9ut+E=; b=RAjDtgyLOmy2qP3t5W//K0+xjxPgFfxhHrUBxngByY8l4PxeR6bYpVqd pgyaMnzHvffhykKEL5BHkrpZrHRrZ9/3q7syZD4SYfaSMhIVLRakhpQnX TbHOYMUWrb+eceMf7XDa9r7DUu9mj9W1l87kkqdOtNn4GivoI56dEGWd4 G5oexJIt4Abx5yE5w1K0/Fi5pSCm75ibgjnVXN2cilUGy5kxQW9sn8AEL mz0RDeDRnkCNiuATe54dz3A21RYVS12Vgr7gFOkayqv+vRK1ApclMvLL+ jhJWSzxlUpGnx2hHQuIzj18ObREF37cHQn/7tmOkmzsUaKOGcKIjLt3+R g==; X-CSE-ConnectionGUID: pfFA2pRLQ0mUlG/lJpmysw== X-CSE-MsgGUID: /oZLNi8fTyq3kG9O274Nbg== X-IronPort-AV: E=McAfee;i="6800,10657,11758"; a="77043338" X-IronPort-AV: E=Sophos;i="6.23,178,1770624000"; d="scan'208";a="77043338" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Apr 2026 19:10:04 -0700 X-CSE-ConnectionGUID: zyphBaoQS3uWGxwYdJEoKg== X-CSE-MsgGUID: LbMqKjbuTZWrdrqMCXypPg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,178,1770624000"; d="scan'208";a="260375841" Received: from unknown (HELO [10.238.1.30]) ([10.238.1.30]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Apr 2026 19:10:01 -0700 Message-ID: <0f7a3753-fd60-4a33-b425-c2d1bf964711@linux.intel.com> Date: Tue, 14 Apr 2026 10:09:58 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] perf/x86/intel: Keep anythread_deprecated capability To: Namhyung Kim , Peter Zijlstra , Ingo Molnar Cc: Mark Rutland , Alexander Shishkin , Arnaldo Carvalho de Melo , LKML , Stephane Eranian References: <20260413212933.2495502-1-namhyung@kernel.org> Content-Language: en-US From: "Mi, Dapeng" In-Reply-To: <20260413212933.2495502-1-namhyung@kernel.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 4/14/2026 5:29 AM, Namhyung Kim wrote: > In update_pmu_cap(), it reads MSR_IA32_PERF_CAPABILITIES on non-MTL CPUs > to update the PMU capabilities. But it resets the anythread_deprecated > bit on GNR so I can see /sys/bus/event_source/devices/cpu/format/any > even if dmesg says AnyThread is deprecated. > > # dmesg | grep -A10 AnyThread > [ 10.662423] Performance Events: XSAVE Architectural LBR, PEBS fmt5+-baseline, AnyThread deprecated, Granite Rapids events, 32-deep LBR, full-width counters, Intel PMU driver. > [ 10.663172] ... version: 5 > [ 10.663173] ... bit width: 48 > [ 10.663174] ... generic counters: 8 > [ 10.663174] ... generic bitmap: 00000000000000ff > [ 10.663175] ... fixed-purpose counters: 4 > [ 10.663176] ... fixed-purpose bitmap: 000000000000000f > [ 10.663176] ... value mask: 0000ffffffffffff > [ 10.663177] ... max period: 00007fffffffffff > [ 10.663178] ... global_ctrl mask: 0001000f000000ff > [ 10.668979] signal: max sigframe size: 11952 > > I guess it's not intentional and we want to keep deprecating anythread > on these machines. > > Fixes: 25c623f41438fafc ("perf/x86/intel: Parse CPUID archPerfmonExt leaves for non-hybrid CPUs") > Cc: Dapeng Mi > Signed-off-by: Namhyung Kim > --- > arch/x86/events/intel/core.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c > index 4768236c054bbcf8..f1fae640cc8e5991 100644 > --- a/arch/x86/events/intel/core.c > +++ b/arch/x86/events/intel/core.c > @@ -5945,8 +5945,12 @@ static void update_pmu_cap(struct pmu *pmu) > } > > if (!intel_pmu_broken_perf_cap()) { > + bool anythread = hybrid(pmu, intel_cap).anythread_deprecated; > + > /* Perf Metric (Bit 15) and PEBS via PT (Bit 16) are hybrid enumeration */ > rdmsrq(MSR_IA32_PERF_CAPABILITIES, hybrid(pmu, intel_cap).capabilities); > + /* It seems anythread_deprecated is deleted unintentionally */ > + hybrid(pmu, intel_cap).anythread_deprecated = anythread; > } > } > Namhyung, thanks for reporting this issue. But it may be not the best way to fix the issue by restoring the anythread_deprecated bit in intel_cap.  anythread_deprecated is enumerated in CPUID.0AH:EDX[15] instead of the PERF_CAPABILITIES MSR. There is no anythread_deprecated bit in PERF_CAPABILITIES MSR, It's not a good practice to define anythread_deprecated bit in perf_capabilities . Maybe we can do this, remove the anythread_deprecated from perf_capabilities and directly depends on the CPUID.0AH:EDX[15] to check if anythread is deprecated. diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 793335c3ce78..450c63165a22 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -7612,11 +7612,8 @@ __init int intel_pmu_init(void)         x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */ -       if (version >= 5) { -               x86_pmu.intel_cap.anythread_deprecated = edx.split.anythread_deprecated; -               if (x86_pmu.intel_cap.anythread_deprecated) -                       pr_cont(" AnyThread deprecated, "); -       } +       if (version >= 5 && edx.split.anythread_deprecated) +               pr_cont(" AnyThread deprecated, ");         /* The perf side of core PMU is ready to support the mediated vPMU. */         x86_get_pmu(smp_processor_id())->capabilities |= PERF_PMU_CAP_MEDIATED_VPMU; @@ -8467,7 +8464,7 @@ __init int intel_pmu_init(void)                                       &x86_pmu.intel_ctrl);         /* AnyThread may be deprecated on arch perfmon v5 or later */ -       if (x86_pmu.intel_cap.anythread_deprecated) +       if (edx.split.anythread_deprecated)                 x86_pmu.format_attrs = intel_arch_formats_attr;         intel_pmu_check_event_constraints_all(NULL); diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index fad87d3c8b2c..01217c663dff 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -660,7 +660,7 @@ union perf_capabilities {                 u64     perf_metrics:1;                 u64     pebs_output_pt_available:1;                 u64     pebs_timing_info:1; -               u64     anythread_deprecated:1; +               u64     __reserved:1;                 u64     rdpmc_metrics_clear:1;         };         u64     capabilities; Not fully tested, only test on SPR and it looks good.  Thanks.