From: "Mi, Dapeng" <dapeng1.mi@linux.intel.com>
To: Sean Christopherson <seanjc@google.com>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Namhyung Kim <namhyung@kernel.org>,
Paolo Bonzini <pbonzini@redhat.com>
Cc: Mark Rutland <mark.rutland@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Jiri Olsa <jolsa@kernel.org>, Ian Rogers <irogers@google.com>,
Adrian Hunter <adrian.hunter@intel.com>,
James Clark <james.clark@linaro.org>,
linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org,
kvm@vger.kernel.org, Jim Mattson <jmattson@google.com>,
Mingwei Zhang <mizhang@google.com>,
Stephane Eranian <eranian@google.com>
Subject: Re: [PATCH v3 5/9] perf/x86/intel: Invert names of intel_ctrl_{guest,host}_mask
Date: Tue, 12 May 2026 12:58:08 +0800 [thread overview]
Message-ID: <0fbd4abc-a767-4dfe-91e4-f40a17ab707d@linux.intel.com> (raw)
In-Reply-To: <20260508231353.406465-6-seanjc@google.com>
On 5/9/2026 7:13 AM, Sean Christopherson wrote:
> Rename intel_ctrl_{guest,host}_mask to intel_ctrl_exclude_{host,guest}_mask
> to more accurately capture what they actually track. Specifically, an
> event that is excluded from the guest is NOT guaranteed to count in the
> host, and vice versa, as it legal (albeit bizarre) to configure an event to
> exclude both the host and the guest, i.e. to not count at all.
>
> Subjectively (though anyone who disagrees is wrong), aligning with
> perf_event_attr.exclude_{guest,host} also makes all related code much
> easier to follow.
>
> No functional change intended.
>
> Suggested-by: Jim Mattson <jmattson@google.com>
> Signed-off-by: Sean Christopherson <seanjc@google.com>
> ---
> arch/x86/events/intel/core.c | 22 +++++++++++-----------
> arch/x86/events/intel/lbr.c | 2 +-
> arch/x86/events/perf_event.h | 4 ++--
> 3 files changed, 14 insertions(+), 14 deletions(-)
>
> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
> index e9f5a6143e71..7f7c7927b70b 100644
> --- a/arch/x86/events/intel/core.c
> +++ b/arch/x86/events/intel/core.c
> @@ -2535,7 +2535,7 @@ static void __intel_pmu_enable_all(int added, bool pmi)
> }
>
> wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL,
> - intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
> + intel_ctrl & ~cpuc->intel_ctrl_exclude_host_mask);
>
> if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
> struct perf_event *event =
> @@ -2733,9 +2733,9 @@ static inline void intel_set_masks(struct perf_event *event, int idx)
> struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
>
> if (event->attr.exclude_host)
> - __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask);
> + __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_exclude_host_mask);
> if (event->attr.exclude_guest)
> - __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask);
> + __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_exclude_guest_mask);
> if (event_is_checkpointed(event))
> __set_bit(idx, (unsigned long *)&cpuc->intel_cp_status);
> }
> @@ -2744,8 +2744,8 @@ static inline void intel_clear_masks(struct perf_event *event, int idx)
> {
> struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
>
> - __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask);
> - __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask);
> + __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_exclude_host_mask);
> + __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_exclude_guest_mask);
> __clear_bit(idx, (unsigned long *)&cpuc->intel_cp_status);
> }
>
> @@ -3473,7 +3473,7 @@ static void x86_pmu_handle_guest_pebs(struct pt_regs *regs,
> struct perf_sample_data *data)
> {
> struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
> - u64 guest_pebs_idxs = cpuc->pebs_enabled & ~cpuc->intel_ctrl_host_mask;
> + u64 guest_pebs_idxs = cpuc->pebs_enabled & ~cpuc->intel_ctrl_exclude_guest_mask;
> struct perf_event *event = NULL;
> int bit;
>
> @@ -5013,8 +5013,8 @@ static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, void *data)
> global_ctrl = (*nr)++;
> arr[global_ctrl] = (struct perf_guest_switch_msr){
> .msr = MSR_CORE_PERF_GLOBAL_CTRL,
> - .host = intel_ctrl & ~cpuc->intel_ctrl_guest_mask,
> - .guest = intel_ctrl & ~cpuc->intel_ctrl_host_mask & ~pebs_mask,
> + .host = intel_ctrl & ~cpuc->intel_ctrl_exclude_host_mask,
> + .guest = intel_ctrl & ~cpuc->intel_ctrl_exclude_guest_mask & ~pebs_mask,
> };
>
> if (!x86_pmu.ds_pebs)
> @@ -5051,8 +5051,8 @@ static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, void *data)
> * in the guest, and (d) _are_ excluded from counting in the host.
> */
> guest_pebs_mask = pebs_mask & intel_ctrl & kvm_pmu->pebs_enable &
> - ~cpuc->intel_ctrl_host_mask &
> - cpuc->intel_ctrl_guest_mask;
> + ~cpuc->intel_ctrl_exclude_guest_mask &
> + cpuc->intel_ctrl_exclude_host_mask;
>
> /*
> * Disable counters where the guest PMC is different than the host PMC
> @@ -5068,7 +5068,7 @@ static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, void *data)
> * What exactly goes wrong if guest and host are using PEBS is
> * unknown.
> */
> - if (pebs_mask & ~cpuc->intel_ctrl_guest_mask)
> + if (pebs_mask & ~cpuc->intel_ctrl_exclude_host_mask)
> guest_pebs_mask = 0;
>
> /*
> diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c
> index 72f2adcda7c6..1298049246d7 100644
> --- a/arch/x86/events/intel/lbr.c
> +++ b/arch/x86/events/intel/lbr.c
> @@ -713,7 +713,7 @@ static inline bool vlbr_exclude_host(void)
> struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
>
> return test_bit(INTEL_PMC_IDX_FIXED_VLBR,
> - (unsigned long *)&cpuc->intel_ctrl_guest_mask);
> + (unsigned long *)&cpuc->intel_ctrl_exclude_host_mask);
> }
>
> void intel_pmu_lbr_enable_all(bool pmi)
> diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
> index fad87d3c8b2c..cc0aeeb34eb5 100644
> --- a/arch/x86/events/perf_event.h
> +++ b/arch/x86/events/perf_event.h
> @@ -339,8 +339,8 @@ struct cpu_hw_events {
> /*
> * Intel host/guest exclude bits
> */
> - u64 intel_ctrl_guest_mask;
> - u64 intel_ctrl_host_mask;
> + u64 intel_ctrl_exclude_host_mask;
> + u64 intel_ctrl_exclude_guest_mask;
This looks much straightforward.
Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
> struct perf_guest_switch_msr guest_switch_msrs[X86_PMC_IDX_MAX];
>
> /*
next prev parent reply other threads:[~2026-05-12 4:58 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-08 23:13 [PATCH v3 0/9] perf/x86: Don't write PEBS_ENABLED on KVM transitions Sean Christopherson
2026-05-08 23:13 ` [PATCH v3 1/9] perf/x86/intel: Ensure guest PEBS path doesn't set unwanted PERF_GLOBAL_CTRL bits Sean Christopherson
2026-05-12 4:53 ` Mi, Dapeng
2026-05-08 23:13 ` [PATCH v3 2/9] perf/x86/intel: Don't write PEBS_ENABLED on host<=>guest xfers if CPU has isolation Sean Christopherson
2026-05-12 4:53 ` Mi, Dapeng
2026-05-08 23:13 ` [PATCH v3 3/9] perf/x86/intel: Don't context switch DS_AREA (and PEBS config) if PEBS is unused Sean Christopherson
2026-05-08 23:13 ` [PATCH v3 4/9] perf/x86/intel: Make @data a mandatory param for intel_guest_get_msrs() Sean Christopherson
2026-05-12 12:39 ` Jim Mattson
2026-05-08 23:13 ` [PATCH v3 5/9] perf/x86/intel: Invert names of intel_ctrl_{guest,host}_mask Sean Christopherson
2026-05-12 4:58 ` Mi, Dapeng [this message]
2026-05-08 23:13 ` [PATCH v3 6/9] perf/x86: KVM: Have perf define a dedicated struct for getting guest PEBS data Sean Christopherson
2026-05-08 23:13 ` [PATCH v3 7/9] perf/x86/intel: KVM: Handle cross-mapped PEBS PMCs entirely within KVM Sean Christopherson
2026-05-12 4:59 ` Mi, Dapeng
2026-05-08 23:13 ` [PATCH v3 8/9] KVM: VMX: Drop a redundant pmu->global_ctrl check when processing pebs_enable Sean Christopherson
2026-05-12 5:00 ` Mi, Dapeng
2026-05-08 23:13 ` [PATCH v3 9/9] KVM: VMX: Only tell perf to enable PEBS counters for fully enabled PMCs Sean Christopherson
2026-05-12 5:01 ` Mi, Dapeng
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