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[84.0.31.242]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48047028928sm191404245e9.2.2026.01.23.03.20.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Jan 2026 03:20:32 -0800 (PST) From: Timur =?UTF-8?B?S3Jpc3TDs2Y=?= To: dri-devel@lists.freedesktop.org, Hamza Mahfooz Cc: Hamza Mahfooz , Alex Deucher , Christian =?UTF-8?B?S8O2bmln?= , David Airlie , Simona Vetter , Harry Wentland , Leo Li , Rodrigo Siqueira , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Sunil Khatri , Lijo Lazar , Ce Sun , Ivan Lipski , Kenneth Feng , Alex Hung , Tom Chung , Melissa Wen , Michel =?UTF-8?B?RMOkbnplcg==?= , Fangzhi Zuo , amd-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/2] drm/amdgpu: implement page_flip_timeout() support Date: Fri, 23 Jan 2026 12:20:30 +0100 Message-ID: <10030872.eNJFYEL58v@timur-hyperion> In-Reply-To: <20260123000537.2450496-2-someguy@effective-light.com> References: <20260123000537.2450496-1-someguy@effective-light.com> <20260123000537.2450496-2-someguy@effective-light.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On Friday, January 23, 2026 1:05:28=E2=80=AFAM Central European Standard Ti= me Hamza=20 Mahfooz wrote: > We now have a means to respond to page flip timeouts. So, hook up > support for the new page_flip_timeout() callback. >=20 > Signed-off-by: Hamza Mahfooz > --- > Hi, >=20 > I have tested this on 7940HS system and it appears even a MODE2 reset > will reset display firmware, so I don't think we need to force a full > reset here. > --- MODE2 reset _is_ a full reset on APUs, it resets everything but just doesn'= t=20 lose the RAM contents. Also note that MODE2 reset is not supported on=20 dedicated GPUs, so this will likely trigger a full reset for those. Can you say how you tested this? I'd be happy to test it myself too. > drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c | 2 ++ > drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h | 1 + > .../drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 18 ++++++++++++++++++ > 3 files changed, 21 insertions(+) >=20 > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c index > 28c4ad62f50e..bd63f0345984 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c > @@ -343,6 +343,8 @@ void amdgpu_reset_get_desc(struct amdgpu_reset_context > *rst_ctxt, char *buf, case AMDGPU_RESET_SRC_USERQ: > strscpy(buf, "user queue trigger", len); > break; > + case AMDGPU_RESET_SRC_DISPLAY: > + strscpy(buf, "display hang", len); > default: > strscpy(buf, "unknown", len); > } > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h > b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h index > 07b4d37f1db6..53b577062b11 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h > @@ -44,6 +44,7 @@ enum AMDGPU_RESET_SRCS { > AMDGPU_RESET_SRC_HWS, > AMDGPU_RESET_SRC_USER, > AMDGPU_RESET_SRC_USERQ, > + AMDGPU_RESET_SRC_DISPLAY, > }; >=20 > struct amdgpu_reset_context { > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index > 697e232acebf..2233e5b3b6a2 100644 > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c > @@ -28,6 +28,7 @@ >=20 > #include "dc.h" > #include "amdgpu.h" > +#include "amdgpu_reset.h" > #include "amdgpu_dm_psr.h" > #include "amdgpu_dm_replay.h" > #include "amdgpu_dm_crtc.h" > @@ -578,12 +579,29 @@ amdgpu_dm_atomic_crtc_get_property(struct drm_crtc > *crtc, } > #endif >=20 > +static void amdgpu_dm_crtc_handle_timeout(struct drm_crtc *crtc) > +{ > + struct amdgpu_device *adev =3D drm_to_adev(crtc->dev); > + struct amdgpu_reset_context reset_context =3D {0}; > + > + if (amdgpu_device_should_recover_gpu(adev)) { > + memset(&reset_context, 0, sizeof(reset_context)); > + > + reset_context.method =3D AMD_RESET_METHOD_NONE; > + reset_context.reset_req_dev =3D adev; > + reset_context.src =3D AMDGPU_RESET_SRC_DISPLAY; > + > + amdgpu_device_gpu_recover(adev, NULL, &reset_context); > + } > +} > + > /* Implemented only the options currently available for the driver */ > static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs =3D { > .reset =3D amdgpu_dm_crtc_reset_state, > .destroy =3D amdgpu_dm_crtc_destroy, > .set_config =3D drm_atomic_helper_set_config, > .page_flip =3D drm_atomic_helper_page_flip, > + .page_flip_timeout =3D amdgpu_dm_crtc_handle_timeout, > .atomic_duplicate_state =3D amdgpu_dm_crtc_duplicate_state, > .atomic_destroy_state =3D amdgpu_dm_crtc_destroy_state, > .set_crc_source =3D amdgpu_dm_crtc_set_crc_source,