* 3 ultra100 controllers
@ 2002-09-04 18:19 T. Ryan Halwachs
2002-09-04 19:48 ` Andre Hedrick
0 siblings, 1 reply; 6+ messages in thread
From: T. Ryan Halwachs @ 2002-09-04 18:19 UTC (permalink / raw)
To: kernel mailing list, ataraid mailing list, andre
sent this to promise:
> -----Original Message-----
> From: T. Ryan Halwachs [mailto:halwachs@cats.ucsc.edu]
> Sent: Monday, August 26, 2002 4:18 PM
> To: support@promise.com
> Subject: 3 ultra100 controllers
>
>
> hi,
> i am trying to use three Promise technology controllers in one system.
> the promise bios only shows drives attached to the first 2 controllers.
> how can i use the drives attached to the third controller?
>
> cheers,
> ryan
>
>
>
got this in reply:
> From: support <support@promise.com>
> To: 'T. Ryan Halwachs' <halwachs@cats.ucsc.edu>
> Subject: RE: 3 ultra100 controllers
> Date: 28 Aug 2002 08:23:29 -0700
>
> Hi Ryan
> Sorry you will not be able to used 3 ultra100 in single system.
> 2 is the most.
>
> It's All About Your Data!
>
> Kevin Huynh
> Reseller Technical Support.
> Promise Technology, Inc
> 1745 McCandless Dr.
> Milpitas Ca, 95035
> 408-228-6300
>
>
from pdc202xx.c in 2.4.19-ac4
/*
* linux/drivers/ide/pdc202xx.c Version 0.35 Mar. 30, 2002
*
* Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
*
* Promise Ultra33 cards with BIOS v1.20 through 1.28 will need this
* compiled into the kernel if you have more than one card installed.
* Note that BIOS v1.29 is reported to fix the problem. Since this is
* safe chipset tuning, including this support is harmless
*
* Promise Ultra66 cards with BIOS v1.11 this
* compiled into the kernel if you have more than one card installed.
*
* Promise Ultra100 cards.
*
* The latest chipset code will support the following ::
* Three Ultra33 controllers and 12 drives.
* 8 are UDMA supported and 4 are limited to DMA mode 2 multi-word.
* The 8/4 ratio is a BIOS code limit by promise.
*
* UNLESS you enable "CONFIG_PDC202XX_BURST"
*
*/
is it possible (using Linux) to run 3 (or more) PDC20267 based ultra100 cards in the same machine?
cheers,
ryan
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: 3 ultra100 controllers
2002-09-04 18:19 3 ultra100 controllers T. Ryan Halwachs
@ 2002-09-04 19:48 ` Andre Hedrick
2002-09-04 23:36 ` Alan Cox
0 siblings, 1 reply; 6+ messages in thread
From: Andre Hedrick @ 2002-09-04 19:48 UTC (permalink / raw)
To: T. Ryan Halwachs; +Cc: kernel mailing list, ataraid mailing list, Jeff Nguyen
BAWHAHAHA,
5 have been done!
Ask "Jeff Nguyen", all it means is that only two cards will be setup by
their BIOS. The remaining cards will be setup by the driver.
IIRC, there was a special RIO version with 8 card or 32 drives.
Cheers,
On 4 Sep 2002, T. Ryan Halwachs wrote:
> sent this to promise:
>
> > -----Original Message-----
> > From: T. Ryan Halwachs [mailto:halwachs@cats.ucsc.edu]
> > Sent: Monday, August 26, 2002 4:18 PM
> > To: support@promise.com
> > Subject: 3 ultra100 controllers
> >
> >
> > hi,
> > i am trying to use three Promise technology controllers in one system.
> > the promise bios only shows drives attached to the first 2 controllers.
> > how can i use the drives attached to the third controller?
> >
> > cheers,
> > ryan
> >
> >
> >
>
> got this in reply:
>
> > From: support <support@promise.com>
> > To: 'T. Ryan Halwachs' <halwachs@cats.ucsc.edu>
> > Subject: RE: 3 ultra100 controllers
> > Date: 28 Aug 2002 08:23:29 -0700
> >
> > Hi Ryan
> > Sorry you will not be able to used 3 ultra100 in single system.
> > 2 is the most.
> >
> > It's All About Your Data!
> >
> > Kevin Huynh
> > Reseller Technical Support.
> > Promise Technology, Inc
> > 1745 McCandless Dr.
> > Milpitas Ca, 95035
> > 408-228-6300
> >
> >
>
> from pdc202xx.c in 2.4.19-ac4
>
> /*
> * linux/drivers/ide/pdc202xx.c Version 0.35 Mar. 30, 2002
> *
> * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
> *
> * Promise Ultra33 cards with BIOS v1.20 through 1.28 will need this
> * compiled into the kernel if you have more than one card installed.
> * Note that BIOS v1.29 is reported to fix the problem. Since this is
> * safe chipset tuning, including this support is harmless
> *
> * Promise Ultra66 cards with BIOS v1.11 this
> * compiled into the kernel if you have more than one card installed.
> *
> * Promise Ultra100 cards.
> *
> * The latest chipset code will support the following ::
> * Three Ultra33 controllers and 12 drives.
> * 8 are UDMA supported and 4 are limited to DMA mode 2 multi-word.
> * The 8/4 ratio is a BIOS code limit by promise.
> *
> * UNLESS you enable "CONFIG_PDC202XX_BURST"
> *
> */
>
> is it possible (using Linux) to run 3 (or more) PDC20267 based ultra100 cards in the same machine?
>
> cheers,
> ryan
>
Andre Hedrick
LAD Storage Consulting Group
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: 3 ultra100 controllers
2002-09-04 19:48 ` Andre Hedrick
@ 2002-09-04 23:36 ` Alan Cox
2002-09-05 9:05 ` Andre Hedrick
2002-09-10 23:05 ` T. Ryan Halwachs
0 siblings, 2 replies; 6+ messages in thread
From: Alan Cox @ 2002-09-04 23:36 UTC (permalink / raw)
To: Andre Hedrick
Cc: T. Ryan Halwachs, kernel mailing list, ataraid mailing list,
Jeff Nguyen
On Wed, 2002-09-04 at 20:48, Andre Hedrick wrote:
> 5 have been done!
>
> Ask "Jeff Nguyen", all it means is that only two cards will be setup by
> their BIOS. The remaining cards will be setup by the driver.
> IIRC, there was a special RIO version with 8 card or 32 drives.
I wouldnt like to see the performance of the resulting box or try it on
a VIA chipset or anything else I didn't trust 100% to handle contention
on the PCI bus
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: 3 ultra100 controllers
2002-09-04 23:36 ` Alan Cox
@ 2002-09-05 9:05 ` Andre Hedrick
2002-09-10 23:05 ` T. Ryan Halwachs
1 sibling, 0 replies; 6+ messages in thread
From: Andre Hedrick @ 2002-09-05 9:05 UTC (permalink / raw)
To: Alan Cox
Cc: T. Ryan Halwachs, kernel mailing list, ataraid mailing list,
Jeff Nguyen
Well Jeff will need to verify, but iirc many of those boxes he build and
sold power "amazon.com". I got a charge knowing that factoid, when
everyone was slamming the reliablity and strenghts of ATA servers.
Also there were select systems that may have been VIA but they were hand
picked boards.
Anyways, Jeff will need to comment on this part. However I know he has
shipped with 4 and maybe even 5 cards in a box that ran fine and stable.
Cheers,
On 5 Sep 2002, Alan Cox wrote:
> On Wed, 2002-09-04 at 20:48, Andre Hedrick wrote:
> > 5 have been done!
> >
> > Ask "Jeff Nguyen", all it means is that only two cards will be setup by
> > their BIOS. The remaining cards will be setup by the driver.
> > IIRC, there was a special RIO version with 8 card or 32 drives.
>
> I wouldnt like to see the performance of the resulting box or try it on
> a VIA chipset or anything else I didn't trust 100% to handle contention
> on the PCI bus
>
Andre Hedrick
LAD Storage Consulting Group
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: 3 ultra100 controllers
2002-09-04 23:36 ` Alan Cox
2002-09-05 9:05 ` Andre Hedrick
@ 2002-09-10 23:05 ` T. Ryan Halwachs
2002-09-10 23:38 ` T. Ryan Halwachs
1 sibling, 1 reply; 6+ messages in thread
From: T. Ryan Halwachs @ 2002-09-10 23:05 UTC (permalink / raw)
To: Alan Cox
Cc: Andre Hedrick, kernel mailing list, ataraid mailing list,
Jeff Nguyen
kernel: 2.4.29-ac4
mobo: intel WS440BX (gateway OEM)
bios: 4W4SB0X0.15A.0019.P14
cpu: celeron 400
mem: 288MB
power: powmax LP6100 500W
controllers:
PDC20267(ultra100 PCI) PCI slot 1
PDC20267(ultra100 PCI) PCI slot 2
CMD649(ultraATA 100 PCI) PCI slot 3
drives:
1 WD1200AB 120G drive on card 1 primary channel
1 IC35L120AVVA07-0 120G drive on card 1 secondary channel
2 WD1200AB 120G drives on card 2 (each on a separate channel)
2 WD1200AB 120G drives on card 3 (each on a separate channel)
problem:
I cannot get these drives to work reliably in a software raid5 array. I
was able to partition, mkraid, mke2fs, fsck, mount, and unmount.
I mounted the array locally on machine#0, then via nfs onto machine#1. I
started copying files from machine#1's local drive(s) to the array on
machine#0 via nfs.
I got these errors:
Sep 9 17:41:45 array kernel: hdi: dma_intr: status=0x51 { DriveReady
SeekComplete Error }
Sep 9 17:41:45 array kernel: hdi: dma_intr: error=0x84 {
DriveStatusError BadCRC }
Sep 9 17:42:12 array kernel: hdi: dma_intr: status=0x51 { DriveReady
SeekComplete Error }
Sep 9 17:42:12 array kernel: hdi: dma_intr: error=0x84 {
DriveStatusError BadCRC }
Sep 9 17:42:12 array kernel: hdi: dma_intr: status=0x51 { DriveReady
SeekComplete Error }
Sep 9 17:42:12 array kernel: hdi: dma_intr: error=0x84 {
DriveStatusError BadCRC }
Sep 9 17:42:16 array kernel: hdi: dma_intr: status=0x51 { DriveReady
SeekComplete Error }
Sep 9 17:42:16 array kernel: hdi: dma_intr: error=0x84 {
DriveStatusError BadCRC }
Sep 9 17:42:16 array kernel: hdi: dma_intr: status=0x51 { DriveReady
SeekComplete Error }
Sep 9 17:42:16 array kernel: hdi: dma_intr: error=0x84 {
DriveStatusError BadCRC }
Sep 9 17:42:16 array kernel: hdi: dma_intr: status=0x51 { DriveReady
SeekComplete Error }
Sep 9 17:42:16 array kernel: hdi: dma_intr: error=0x84 {
DriveStatusError BadCRC }
Sep 9 17:42:16 array kernel: hdi: dma_intr: status=0x51 { DriveReady
SeekComplete Error }
Sep 9 17:42:16 array kernel: hdi: dma_intr: error=0x84 {
DriveStatusError BadCRC }
Sep 9 17:42:16 array kernel: PDC202XX: Primary channel reset.
Sep 9 17:42:16 array kernel: ide4: reset: success
Sep 9 17:42:36 array kernel: hdk: timeout waiting for DMA
Sep 9 17:42:36 array kernel: PDC202XX: Secondary channel reset.
Sep 9 17:42:36 array kernel: hdk: ide_dma_timeout: Lets do it
again!stat = 0x50, dma_stat = 0x20
Sep 9 17:42:36 array kernel: hdk: DMA disabled
Sep 9 17:42:36 array kernel: PDC202XX: Secondary channel reset.
Sep 9 17:42:36 array kernel: hdk: ide_set_handler: handler not null;
old=c01c0840, new=c01bdf30
Sep 9 17:42:36 array kernel: bug: kernel timer added twice at c01c06a8.
Sep 9 17:42:36 array kernel: hdk: ide_set_handler: handler not null;
old=c01bdf30, new=c01bdfa0
Sep 9 17:42:36 array kernel: bug: kernel timer added twice at c01c06a8.
Sep 9 17:42:36 array kernel: hdi: timeout waiting for DMA
Sep 9 17:42:36 array kernel: PDC202XX: Primary channel reset.
Sep 9 17:42:36 array kernel: hdi: ide_dma_timeout: Lets do it
again!stat = 0x50, dma_stat = 0x20
Sep 9 17:42:36 array kernel: hdi: DMA disabled
Sep 9 17:42:36 array kernel: PDC202XX: Primary channel reset.
Sep 9 17:42:36 array kernel: hdi: ide_set_handler: handler not null;
old=c01c0840, new=c01bdf30
Sep 9 17:42:36 array kernel: bug: kernel timer added twice at c01c06a8.
Sep 9 17:42:36 array kernel: hdi: ide_set_handler: handler not null;
old=c01bdf30, new=c01bdfa0
Sep 9 17:42:36 array kernel: bug: kernel timer added twice at c01c06a8.
Sep 9 17:43:06 array kernel: hdk: dma_intr: status=0x58 { DriveReady
SeekComplete DataRequest }
Sep 9 17:43:06 array kernel:
Sep 9 17:43:06 array kernel: hdk: status timeout: status=0xd0 { Busy }
Sep 9 17:43:06 array kernel:
Sep 9 17:43:06 array kernel: hdk: DMA disabled
Sep 9 17:43:06 array kernel: PDC202XX: Secondary channel reset.
Sep 9 17:43:06 array kernel: hdk: drive not ready for command
Sep 9 17:43:06 array kernel: ide5: reset: success
Sep 9 17:43:26 array kernel: hdi: dma_intr: status=0x58 { DriveReady
SeekComplete DataRequest }
Sep 9 17:43:26 array kernel:
Sep 9 17:43:26 array kernel: hdi: status timeout: status=0xd0 { Busy }
Sep 9 17:43:26 array kernel:
Sep 9 17:43:26 array kernel: hdi: DMA disabled
Sep 9 17:43:26 array kernel: PDC202XX: Primary channel reset.
Sep 9 17:43:26 array kernel: hdi: drive not ready for command
Sep 9 17:43:26 array kernel: ide4: reset: success
Sep 9 18:07:17 array kernel: hdk: status timeout: status=0xd0 { Busy }
Sep 9 18:07:17 array kernel:
Sep 9 18:07:17 array kernel: PDC202XX: Secondary channel reset.
Sep 9 18:07:17 array kernel: hdk: no DRQ after issuing WRITE
Sep 9 18:07:17 array kernel: ide5: reset: success
Sep 9 19:29:16 array kernel: hdi: status error: status=0x58 {
DriveReady SeekComplete DataRequest }
Sep 9 19:29:16 array kernel:
Sep 9 19:29:16 array kernel: hdi: drive not ready for command
Sep 9 19:36:37 array kernel: hdi: status error: status=0x58 {
DriveReady SeekComplete DataRequest }
Sep 9 19:36:37 array kernel:
Sep 9 19:36:37 array kernel: hdi: drive not ready for command
Sep 9 19:39:18 array kernel: hdi: status error: status=0x58 {
DriveReady SeekComplete DataRequest }
Sep 9 19:39:18 array kernel:
Sep 9 19:39:18 array kernel: hdi: drive not ready for command
Sep 9 19:42:41 array kernel: hdi: status error: status=0x58 {
DriveReady SeekComplete DataRequest }
Sep 9 19:42:41 array kernel:
Sep 9 19:42:41 array kernel: hdi: drive not ready for command
Sep 9 19:42:46 array kernel: hdi: status error: status=0x58 {
DriveReady SeekComplete DataRequest }
Sep 9 19:42:46 array kernel:
Sep 9 19:42:46 array kernel: hdi: drive not ready for command
Sep 9 19:43:09 array kernel: hdi: status error: status=0x58 {
DriveReady SeekComplete DataRequest }
Sep 9 19:43:09 array kernel:
Sep 9 19:43:09 array kernel: hdi: drive not ready for command
Sep 9 19:43:09 array kernel: hdi: status error: status=0x58 {
DriveReady SeekComplete DataRequest }
Sep 9 19:43:09 array kernel:
Sep 9 19:43:09 array kernel: hdi: drive not ready for command
Sep 9 19:44:37 array kernel: hdi: status error: status=0x58 {
DriveReady SeekComplete DataRequest }
Sep 9 19:44:37 array kernel:
Sep 9 19:44:37 array kernel: hdi: drive not ready for command
Sep 9 19:45:01 array kernel: hdi: status error: status=0x58 {
DriveReady SeekComplete DataRequest }
Sep 9 19:45:01 array kernel:
Sep 9 19:45:01 array kernel: hdi: drive not ready for command
Sep 9 19:48:29 array kernel: hdi: status error: status=0x58 {
DriveReady SeekComplete DataRequest }
Sep 9 19:48:29 array kernel:
Sep 9 19:48:29 array kernel: hdi: drive not ready for command
Sep 9 19:48:34 array kernel: hdi: status error: status=0x58 {
DriveReady SeekComplete DataRequest }
Sep 9 19:48:34 array kernel:
Sep 9 19:48:34 array kernel: hdi: drive not ready for command
Sep 9 19:48:39 array kernel: hdk: status timeout: status=0xd0 { Busy }
Sep 9 19:48:39 array kernel:
Sep 9 19:48:39 array kernel: PDC202XX: Secondary channel reset.
Sep 9 19:48:39 array kernel: hdk: no DRQ after issuing WRITE
Sep 9 19:48:39 array kernel: ide5: reset: success
Sep 9 19:55:05 array kernel: hdk: status timeout: status=0xd0 { Busy }
Sep 9 19:55:05 array kernel:
Sep 9 19:55:05 array kernel: PDC202XX: Secondary channel reset.
Sep 9 19:55:05 array kernel: hdk: no DRQ after issuing WRITE
Sep 9 19:55:05 array kernel: ide5: reset: success
Sep 9 19:55:47 array kernel: hdi: status error: status=0x58 {
DriveReady SeekComplete DataRequest }
Sep 9 19:55:47 array kernel:
Sep 9 19:55:47 array kernel: hdi: drive not ready for command
Sep 9 20:04:01 array kernel: hdi: status error: status=0x58 {
DriveReady SeekComplete DataRequest }
Sep 9 20:04:01 array kernel:
Sep 9 20:04:01 array kernel: hdi: drive not ready for command
Sep 9 20:04:08 array kernel: hdi: status error: status=0x58 {
DriveReady SeekComplete DataRequest }
Sep 9 20:04:08 array kernel:
Sep 9 20:04:08 array kernel: hdi: drive not ready for command
Sep 9 20:04:13 array kernel: hdi: status error: status=0x58 {
DriveReady SeekComplete DataRequest }
Sep 9 20:04:13 array kernel:
Sep 9 20:04:13 array kernel: hdi: drive not ready for command
Sep 9 20:04:24 array kernel: hdi: status error: status=0x58 {
DriveReady SeekComplete DataRequest }
Sep 9 20:04:24 array kernel:
Sep 9 20:04:24 array kernel: hdi: drive not ready for command
Sep 9 20:04:42 array kernel: hdi: status error: status=0x58 {
DriveReady SeekComplete DataRequest }
Sep 9 20:04:42 array kernel:
Sep 9 20:04:42 array kernel: hdi: drive not ready for command
Sep 9 20:04:53 array kernel: hdi: status error: status=0x58 {
DriveReady SeekComplete DataRequest }
Sep 9 20:04:53 array kernel:
Sep 9 20:04:53 array kernel: hdi: drive not ready for command
Sep 9 20:05:11 array kernel: hdi: status error: status=0x58 {
DriveReady SeekComplete DataRequest }
Sep 9 20:05:11 array kernel:
Sep 9 20:05:11 array kernel: hdi: drive not ready for command
Sep 9 20:05:39 array kernel: hdi: status error: status=0x58 {
DriveReady SeekComplete DataRequest }
Sep 9 20:05:39 array kernel:
Sep 9 20:05:39 array kernel: hdi: drive not ready for command
Sep 9 20:05:46 array kernel: hdi: status error: status=0x58 {
DriveReady SeekComplete DataRequest }
Sep 9 20:05:46 array kernel:
Sep 9 20:05:46 array kernel: hdi: drive not ready for command
Sep 9 20:06:38 array kernel: hdi: status error: status=0x58 {
DriveReady SeekComplete DataRequest }
Sep 9 20:06:38 array kernel:
Sep 9 20:06:38 array kernel: hdi: drive not ready for command
Sep 9 20:24:13 array kernel: hdk: status timeout: status=0xd0 { Busy }
Sep 9 20:24:13 array kernel:
Sep 9 20:24:13 array kernel: PDC202XX: Secondary channel reset.
Sep 9 20:24:13 array kernel: hdk: no DRQ after issuing WRITE
Sep 9 20:24:14 array kernel: ide5: reset: success
Sep 9 20:26:28 array kernel: hdk: status timeout: status=0xd0 { Busy }
Sep 9 20:26:28 array kernel:
Sep 9 20:26:28 array kernel: PDC202XX: Secondary channel reset.
Sep 9 20:26:28 array kernel: hdk: no DRQ after issuing WRITE
Sep 9 20:26:28 array kernel: ide5: reset: success
Sep 9 21:02:28 array kernel: hdk: status timeout: status=0xd0 { Busy }
Sep 9 21:02:28 array kernel:
Sep 9 21:02:28 array kernel: PDC202XX: Secondary channel reset.
Sep 9 21:02:28 array kernel: hdk: no DRQ after issuing WRITE
Sep 9 21:02:28 array kernel: ide5: reset: success
Sep 9 21:04:58 array kernel: hdk: status timeout: status=0xd0 { Busy }
Sep 9 21:04:58 array kernel:
Sep 9 21:04:58 array kernel: PDC202XX: Secondary channel reset.
Sep 9 21:04:58 array kernel: hdk: no DRQ after issuing WRITE
Sep 9 21:04:58 array kernel: ide5: reset: success
Sep 9 21:55:05 array kernel: hdk: status timeout: status=0xd0 { Busy }
Sep 9 21:55:05 array kernel:
Sep 9 21:55:05 array kernel: PDC202XX: Secondary channel reset.
Sep 9 21:55:05 array kernel: hdk: no DRQ after issuing WRITE
Sep 9 21:55:05 array kernel: ide5: reset: success
now machine#0 hangs at various places during boot.
I had tried other -ac kernels as well as some 2.5.xx. No joy.
Is there any work done lately that may address this(these) problems?
thanks a whole lot,
ryan
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: 3 ultra100 controllers
2002-09-10 23:05 ` T. Ryan Halwachs
@ 2002-09-10 23:38 ` T. Ryan Halwachs
0 siblings, 0 replies; 6+ messages in thread
From: T. Ryan Halwachs @ 2002-09-10 23:38 UTC (permalink / raw)
To: ataraid mailing list
Cc: Alan Cox, Andre Hedrick, kernel mailing list, Jeff Nguyen
On Tue, 2002-09-10 at 16:05, T. Ryan Halwachs wrote:
> kernel: 2.4.29-ac4
Should be 2.4.19-ac4
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2002-09-10 23:37 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2002-09-04 18:19 3 ultra100 controllers T. Ryan Halwachs
2002-09-04 19:48 ` Andre Hedrick
2002-09-04 23:36 ` Alan Cox
2002-09-05 9:05 ` Andre Hedrick
2002-09-10 23:05 ` T. Ryan Halwachs
2002-09-10 23:38 ` T. Ryan Halwachs
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox